JPH0172748U - - Google Patents
Info
- Publication number
- JPH0172748U JPH0172748U JP1987167513U JP16751387U JPH0172748U JP H0172748 U JPH0172748 U JP H0172748U JP 1987167513 U JP1987167513 U JP 1987167513U JP 16751387 U JP16751387 U JP 16751387U JP H0172748 U JPH0172748 U JP H0172748U
- Authority
- JP
- Japan
- Prior art keywords
- bit
- frame
- leading edge
- detecting means
- detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003708 edge detection Methods 0.000 claims description 2
- 238000001514 detection method Methods 0.000 claims 3
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図は本考案の一実施例のシリアルデータ受
信装置の要部回路図、第２図ａ〜ｉは第１図に示
す回路の各部の信号波形図、第３図は従来のシリ
アルデータ受信装置における受信タイミングのず
れを説明する信号図である。
〔符号の説明〕、１……シリアルデータ受信装
置、２……エツジ検出フリツプフロツプ、３……
クロツク発振器、４……シフトレジスタ、５……
ＳＴＩＤカウンタ、６……データ有効フリツプフ
ロツプ、８……負論理入力アンドゲート、９……
アンドゲート、１０……ビツトフレームカウンタ
、１１……データフレームカウンタ。
Fig. 1 is a circuit diagram of a main part of a serial data receiving device according to an embodiment of the present invention, Fig. 2 a to i are signal waveform diagrams of each part of the circuit shown in Fig. 1, and Fig. 3 is a conventional serial data receiving device. FIG. 3 is a signal diagram illustrating a shift in reception timing in the device. [Explanation of symbols], 1... Serial data receiving device, 2... Edge detection flip-flop, 3...
Clock oscillator, 4...Shift register, 5...
STID counter, 6...Data valid flip-flop, 8...Negative logic input AND gate, 9...
AND gate, 10...Bit frame counter, 11...Data frame counter.
Claims (1)
であつて、リーデイングエツジ検出手段と、レベ
ル検出手段と、連続する２以上のビツトフレーム
からなるデータフレームの第１番目のビツトフレ
ームを第２番目以後のビツトフレームと弁別する
ビツトフレーム弁別手段と、第１番目のビツトフ
レームについては前記リーデイングエツジ検出手
段とレベル検出手段の両方の検出出力によりスタ
ートビツトの判定を行うと共に第２番目以後のビ
ツトフレームについては前記リーデイングエツジ
検出手段の検出出力のみによりスタートビツトの
判定を行うスタートビツト判定手段とを具備して
なることを特徴とするシリアルデータ受信装置。 A device for receiving asynchronous serial data, which includes a leading edge detection means, a level detection means, and a data frame consisting of two or more consecutive bit frames. A bit frame discriminating means for discriminating the first bit frame from the frame, and a start bit determination method based on the detection outputs of both the leading edge detecting means and the level detecting means for the first bit frame, and the above described for the second and subsequent bit frames. 1. A serial data receiving device comprising: start bit determining means for determining a start bit only based on the detection output of the leading edge detecting means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987167513U JPH0172748U (en) | 1987-10-30 | 1987-10-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987167513U JPH0172748U (en) | 1987-10-30 | 1987-10-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0172748U true JPH0172748U (en) | 1989-05-16 |
Family
ID=31455878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987167513U Pending JPH0172748U (en) | 1987-10-30 | 1987-10-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0172748U (en) |
-
1987
- 1987-10-30 JP JP1987167513U patent/JPH0172748U/ja active Pending
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