JPS586484U

JPS586484U - Monitoring operation panel signal input/output device

Info

Publication number: JPS586484U
Application number: JP8564182U
Authority: JP
Inventors: 坂根　忠俊; 小竹　伸行
Original assignee: 株式会社明電舎
Priority date: 1982-06-09
Filing date: 1982-06-09
Publication date: 1983-01-17
Also published as: JPS622856Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来の監視操作パネルの信号入出力方式を示す
ブロック図、第２図は本考案の一実施例を示すブロック
図、第３図、第４図は第２図における信号伝送フォーマ
ットを示す図、第５図は第２図における制御回路の一実
施例を示す回路図、第６図は第５図の動作を説明するた
めの波形図、第７図は第２図における入出力装置の一実
施例を示すブロック図である。１・・・・・・監視操作パネル、３−・・・・・・デー
タ処理部、４・・・・・・入出力装置、＃１．＃Ｎ・・
・・・・選択スイッチ、Ｃ０，Ｃ−・・・・・・制御回
路、６□、６゜・・・・・・結合回路、７・・・・・・
信号線、８・・・・・・スタート検出回路、９・・・・
・・計数器、１０・・・・・・クロック検出器、１１・
・・・・・長符号検出器、１２・・・・・・アドレス設
定器、１３・・・・・・一致回路、１４・・・・・・分
配器、１５．１６・・・・・・ラッチ回路、１７．１８
・・・・・・結合回路、１９．２２・・・・・・アンド
ゲート、２０・・・・・・結合回路、２１・・・・・・
オアゲート、２３・・・・・・タイマ回路、３０．３１
・・・・・・結合回路、３２・・・・・・ＣＰＵ０Fig. 1 is a block diagram showing the signal input/output method of a conventional monitoring operation panel, Fig. 2 is a block diagram showing an embodiment of the present invention, and Figs. 3 and 4 show the signal transmission format in Fig. 2. 5 is a circuit diagram showing an example of the control circuit in FIG. 2, FIG. 6 is a waveform diagram for explaining the operation of FIG. 5, and FIG. 7 is an input/output device in FIG. 2. FIG. 2 is a block diagram showing one embodiment of the present invention. 1... Monitoring operation panel, 3-... Data processing unit, 4... Input/output device, #1. #N...
...Selection switch, C0, C-...Control circuit, 6□, 6゜...Coupling circuit, 7...
Signal line, 8...Start detection circuit, 9...
...Counter, 10...Clock detector, 11.
...Long code detector, 12... Address setter, 13... Match circuit, 14... Distributor, 15.16... latch circuit, 17.18
・・・・・・Coupling circuit, 19.22・・・・・・AND gate, 20・・・・Coupling circuit, 21・・・・・・
OR gate, 23... Timer circuit, 30.31
......Combination circuit, 32...CPU0

Claims

[Scope of utility model registration request]

In transmitting and receiving signals between a large number of indicator lights and switches provided on the monitoring operation panel and the data processing section, each selection switch group including at least one of the indicator lights and switches receives the data via a control circuit. It is connected to the input/output device of the processing section through 1 to 3 pairs of common signal lines, and the signal lines are connected to the indicator lights of the selection switch group and the signals of the switches, including the start signal, as pulse train signals divided in time. give,
The control circuit matches a counter that starts counting the number of pulses of the pulse train signal with the start signal and address data that sets the contents of the upper digits of this counter in detail for the selection switch group. A matching circuit for detecting, a distributor for capturing and decoding the lower digit content of the counter at the matching output timing of the matching circuit, and a data timing output of the selection switch obtained by the distributor to output one of the pulse train signals. drive circuit means for reading the sign detection signal of the indicator light control pulse to obtain a drive signal for the indicator light; and a data timing output of the distributor to determine the state of the switches in the pulse train signal and confirmation control pulse timing for the switches. and drive circuit means for obtaining a status and confirmation signal and sending it to the signal line, and for controlling the corresponding indicator lights and switches by temporally distinguishing the input signals of the signals for the indicator lights and switches. Features a signal input/output device for the monitoring operation panel.