JPS5834187U - display circuit - Google Patents
display circuitInfo
- Publication number
- JPS5834187U JPS5834187U JP12906081U JP12906081U JPS5834187U JP S5834187 U JPS5834187 U JP S5834187U JP 12906081 U JP12906081 U JP 12906081U JP 12906081 U JP12906081 U JP 12906081U JP S5834187 U JPS5834187 U JP S5834187U
- Authority
- JP
- Japan
- Prior art keywords
- display
- display mode
- control signal
- output port
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Digital Computer Display Output (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案による表示回路の一実施例を示す回路図
、第２図ａ”Ｊｓ、第３図ａ ”ｊｓは第１図に示す回
路の各部動作波形図である。
−１・・・・・・波形整形回路、２・・・・・・中央演
算装置、３ａ〜３ｄ・・・・・・シフトレジスタ、４ａ
〜４Ｃ・・・・・・ゲ ゛−ト、５・・・・・・バー
グラフ表示装置。FIG. 1 is a circuit diagram showing an embodiment of the display circuit according to the present invention, and FIG. 2 a"Js and FIG. 3 a"js are operation waveform diagrams of various parts of the circuit shown in FIG. 1. -1...Waveform shaping circuit, 2...Central processing unit, 3a to 3d...Shift register, 4a
~4C...Gate, 5...Bar graph display device.
Claims (1)
出力ポートからシリアルパルス列のパルス数によって表
わされる表示情報を予め定められた更新周期に対応して
発生し、第３出力ポートから第１クリア信号を発生する
中央演算装置と、前記中央演算装置から出力される表示
情報をそれぞれクロック入力とする複数個のシフトレジ
スタが縦続接続され、かつ前記表示モード制御信号を前
記初段シフトレジスタのシフト入力とするシフトレジス
タ部と、前記各シフトレジスタの最上位を除く上位の隣
接する２信号の不一致を検出して次段の前記シフトレジ
スタを順次クリアするゲート回路と、前記シフトレジス
タ部の各出力によってそれぞれ駆動される表示セグメン
トが複数個並設されたバーグラフ表示装置とを備え、前
記表示モード制御信号はバーグラフ表示モードに於いて
は前記表示情報の送出期間に疲いてすべてアクティブレ
ベルとなり、ポイント表示モードに於いては前記表示情
報を構成するシリアルパルス列の少なくとも第１パルス
を含む連続した所定パルス期間のみアクティブレベルと
なる信号によって構成され、前記第１クリア信号は表示
情報の送出に先立って発生さることを特徴とする表示回
路。A display mode control signal is generated from the first output port, and a display mode control signal is generated from the second output port.
a central processing unit that generates display information represented by the number of pulses of a serial pulse train from an output port in accordance with a predetermined update cycle, and generates a first clear signal from a third output port; and an output from the central processing unit. A plurality of shift registers are connected in cascade, each receiving the display information to be displayed as a clock input, and excluding a shift register section in which the display mode control signal is used as a shift input of the first stage shift register, and a topmost part of each of the shift registers. A bar graph display including a gate circuit that detects a mismatch between two upper adjacent signals and sequentially clears the shift register at the next stage, and a plurality of display segments arranged in parallel, each driven by each output of the shift register section. In the bar graph display mode, the display mode control signal is tired from the sending period of the display information and becomes active level, and in the point display mode, at least one of the serial pulse trains constituting the display information is set to an active level. 1. A display circuit comprising a signal that is at an active level only during a predetermined continuous pulse period including a first pulse, and wherein the first clear signal is generated prior to sending display information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12906081U JPS5834187U (en) | 1981-08-31 | 1981-08-31 | display circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12906081U JPS5834187U (en) | 1981-08-31 | 1981-08-31 | display circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5834187U true JPS5834187U (en) | 1983-03-05 |
| JPS6328468Y2 JPS6328468Y2 (en) | 1988-08-01 |
Family
ID=29922738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12906081U Granted JPS5834187U (en) | 1981-08-31 | 1981-08-31 | display circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5834187U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11296140A (en) * | 1998-04-15 | 1999-10-29 | Mitsubishi Electric Corp | Device and method for driving plasma display panel |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5476630U (en) * | 1977-11-10 | 1979-05-31 | ||
| JPS5517436A (en) * | 1978-07-24 | 1980-02-06 | Seiko Epson Corp | Bar graph drive circuit |
-
1981
- 1981-08-31 JP JP12906081U patent/JPS5834187U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5476630U (en) * | 1977-11-10 | 1979-05-31 | ||
| JPS5517436A (en) * | 1978-07-24 | 1980-02-06 | Seiko Epson Corp | Bar graph drive circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11296140A (en) * | 1998-04-15 | 1999-10-29 | Mitsubishi Electric Corp | Device and method for driving plasma display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6328468Y2 (en) | 1988-08-01 |
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