JPS5978740U

JPS5978740U - electronic counter

Info

Publication number: JPS5978740U
Application number: JP17353582U
Authority: JP
Inventors: 耕一藤井
Original assignee: オムロン株式会社
Priority date: 1982-11-18
Filing date: 1982-11-18
Publication date: 1984-05-28

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は電子カウンタを用いた位置表示装置の１例を示
す模式図、第２図は本考案の１実施例に係る電子カウン
タのブロック構成図、第３図は第′　２図の電子カウン
タ各部の動作信号のタイミングチャート、第４図は第２
図における倍数回路４お　−よび倍数設定器５部分のよ
り詳細なブロック図、そして第５図は第２図の電子カウ
ンタめ外観図である。１・・・入力回路、−２・・・カウント回路、３・・・
表示器、４・・・倍数回路、５・・・倍数設定器、６・
・・ＲＳフリップフロップ、７・・・Ｄフリップフロッ
プ、８・・・発振回路、９・・・ＢＣＤレイトマルチプ
ライア。リｔ！−ｔｔ−Ｊ　　Ｌ−−−一−−−−−−−叶　　
−ｆｆｉ口］− ＤＯＷＮ　　−一一一一一一一」− 表装　　−一一中一一一で−一一−Fig. 1 is a schematic diagram showing an example of a position display device using an electronic counter, Fig. 2 is a block diagram of an electronic counter according to an embodiment of the present invention, and Fig. 3 is a schematic diagram showing an example of a position display device using an electronic counter. The timing chart of the operation signals of each part, Figure 4 is the 2nd
A more detailed block diagram of the multiplex circuit 4 and multiple setter 5 in the figure, and FIG. 5 is an external view of the electronic counter shown in FIG. 2. 1...Input circuit, -2...Count circuit, 3...
Display unit, 4... Multiplier circuit, 5... Multiplier setter, 6.
...RS flip-flop, 7...D flip-flop, 8...oscillator circuit, 9...BCD rate multiplier. Lit! -tt-J L----1----Ko
-ffi mouth] - DOWN -111111" - Mounting -11 middle 111 de -11-

Claims

[Scope of utility model registration request]

An addition/subtraction type electronic counter comprising a count circuit that increases or decreases the number of pulses of a count signal consisting of up count pulses and down count pulses according to the count signal, and a display circuit that displays the counted value of this count circuit. A multiplier circuit that generates n (n is an integer) pulses every time one of the count signals is generated is provided in the front stage of the circuit, and the count signal is increased or decreased by n for each count signal. Features an electronic counter.