JPS60158338U

JPS60158338U - counter device

Info

Publication number: JPS60158338U
Application number: JP4568184U
Authority: JP
Inventors: 竹村　茂章
Original assignee: 小谷電機株式会社
Priority date: 1984-03-28
Filing date: 1984-03-28
Publication date: 1985-10-22

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示すブロック図、第２図は
第１図のブロック図の動作を示す流れ線図である。１・・・クロック信号発生回路、２・・・第１のカウン
ター、３・・・初期値設定回路、４・・・第２のカウン
ター、５・・・入力端子、６・・・表示部。FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a flow diagram showing the operation of the block diagram of FIG. DESCRIPTION OF SYMBOLS 1... Clock signal generation circuit, 2... First counter, 3... Initial value setting circuit, 4... Second counter, 5... Input terminal, 6... Display section.

Claims

[Claims for Utility Model Registration] A clock signal generation circuit for generating a reference clock signal, a first counter for counting the reference clock signal, and setting an arbitrary initial value to the first counter. and an initial value setting circuit for starting counting of the measured value applied from the input terminal at the same time as the first counter starts counting, and starts counting the measured value applied from the input terminal in a direction opposite to the counting direction of the first counter, and ends the counting of the first counter. a second counter that ends counting at the same time as the second counter; and counting of the second counter. A counter device comprising a display section for displaying results.