JPS62150924A - N-train pulse detector - Google Patents

Abstract

PURPOSE:To reduce the number of pulse detection circuits by using a couple of gates so as to obtain AND and OR results and using a flip-flop so as to latch them thereby generating state information. CONSTITUTION:A couple of gates 11, 12, the 1st and 2nd flip-flops 13, 14 and a pulse detection circuit 15 are provided. A couple of the gates consist of an AND gate 11 and an OR gate 12, to which N-series of pulses are inputted at the same time to obtain the AND and OR logic. The 1st flip-flop 13 executes 1/2 frequency division by the output of the AND gate 11. The 2nd flip-flop 14 is operated by using an output of the OR gate 12 as a clock input and generates a pulse train detection signal and outputs from the output of the 1st flip-flop 13. A pulse detection circuit 15 detects a pulse train from the pulse train detection signal and recognizes it. Thus, even when the number of pulse trains is may, the number of the pulse detection circuits is reduced thereby simplifying the circuit constitution.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention provides an N
The present invention relates to a train pulse detection device.

(Prior Art) Conventionally, when detecting N columns of pulse trains, a circuit configuration has been adopted in which an independent pulse detection circuit is provided for each column and each pulse detection circuit detects a pulse.

FIG. 8 is a block diagram showing an example of a conventional N-series pulse detection device. In Figure 8, 28.26
are each a pulse detection circuit.

In FIG. 8, each pulse train is connected to input terminal 23.2.
4 and are added to pulse detection circuits 25 and 26, respectively.

(Problems to be Solved by the Invention) The configuration of the conventional pulse train detection device described above requires as many pulse detection circuits as there are pulse trains, so it has the disadvantage that the circuit configuration becomes complicated as the number of pulse trains to be detected increases. .

An object of the present invention is to obtain the logical product and logical sum using a pair of gates consisting of an AND gate and an OR gate, and generate state information by latching the logical product and logical sum using a Noritub flop. It is an object of the present invention to provide an N-series pulse detection device configured to eliminate the drawbacks and reduce the number of pulse detection circuits.

(Means for solving the problem) The N-column pulse detection device according to the present invention includes a pair of gates,
The device includes first and second flip-flops and a pulse detection circuit.

The pair of gates consists of an AND gate and an OR gate,
This is for calculating logical products and logical sums by simultaneously inputting N columns of pulses.

The first flip-flop is for performing a divide-by-two operation using the output of the AND gate.

The second flip-flop operates using the output of the OR gate as a clock input, and is used to generate and output a pulse train detection signal from the output of the first flip-flop.

The pulse detection circuit detects and recognizes a pulse train using a pulse train detection signal.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an N-sequence pulse train detection device. In FIG. 1, ll is an AND gate,
12 is an OR gate, 13 is a first flip flora 7',
14 is a second flip-flop, and Ig is a pulse detection circuit.

FIG. 2 is a timing chart showing signal waveforms at various parts in the N-column pulse train detection device shown in FIG. 1.

In FIGS. 1 and 2, when pulse trains are applied to signal line 18, 17, these pulse trains are input to AND gate 11 and OR gate 12. AND game)
11 generates a logical product of the above pulse trains and outputs it onto a signal line 18. The OR gate generates the logical sum of the above pulse trains and generates the signal #! Output on 19. The pulse train on the signal line 18 is input to the clock terminal CL of the first 7-lip 70 tube 13, and the frequency is divided by 2 to produce an output pulse train.
is output above. The pulse train on the signal line 21 is applied to the D input terminal of the second flip-flop 14, and the pulse train sent from the OR gate 12 onto the signal line 19 is input to its clock terminal CL.

The pulse train output from the second flip-flop 14 onto the signal line 22 is input to the pulse detection circuit 15 as a pulse train detection signal.

When the pulse train on signal lines 16 and 17 is normal,
A pulse train appears at the Q output terminal of the second flip-flop 14 and is detected and recognized by the pulse detection circuit 15.

If even one pulse train on the signal line 16,1 is disconnected and the output of the first flip-flop 13 is held at %1g, the pulse train output sent from the first flip-flop 13 onto the signal line 21 will be 111, and the pulse train on the signal line 22 is cut off.

On the other hand, when the pulse trains on the signal lines 16 and 17 are both cut off and the output of the first flip 70 knob 13 is held at 10I, the pulse train output sent from the OR gate 12 onto the signal line 19 becomes %Ol. Therefore, the pulse trains on signal lines 21 and 22 are both cut off.

(Effects of the Invention) As explained above, the present invention generates a large number of pulse trains by calculating the logical product and the logical sum using a pair of gates, and latching these values using a flip-flop to generate state information. However, the number of pulse detection circuits can be reduced, and the circuit configuration can be simplified.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an N-column pulse detection circuit according to the present invention. FIG. 2 is a timing diagram showing an example of the operation of the N-column pulse detection circuit shown in FIG. FIG. 8 is a block diagram showing an example of an N-column pulse detection circuit according to the prior art. 11...AND gate 12-...OR gate 13.14.e.Flip-flop 15.25, 26...Pulse detection circuit 16-22...
e signal line 23.24...terminal

Claims (1)

[Claims] A pair of gates consisting of an AND gate and an OR gate for simultaneously inputting N rows of pulses to obtain a logical product and a logical sum, and a first flip-flop for performing a divide-by-2 operation using the output of the AND gate. a second flip-flop that operates with the output of the OR gate as a clock input and generates and outputs a pulse train detection signal from the output of the first flip-flop; and a second flip-flop that detects a pulse train using the pulse train detection signal. What is claimed is: 1. An N-series pulse detection device comprising: a pulse detection circuit for recognizing an N-series pulse;