JPS60164257A - Pulse width measuring apparatus - Google Patents

Abstract

PURPOSE:To measure a small pulse width with a clock signal by holding outputs of a delay line group for delaying the clock signal at the time of starting and ending an unknown pulse signal. CONSTITUTION:Delay lines 7a-7d output a clock signal 4 delayed by one-fifth the cycle of each thereof 4. The signal 4 and delayed clock signals 17a-17d outputted from the delay lines 7a-7d are applied to data inputs of latches 8a-8j. A pulse signal 5 with an unknown pulse width is inputted into a driver 9, which outputs a latch pulse 14a at the rising time of the signal 5 while a latch pulse 14b at the falling time thereof. Outputs of the latches 8a-8j are applied to an address terminal of a ROM10, a phase signal 11 as output of the ROM10 is added to the lower word of a signal of a counter 3 to obtain a pulse width signal 13 having a resolving power equivalent to one-tenth the cycle of the signal 4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse width measuring device used, for example, in a laser distance measuring device.

First, a conventional C seed device will be explained.

In Figure 1, (1) is a clock generation circuit, (2) is a gate, (3) is a counter, (4) is a clock signal, (
5) is a pulse signal, and (6) is a count value. Next, the operation of this device will be explained. The clock generation circuit +11 outputs all the clock signals (4) with a constant frequency, and the gate (
2). On the other hand, a pulse with an unknown pulse width (No. F (5)) is applied to the gate (2) I/C,
The clock signal (4) is switched to the time width of the pulse signal (5) and output to the counter (3) - The counter (3) counts the number of pulses output from the gate (2) and completes counting. It is then output as a digital count value signal (6). The above count value signal (6) is a pulse signal (5)
Since it is proportional to the pulse width of , the pulse width can be measured.

By the way, in this type of device, if you want to increase the resolution of pulse width measurement to improve accuracy.

The clock signal output from the normal clock generation circuit (1) (
For all 410 frequencies, ζ1 is performed. However, if the frequency of the clock signal (4) is increased completely, the counter (3) K is required to have high-speed responsiveness.

This invention uses all counters that operate at the same speed.4. Higher resolution pulse width's: 1lllll
This is to propose a fixed value for the pulse 11ii+ all fixed values.

Hereinafter, a simple embodiment of the present invention shown in FIGS. 2 and 3 will be described. In Fig. 2, (1) to (6) are Tftls (7a) which have the same function and name as each part of the conventional example.
), (7b), (7C), (7d) are delayed fa
n + (8a) to (8j) are latches, (9: is a driver, utn is f(OM), (ill is a phase (A-'
4i, f12 is the addition circuit, OJ is the pulse width i, (
14a) (171b) are latch pulses, (15a) to (
15θ) is the starting phase No. 111, (16a) to (16θ)
is the end phase signal, (17a).

(17b), (17Q), and (17d) are delayed clock signals.

Next, I will explain the operation. In Kaku 2 diagram, (1)
The parts consisting of (6) to (6) have the same functions and operations as the conventional example. Slow'1LnAJ (7a) * (7b)
+ (70), (7”) Hakurok Shin 4ji-14
1 are each delayed by one period of the clock signal (41 itself) and output.The clock signal (41 and the delay h'i 0a)
, (7b) , (yc), , (yd) output delayed clock signal (17a) , (17b) ,
(17c), (17(1) is the latch (8a) to (8
j) is applied to the theta human power. On the other hand, a pulse signal (5) with an unknown pulse width is input to the driver (9), and the driver (9) outputs a 1itIK latch pulse (i4a) f at the rising edge of the pulse signal (5), and at the falling edge of the pulse signal (5). A latch pulse (141:+) is output at time t2. Therefore, the latch (8a) to (8 is the clock signal at the rising time t1 of the pulse signal (5) (
4) and delayed clock signals (17a) to (17d). )'(z will be latched. FIG. 3 is a diagram explaining the above operation.

al is the clock signal 141.al in FIG. a2~
a5 are the delayed clock signals (17a
) to (17d) correspond to FC. It can be seen that by latching at the full signal times of a1 to a5, a bit pattern indicating ALK can be obtained. In this case, the clock signal (
It can be seen that the resolution is 1/10 of 410 cycles. Therefore, in Figure 2, the latch (8a) ~ (start phase signal (159 ~ (15 is the pulse signal
) is the phase of the clock signal (4) at the rising time of The phase of the signal (41) is shown.

The start phase signals (15a) to (15a) and the end phase signals (16a) to (16e) are applied to the address terminals of the ROMH.The phase signal θ1, which is the output of the ROM controller, is
The clock signal (410) between the rising and falling edges of the pulse signal (5) is a phase signal (Ii, counter (3)) that outputs the phase difference in complement representation.
By adding it to the lower word of the division value signal (6) which is the output of , a pulse width signal On having a resolution equal to 1/10 of the period of the clock signal +41 is obtained.

Note that in the above explanation, the resolution is shown in the case of a clock signal (1-0 with a period of 41), but if the resolution is 1-0 with a period of 41,
d) and by increasing the number of stages of latches (8a) to (8j), it is possible to obtain a pulse width of 1$111 with a desired resolution.

As described above, the present invention has the effect that it is possible to easily realize pulse width measurement with higher resolution than the conventional method.

[Brief explanation of the drawing]

Is Figure 1 the conventional pulse width? Is Fig. 2, a diagram showing an example of a 1+1 constant device, an embodiment of this invention? The configuration diagram shown. FIG. 3 is a diagram for explaining the present invention in detail, in which (1) is a clock generator circuit, (2) is a clock generator circuit,
is a counter, (4) is a clock signal, and (5) is a pulse signal. (6) is the count value signal, (7a) to (7(1) is the delay 1
13. (8a) to (8j) are latches, (9) are drivers, and ULJ-ROM. (Ill is a phase signal, Qz is an adder circuit, and 031 is a pulse width signal. (14a) and (Mb) are latch pass/l/spins. , (15a
) ~ (15 is the start phase signal, (169 ~ (16 is the end phase signal. (17a) ~ (17d) are the delayed clock signals. In the figure, the same or equivalent parts are given the same reference numerals. This is indicated by C. Agent Masu Oiwa 1st month

Claims (1)

[Claims] In the pulse width constant device 6111, which measures the pulse time width of the unknown pulse signal, the counter is equipped with a counter that counts a fixed frequency clock signal by the time that a pulse signal of an unknown pulse width is applied. a group of delay lines that completely delay the clock signal; a group of edges that has a function of holding each output of the delay line group at each of the start time and end time of the unknown pulse signal; and an output sound of the latch group. 1. A pulse width measuring device, comprising means for extracting the output of the counter using the pulse width signal to obtain a pulse width + 1111 constant resolution smaller than the period of the clock signal.