SU428544A1 - DEVICE FOR TEMPORARY COMPRESSION INPUT SIGNAL - Google Patents

Description

one

The invention relates to the field of automation and calculators and is intended for analyzing signals in real time, matching the signal bandwidth with the transmission bandwidth of the analyzing equipment, and so on.

The known device is auth. St. No. 253456 has a good teraturic stability.

The purpose of the invention is to improve the device’s thermal stability.

To do this, in the feedback loop of each megaprocessing delay line, additionally enter a single-bit buffer register, the control inputs of which are connected to the output of the additionally introduced pulse distributor, whose input is connected to the output of the clock pulse generator.

FIG. 1 and the block diagram of the proposed device; in fig. 2 - block diagram .ma distributor (frequency divider); in fig. 3 - diagrams of the distributor; in FIG. 4 is a block diagram of one nanosecond lam- ity channel entering the memory block; in fig. 5 is a block diagram of a unit; in fig. 6 - diagram of the buffer register.

The proposed device consists of a converter / aialog-code, the output of which is connected to the input of memory block 2, made on magnetic delay lines, the feedback circuit of which includes single-digit buffer registers 3. The outputs of buffer registers 3 are connected to the inputs of code-converters analogue 4. The inverter 1 adjusts the analogue code and buffer registers 3 by control block 5, to the input of which the frequency of a 6-clock pulse from a stable (for example, quartz) geyerator is Approximately 5 drives are connected to the converter / analog-code and memory block 2.

In block 5 of the control unit, there is a frequency divider that generates control impulses that ensure synchronous stable operation of the multi-channel compression device. The frequency of the generator 6 is determined by the frequency of the samples at the output of the block 2 us the possible departure of the time delay lines

in terms of providing compensation for this care by the buffer register. To ensure the work of the buffer register, the frequency of the generator 6 must be no less than 4 times the frequency of the compressed samples at the output

delay lines of each channel. Thus, at the frequency divider in the control unit 5 at least four clock series shifted one with respect to the other are formed, the frequency of the pulses of each

equal to the nominal sampling frequency pa output of the delay lines. Such series can be obtained on an annular shift register, to the input of which the frequency of the oscillator 6 is fed (Fig. 2), where 7, 8, 9, 10 are the regressor bits of the shift; //, 12, 13, 14 - distributor output buses (Fig. 2).

Each memory channel (Fig. 4) of a multichannel compression device included in memory block 2 and consisting of an electronic key 15, a magnetostrictive delay line 16 and a one-bit buffer register 3, which is made up of triggers 17, 18 and circuits matches 19, 20.

The converter / analogue code is connected to terminal 21. The recording terminal 22 and the reading terminal 23 are connected to the control unit 5. 24 - output to the converter 4 code-analogue; // - 14 - tires connected to the respective distributor wands.

The control BvioK 5 consists of an electronic switch 25, a magnetostriction delay line 26, triggers 27, 28, 29, 30, and a matching circuit 31 and 32.

The triggers 27, 28 and the matching schemes 31, 32 form the EUT from the buffer register, similar to the buffer register 3, which compensates for the delay time decreasing with temperature.

Record terminal 33 and erase terminal 34 are connected to memory block 2.

By contact 35 (FIG. 5), via key 25, a single pulse is pulsed into the control magnetostriction delay line 26, which circulates through the circuit, passing through the buffer register and the shift register, performed on the flip-flops 29, 30, which is an additional element of delay by one bit and providing the operation of the delay line 26 in the “nam” mode, when the delay line 26 in terms of the memory volume is similar to the delay line 16 of each channel of the memory block.

The control signals "write and erase" removed from the trigger 30 provide for reading information from the converter / analogue code and entering it into the magnetostrictive delay lines of the memory block 2 through keys similar to key 15 in the diagram (Fig. 4) and prohibit the regeneration circuit of the magnetostriction delay line 16 at the moment of entering information, which results in erasing the old information.

The pulses circulating along delay line 26, as well as sampling of the input signal in the delay lines of the memory block, fluctuate with time due to the instability of the delay time of the lines. The inclusion in the feedback circuit of one-bit buffer registers allows stabilizing the temporal position of the circulating samples at the output of the buffer register, despite the change in the delay time of the delay lines during operation.

A sample from the output of the delay line (for example, 16, Fig. 4) writes information to the trigger 18, which provides the control potential to the input of the coincidence circuit 20, the second input of which is supplied with a series of clock pulses from the bus 13. Thus, at the output of the coincidence circuit 20 Wits pulse, and in a strictly defined cycle of the fs series of the bus 13 in the presence of a resolving potential on the trigger 18. Since the clock series / 4 is applied to reset the trigger / 5 from a strip 14, then later on the output of the coincidence circuit 20 pulses will not be the arrival of the next sample from the lin output and delay 16. The pulse from the output of the coincidence circuit 20 sets the trigger 17 to the state allowing the clock fi to pass from the bus // through the coincidence circuit 19, and since the trigger 17 is reset by the clock series / from the bus 12, then the output of the coincidence circuit 19 there will always be only one pulse per clock corresponding to the clock series f of bus 11, for each incoming sample to the input of the one-bit buffer register 3 from the output of delay line 16. The buffer registers in each channel of the multi-channel compression device work in the same way. The timing diagram, “ascertaining the operation of the buffer register, is shown in FIG. 6

From the timeline and the above

 Explanation of the work of the buffer register shows that the possible interval for changing the line delay time from the value of Hzp, in which this care can be compensated with a single-bit buffer register 5, controlled by the frequencies formed on the frequency divider, lies within the rear of the clock pulse / 4 front from the bus 14 to the leading edge of the fs clock pulse from the bus 13.

0 From the timing diagram it can be seen that this interval is not symmetrical with respect to the clock series f since the //. By setting the oscillator frequency greater than 4 times the sampling frequency with the implementation, you can extend the allowable interval and make it symmetric with respect to the clock series fi. If we consider that the sample at the output of the delay line 16 has a finite duration, and the system of digital elements is sufficiently fast, then the tolerable limit of the change of the delay time of the delay line 16, compensated with a single-bit buffer register 3, can be further increased and in the limit tends to the period following up

5 samples at the output of the compression device.

Subject invention

A device for temporary compression of the input signal according to the ed. St. No. 253456, characterized in that, in order to increase the temperature stability of the device, a one-time buffer register is additionally inserted in the feedback circuit of each magnetostriction delay line, the control inputs of which are connected to the output of the additionally introduced pulse distributor, whose input is connected to the output of the generator clock speeds.