SU1721627A1 - Method of and device for magnetic recording of digital data - Google Patents

Abstract

This invention relates to digital magnetic recording. The purpose of the invention is to increase the recording density by reducing intersymbol distortion. A two-phase signal is fed to the recording head, into which the predistortion is inserted, consisting in the fact that in sections of a pulse sequence consisting of successive or more pulses of duration T (T is the transmission time of one bit of information), - at the expense of the previous and the penultimate one is shortened by the same time interval due to the subsequent one; m is chosen from the interval from 7 to 14 depending on the amount of intersymbol distortion in the response of the path of the recording device to the original two-phase signal. In the event that only two opposite-polarity pulses of duration T follow each other, the first one is shortened on both sides. In order to better match the path of the recording device with the signal spectrum, it is possible to fill the sections in the initial two-phase signal filled with a frequency meander, a meander of higher frequency where. 2 sec. item f-ly, 2 ill.

Description

This invention relates to digital magnetic recording (CMZ) and can be used to create mass storage devices.

The aim of the invention is to increase the recording density by reducing intersymbol distortion.

FIG. 1 shows timing charts of the recording and playback signals; in fig. 2 - block diagram of the CMZ device.

The diagrams shown (Fig. 1) characterize an arbitrary information sequence (Fig. 1a), its presentation by codes without returning to

zero (BVN-1) (Fig. 16), the result of converting it into two-phase codes (Fig. 1c).

In the intervals containing two or more successive pulses of duration T, the first and the penultimate of

they are shortened by a value - by lengthening the previous and the last. If there are only two pulses of duration T, then the first one is shortened by this value from the front and from the rear (Fig. 1 g).

To compensate for large intersymbol distortions (ISI) by a small amount does not make sense, and to compensate for small ISIs that do not affect the accuracy of the reading is impractical. The preferred integer values of m (especially), since frequencies that are multiples of the clock, are the easiest to obtain (Fig. 1r,). An example of the path response to this signal is shown in FIG. 1e

A device for implementing the recording method (Fig. 2) includes the first element EXCLUSIVE OR 1 and the logical key 2 and 2, also contains the second 3, third 4, fourth 5, fifth 6 and sixth 7 elements EXCLUSIVE OR, delay unit 8 at time T / t, a four-bit shift register 9 and two synchronous D-flip-flops 10 and 11, triggered by a positive clock signal, a two-position switch 12 and a 3-ZI-2IL logic circuit 13.

The information register 9 serves the initial information sequence, presented in the BVN-type, at the clock frequency-meander of the clock frequency. On the delay unit the arrival of t BVN-copy of the source information from the second output of the shift register, the square wave clock frequency from the input

| /; .

devices and frequency meander. By work

the unit controls the frequency signal from input

device, which also enters the synchronous input of the D-flip-flop 10.

The device (Fig. 2) works as follows.

The information BVN signal is fed to the data input of the shift register 9 and, under the control of the clock signal, is written into it and shifted to the right. Thus, at the outputs a, b, c, d (a - the first, b - three, c - the third, d - the fourth) of the register, copies of the information signal appear, delayed in time relative to the original at intervals T, 2T, 3T and 4T respectively. From the copy from the output b of the register, a two-phase signal is formed as follows: The filling window forms the D-flip-flop 11, the Window signal

opens key 2 and delivers the square wave clock

K frequency or frequency depending on

the position of the switch 12 to the input element EXCLUSIVE OR 6, which compensates for the filling phase. Thus obtained two-phase signal has

time delay - relative to copy b,

necessary to temporarily reconcile parts of the device.

The EXCLUSIVE OR 1 element generates pulses for shortening the current pulse of a two-phase code by lengthening the next, and D-flip-flop 10 by delaying

of this impulse for time - forms img

pulses shortening the current due to the previous one. These pulses affect the two-phase signal on condition that they pass through the corresponding gates in circuit 13 controlled from the outputs of the EXCLUSIVE OR 3-5 elements that perform the original modulo 2 summaries of the BVN signal from the a, b, c, d registers 9. The procedure for lengthening the shortening is implemented by the element EXCLUSIVE OR 7, the output of which is the output of the device. Due to their very short duration, the needles present in the recording signal at the output of the device are not perceived by the path, and if necessary, they can be easily eliminated by connecting a synchronous D-trigger synchronized

frequency meander. Total delay

introduced by the device during the transfer of information (1 + t) of the T mation, is -i - "-.

Claims (2)

1. A method of magnetic recording of digital information, including the supply to the recording head of sequences of rectangular pulses of constant amplitude and duration T, characterized in that, in order to increase recording density by reducing intersymbol distortion, the first of two or more successively different polar polarities pulses of duration T are formed with a duration of less than the time T / T due to an increase in the duration of the previous pulse, and the duration of the penultimate pulse is reduced by the same interval due to increase the duration of the last pulse, and the value of m is chosen as an integer from the interval from 7 to 14. 2. A device for magnetic recording of digital information, containing two triggers, two elements EXCLUSIVE OR, one input of the first of which is connected to the output of the element I, which means that in order to increase the recording density , between the output bus and the first element EXCLUSIVE OR the third element EXCLUSIVE OR is connected, the second input of which is connected to the output of the ZI-2ILI element, the first three inputs of which are connected respectively to the outputs of the fourth, fifth and second elements EXCLUSIVE OR, and the second three inputs to exits of this and the fifth elements EXCLUSIVE OR and the first trigger, the inputs of the fourth, second and sixth elements EXCLUSIVE OR connected respectively to the outputs of the first and third, second and second detainees in the delay unit, second and fourth bits of the register connected to the information and synchronization buses, the inputs of the fifth element EXCLUSIVE OR are connected to the outputs of the fourth and sixth elements EXCLUSIVE OR, D- inputs Triggers are connected to the output of the second element EXCLUSIVE OR, and their C-inputs are connected to the bus by a meander 0 clock frequency and through the delay unit - with the synchronization bus, respectively, the inputs of the And element are connected to the inverse output of the second trigger and through the switch and the delay unit - to the synchronization bus and the square wave TO the clock frequency is where the values of m and K are chosen from integers in the range from 7 to 14 and from 2 to 5, respectively. 0 7.0. 7 7 ABOUT . one . 7 7 Oh. ABOUT . ABOUT . About .0. ten 6 J-LT-U1 Phia.1 FIG. 2