JPH01501752A - High speed data clock synchronous processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] High speed data clock synchronous processor field of invention The present invention relates to a digital data clock synchronous processor, and further relates to a digital data clock synchronous processor. For more information, see How to synchronize received serial data with a local crystal clock. In particular, the present invention relates to a digital processor that enables error-free reception.

Background of the invention At very high data transfer rates, especially when the speed is (when electronic operating speed limits are approached), error-free data in a single data path For data transmission to occur, the received data must be precisely synchronized with the receiver's local clock. We have to overcome the problem of letting people do it.

Previously, this problem was solved by using a timer with a higher frequency than the data transmission rate before data transmission. The signal was processed by encoding the data. In that case, a A receiver by analog means resolves the received signal into data and timing signals. I read it. The regenerated timing signal is used as a local clock for data reception. and when the receiver is part of a data bus system, the transmission medium used as a local tarokk for data retransmission to

These previous methods had two major drawbacks.

That is, l) The timing signal that encodes the data is of a higher frequency than the data transmission rate. It has to be something. Therefore, data transmission speed is faster than the bandwidth of the transmission medium. will also be considerably lower. Also, 2) Within one data bus system, the number of stations connected to the bus is limited. . The clock derived from the decrypted data is used to retransmit the data to the medium. I can stay. With this method, distortion is accumulated on both the data and the clock. . Each is used to generate the other in a closed loop. It is from.

Detailed description of the invention According to the invention, digital electronics can be used without the need for timing information exchange. non-return-to-zero (NRZ) between two or more devices at the maximum speed possible. Data can be exchanged. A receiving device using the present invention has its own crystal The optimal receive clock phase can be generated from the digital clock. The clock has a maximum size limit determined by the accuracy of the clock and the logic components used. Record the received data in a register without loss of information until the message is reached.

The two disadvantages mentioned above do not exist in this newly invented processor. Why and others, l) Uncoded data can be carried on the transmission medium. Therefore, de The data transmission speed can reach the bandwidth of the transmission medium.

2) To receive and retransmit data at the beginning of each received data block. , the receiver can choose the phase of its own crystal clock. chosen The phase of the received clock is used as the data clock, but the phase of the received/retransmitted clock is is constant. By using a fixed data clock, the received data If the data is retransmitted, the receiver puts a new signal on the medium. and the data Strain is removed. Once the composite signal distortion is removed, you can connect to the data bus There is no limit on the number of stations.

Brief description of the drawing Considering the above-mentioned purpose of the present invention, the merits of the present invention can be further understood by considering the attached drawings. be clearly understood.

FIG. 1 is a logic diagram of a first embodiment of the present invention. FIG. 2 also shows the second embodiment of the present invention. FIG. 2 is a logic diagram of an example.

Detailed description of the invention FIG. 1 shows the hardware of a high-speed data clock synchronous processor that is one embodiment of the present invention. FIG. 2 is a logic diagram corresponding to the hardware part. The purpose of this processor is to The objective is to generate a data clock without the drawbacks described in connection with the technology. Main departure The data clock generated by the Ming processor is a local crystal clock. A parallel output clock 10 is used, which outputs parallel output through a clock delay phase generator 16. subject to power delay. The parallel output signals 18 from generator 1B are sequentially and evenly delayed. . The purpose of the remaining hardware is to accurately synchronize all circuits given the data. of various delay outputs indicating the optimal clock phase to serve as the data clock The key is to choose a specific clock phase. Clock delay phase generator delay (element) The number may vary depending on the accuracy of the synchronization.

The selection of the optimal clock phase is performed by the clock delay phase snapshot processor 20. , which during a short time interval (window) 3B all delayed phase signals 18 Take a sample of the logical level of and the processor 24. The processor mainly uses certain clicks during windows. It consists of a series of gates that detect lock phase transitions or edges. Professional The parallel output from the processor 24 is input to the optimal clock phase setting processor 2B. , which of the locked phases this processor has checked the transition for a particular Special transitions (rising edges, or (falling edge). The final optimal clock phase selection is This is done in another level of logic circuitry, shown as lock phase selector 28. this The final selector 2B receives the parallel generation output of the processor 2B and the initial output from the generator 16. clock delay phase. Each game of the phase selector 28 The output from B is collected at gate 62 and the result is output at output B It becomes the optimal data clock on 4.

Data is input to processor 20 by input 12, particularly window generator 3B, which generates a window one hour for processor 20. It is the data message that governs the occurrence of the interval.

Considering the circuit in Figure ji1 in detail, the clock delay phase generator consists of multiple series connections. It can be seen that it includes a continuous digital delay (element) 30, with multiple parallel taps. It forms a digital delay line. The output tap of phase generator 1B has a C set. There is a sequentially delayed local crystal clock signal called clock, in the example C3- It is shown to contain C5. This set is C-(CC...,Ck) 0’ 1″ is defined as here co=local clock signal Ck: Most delayed clock signal The C set of clock signals corresponds to the terminals Do to D5 of the edge register 34. is input. The input to the edge register changes continuously, causing a clock transition. when the write enable pulse is applied to the register input terminal WE. Only the register works. If such a permission signal is given to the edge register 34, while register 34 records the corresponding digital level appearing at terminals Do-D5. A “snapshot window 〇 is created for a sufficient period of time to write.” . The means to generate such a time window is the snapshot window. This is achieved by a tone generator 36. The generator connects the first and second interconnection planes. Includes flip-flops 38 and 40. System reset pulse flips It appears on an input line 41 connected to the first input terminal of flop 38. to this terminal The input of resets the generator flip-flop to its initial state.

When a block of data appears on data input line 12, the second flip-flop 40 is set to generate one pulse along register input line 42. and this input line represents the window period that occurs during the first pulse of input data. In the meantime, writing of the C set from register 34 is enabled. Input line 12 The data is delayed through a serial delay 66 and the output of the last delay is The terminal CLK of the register 34 forms the clock input and the edge register outputs Q0 to Q5. clocks the output of the storage level written from.

From these outputs, the tJ2 set corresponding to the C set and denoted as 5o-S5 The level of (S set) is generally indicated by reference numeral 22. Proceed to this + The value set is 5-(SS......, 5k) 0' 1' defined by

Snapshot window generator 3B generates a signal for when the window is opened and clocked. When an edge appears, a snapshot image of the C set is stored in the edge register 34. issue. The number of continuous or discrete snapshots can be chosen by the generator. can. Only the first edge of the data block is used for the C set snapshit. A single, fixed delay phase is chosen for the entire data block when available. .

The next logic level is generally indicated by the reference digit 24 and is shown as a server. This device has an input of S set and two called E set. Generate a hex set to 4B. The E set can be used to compare a pair of adjacent values in the S set. and contains a binary value. E, -ko A value of 0 indicates a discontinuity in set S.

E-set is defined as follows.

E-(El, E2..., Ek) 'Here, j-1, 2,..., k .

As will be described later, the professional serpentine is equipped with a single gate level including the same gate 44. It contains the logic of For example, the output of a particular gate is At the same time, we generate a binary level 1, and the adjacent levels of S set are heterogeneous, and S set A binary 0 level is generated when a transition region or "edge" is indicated.

The next logic level is the optimum clock phase setting processor 2B, and the first human power is E. It is connected to the corresponding line of the set, and the second human power is connected to the corresponding line of the S set. It includes a large number of identical gates 48. For example, the top gate 48 has E There are l and sl. The output from gate 48 is referred to as P set (P1-P5) at 50. generates a binary set that is

This set is defined as follows.

P-(P P..., Pk, K11° 2゛ Here, each term in the set is defined by the binary value Pj-Ej+5j-1.

The terms p, -o are the thrusts from 0 to 1 in the S set at point j. Indicates the transition. Transition from 1 to 0 for the digital electronics family used When you need to select P, P, -E, +S are defined.

Cococo The output term in the P set is the inverse of all other terms (such as output 52) in the P set. is the binary sum at the adder 54. The final function to the optimal phase selection process is 5. A selector consisting of logic levels given by the same gates such as 6 and 58. This is done by the controller 28. Top gate 58 provides an output from adder 54 to and the second output represents the complement of the clock delay phase co. Each remaining gate is P Connected to the corresponding output of the set and the corresponding complement of the C set.

The inverted output from top gate 58 and remaining gate 56 is connected to gate 62 or It is collected in 0Rcd. In this way, selector 2B inputs the P set and from there , ideally used as a data clock for receiving or retransmitting received data. Select clock phase. The data clock is defined as follows.

Here, sum and product indicate binary operations. The output 14 of the summing gate 62 is a data clock. It carries the lock signal and output 64 carries the complement. Such a data clock output is Any suitable receiver or transmission circuit data clock that does not itself form part of the invention. can be connected to the network input section.

In the example shown in Figure 1, the output BO from the clock acting on the P4 set input and the delay clock The 04's complement from the lock signal is unique compared to the remaining gates of selector 28. provides clear output. Therefore, data clock outputs 14 and 64 are the optimal clock for C4. Corresponds to the lock phase and its complement. This is the data input along line 12 A delayed data clock that provides the first transition or edge in the chosen direction after the start of becomes. This optimal clock is used by all connected users for the entire data message. Attire! (not shown). new data message When a change occurs, the optimal clock selection is repeated.

Time in the clock and data path is critical to operation during this process. This is to maintain equality. To achieve this equalization, the data is sequentially delayed by passing the delay. The delay (element) is the delay (element) in the clock path. It is the same as the thing. The last gate 69 of equalizer 68 is initially shown on input line 12. Provides previously-used and inverted data, but is required to be synchronized to the clock. Delay equalization is performed.

An anti-lock safety control device 75 is provided as a safety mechanism. This control device The arrangement consists of two interconnected flip-flops 74 and 76, which As long as a valid data clock signal is present on reset line 78, the reset state is maintained. However, when the data clock is lost, the flip-flop The master reset terminal 80 of the edge register 34 and the snapshot window providing a set signal to the set terminal 82 of the mode generator flip-flop 38; .

In the second embodiment of FIG. 2, the processors 24, 26 and selector 28 of FIG. is replaced by the optimum clock phase selector 84, which allows the data clock to where sum and product are binary operations.

The selector 84 is used for normal and inverted outputs of the edge register 34a. for example, The top gate of selector 84 receives the complementary C set delay clock from phase generator 16. In addition to the complement of the C level from line 32 which provides It has a complement. Set the binary level to 0- indicated by the input and output of register 34a. Looking at the example used, the unique output is the third gate 86 with inverted 02 manual power. It can be seen that this occurs. This indicates the best selected clock phase and indicates the data clock phase. represents the signal appearing at output 14.

Processor 24.2B and phase selector 28 of the embodiment of FIG. Since it is compressed to 84 single logic levels, the delay equalization of the data is as shown in Figure 1. lower than that of the converter 68. Therefore, the data and clock path equalizer 68a , to provide equalized delayed data at output terminal 70 and inverted data at 72. connected in series with the data path.

As can be seen from the detailed description of the present invention, according to the present invention, the series delay local local crystal clock by choosing the optimal clock phase from the lock signal. A data clock can be generated from the clock. As a result, the processor Maximize bandwidth without the limitations of traditional technology coded clock processors can be done. Furthermore, for each received data block, a locally generated fixed data Data distortion is prevented because the data clock is available, which The number of stations that can be connected to the data bus increases.

The present invention is not limited to the detailed structure shown and described herein, but is It should be understood that obvious modifications are possible to those skilled in the art.

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Claims (1)

[Claims] 1. connected to the local clock to generate the delayed clock phase (18). Multi-tap delay line means (16) and sampled digital levels (22) at a preselected time after data reception. input to the delayed clock phase to sample the clock phase during the means (20) connected to the A system for selecting the optimal clock phase by detecting the occurrence of selected transitions. means (26, 28) (84) connected to the sampling means; A selection method for using the optimal clock phase as the data clock during data reception. terminal means (14) connected to the output of the stage; A synchronous circuit for generating a data clock from a local clock (10). 2. In order to equalize the circuit propagation time of the data clock and the data, Claim comprising means (68) (68a) for delaying said received data. Structure according to item 1. 3. The sampling means a register (34) (34a) with an input connected to each clock phase; Beauty Strobe the register ( 42) and also input data to produce the sampled clock phase. means (36) triggered by 2. The structure of claim 1, comprising: 4. In order to generate the delayed clock phase constituting the first signal set (18), multi-tap active delay line means (16) connected to the internal clock (10); , a) a register (34) having an input connected to each clock phase; b) Stroke the registers to enable the first set of writes from the registers. (42) and to produce the sampled clock phase. sampling means including means (36) triggered by input data; By means of a circuit for generating the second signal set (22), the A first cycle is performed to sample the clock phase during a selected timing period. means (20) having an input section connected to the cut; By detecting the occurrence of a preselected transition within the sample clock phase , means (84) for selecting an optimal clock phase; Contains multiple gates, each gate has a a) a first input connected to the corresponding delayed clock phase; and b) which delayed clock phase. Determine whether the phase has undergone the desired transition during the sampling period to indicate the optimal phase. For this purpose, there are second and third inputs connected sequentially to a second set of adjacent signals. during data reception, so that the optimal clock phase is available as the data clock. Terminal means (14) connected to the output section of the selection means, the synchronous circuit comprising: , the selection means further creates a delayed optimal clock phase as a data clock. In order to including a file addition means (88); Synchronous circuit for generating data clock from local clock. 5. In order to equalize the circuit propagation time of the data clock and the data, 5. A structure according to claim 4, including means (68a) for delaying the data. 6. In order to generate the delayed clock phase that constitutes the first signal set (18), multi-tap active delay line means (16) connected to the cal clock; a) a register (34) having an input connected to each clock phase; b) Strobe the registers to facilitate writing the first set from the registers. 42) and is also triggered by the input data to create the sample clock phase. sampling means comprising means (36) for sampling a second set of signals (2); 2) at a pre-selected timing after data reception by a circuit for producing In order to sample the clock phase during the period, the input section is connected to the first set. means (20), Detecting the occurrence of preselected transitions within the sampled clock phase. means (26, 28) for selecting an optimal clock phase by; Select to use the optimal clock phase as the data clock during data reception. Terminal means (14) connected to the output of the means, the synchronous circuit comprising: The selection means includes a plurality of gates, and the selection means includes: a) to generate a third set of signals (46) indicating which phase undergoes a transition; A plurality of first gates ( 44), and b) a second and third set of signals to form a fourth set of signals (50). a plurality of second gates (48 ), and c) determining which phases undergo the desired transition during the sampling period; From the third set and the delayed clock phase, the corresponding signal is a plurality of third gates (58) connected at each input; and d) an optimal clock position. To produce the phase as a data clock, from the third gate to all outputs, and a digital summing means (62) to which its input is connected. Synchronous circuit for generating data clock from clock. 7. In order to equalize the circuit propagation time of the data clock and the data, 7. The structure of claim 6, including means (68) for delaying the received data.