RU2030114C1 - Device for reception and transmission of asynchronous information - Google Patents

Abstract

FIELD: digital electric communication. SUBSTANCE: device includes storage 1, switch 2, D flip-flop 3, unit of correction of reading of addresses, former 5 of recording signal "by condition", counter 6 of recording addresses, counter 7 of reading addresses, wire 8 of recording addresses, wire 9 of higher position of recording addresses, wire 10 of reading addresses, wire 11 of higher position of reading addresses, common address wire 12. Device provides for capability of addressing storage under conditions of recording and reading for the course of one reading cycle and for use of cyclic correction of reading address with reference to recording address. EFFECT: simplified design, elimination of restrictions for duration of communication cession. 3 dwg

Description

 The invention relates to digital telecommunications and is intended to synchronize the received stream of information, clocked by the tracking frequency, with the frequency of the clock generator in the stream receiver.

 There are digital data transmission systems in which it is necessary to ensure the exchange of information, while the transmission is carried out in a sequential manner at a fixed transmitter frequency. When transmitting information on real physical lines, phase and temporal distortions of the clock frequency occur, as a result of which at the input of the receiver of this information the latter differs by an indefinite amount from the original. If the received information must be transmitted further as part of a group signal clocked by its own reference frequency, then due to the difference between the received and reference frequencies, distortions in the processing results inevitably occur, and the magnitude of these distortions is greater, the stronger the accompanying frequency differs from the reference frequency in phase and value .

 Known methods of combining these frequencies using an intermediate storage device (memory), the information in which is recorded at a speed determined by the tracking frequency of the received signal, and the reading of the recorded information is performed at a speed determined by the frequency of the reference generator of the receiver. It is fundamentally impossible to make the memory volume infinitely large, therefore, in real devices, a cyclic method of recording information is used, in which recording is performed in memory cells of the memory, starting with the youngest and ending with the oldest, after which the recording cycle is repeated. Thus, the information recorded in the first recording cycle is inevitably replaced by new information in the second cycle, in turn, the information of the second cycle is replaced by information of the third cycle, etc. so that each memory cell recorded in the first write cycle is read before the second write cycle. If the write and read frequencies are equal, then this requirement is satisfied automatically, that is, the processes of writing and reading are synchronous. In the case of different values of these frequencies, which occurs when the recording frequency arrives from the physical communication channel, there may be cases when the recording frequency is greater than, less than, or equal to the read frequency, and, in addition, may differ in state phase.

 The method using an intermediate memory as an asynchronous interface unit is used in PCM-120 equipment. Actually, the memory of this equipment is a set of triggers (memory cells), the recording and reading of which are carried out under the control of the signals generated by the write distributor and the read distributor, which change the trigger number with the arrival rates of the write and read frequencies, and the result of reading through the system of matching schemes combined through OR circuit, is fixed (gated) by a separate trigger, at the output of which a read pulse sequence is formed. The number of memory cells is chosen so that the moment of reading never coincides with the moment of recording. The minimum number of memory cells depends on the length of the transmit-receive cycle, which is determined by the transmission of special synchronizing symbols in the stream. A standard PCM channel cycle contains 256 clock cycles of the accompanying frequency, therefore, in the general case, the number of memory cells must be a multiple of this value. The use of triggers as memory cells in this case is disadvantageous due to the difficulties of the constructive, economic and energy orders.

 An asynchronous interface device is also known that works on the basis of the considered principle using an intermediate memory consisting of two memory blocks and an additional intermediate memory block, into which the code for comparing the write address counter and read address counter is pre-written, which ensures switching the memory blocks when the write addresses match and reading, thereby eliminating the simultaneous access to write and read to the same memory cell.

 The disadvantages of the known device are its complexity and limitation of the duration of the communication session.

 The purpose of the invention is to simplify the device and remove restrictions on the duration of the communication session.

 In FIG. 1 is a structural electrical diagram of a device for receiving and transmitting asynchronous information; in FIG. 2 and 3 are timing diagrams explaining its operation.

 The device for receiving and transmitting asynchronous information contains a memory unit 1, a switch 2, a D-trigger 3, a read address correction block 4, a conditional write signal shaper 5, a write address counter 6, a read address counter 7, a write address bus 8, a write bus 9 high-order bits of write addresses, a bus 10 of read addresses, a bus 11 high-order bits of read addresses, a common address bus 12.

 A device for receiving and transmitting asynchronous information operates as follows.

It provides a pair of two asynchronous frequencies, one of which, the recording frequency (F ₃ ), can change the magnitude and phase, and the other, the reading frequency (F _Th ), is a fixed stable frequency of the reference generator. The information flow entering the input of the device is clocked by the recording frequency and under the control of this frequency is recorded in the D-trigger 3, where it is stored for one clock cycle of the recording frequency. The recording frequency controls the operation of the counter 6 recording addresses, providing bus 8 cyclic change of address with a period of change of one clock cycle recording. The older part of the address space is entered into the read address correction block 4, which corrects the state of the read address under the control of the derived signal of the read frequency when the counter 6 reaches the write address of the value that matches the current value of the counter 7 of the read addresses.

 To exclude the possibility of the simultaneous occurrence of read and write enable signals on the memory unit 1 and the switch 2, a shaper of write signals 5 is introduced “by condition”, to the inputs of which the read write frequency signals are received. It provides control of the phase of the recording frequency, comparing it with the phase of the read frequency so that at the time the read signal is generated, the write signal does not appear.

The read frequency (F _Th ) is supplied to the counter 7 read addresses and provides a cyclic change in the state of the bus 10 read addresses. The switch 2, in accordance with the addresses of the write or read, arriving at its inputs, controls via the general address bus 12 the selection of the memory cell of the memory unit 1. On the common address bus 12, the read and write address appears alternately depending on the receipt of read and write signals at the control inputs of the switch 2. The memory block 1 is also controlled by these signals, as a result of which, when the read signal is in effect, the memory cell specified by the read address is read and the data bit from this cell appears at the output of the memory block 1, and when the write signal is in effect, the data bit is recorded from the D-trigger 3 in the memory location of the memory unit 1 specified by the recording address through its information input.

 Block 4 correction of read addresses works as follows.

Changing the current read address within the specified number is performed by block 4 when the counter 6 reaches the read address value equal to the value of the counter 7 read addresses. Correction of the read address occurs under the influence of the correction signal (F _Th / n) by changing the upper bits of the read address once per cycle, provided that the current value of these bits coincides with the current value of similar bits of the counter 6 write addresses, i.e. block 4 changes the state of the bus 10 read addresses in such a way that the correction is always performed on a strictly fixed value determined by the number of ticks (n) in the cycle.

Consider a signal diagram explaining the principle of operation of the reading address correction block 4 (Fig. 2). In FIG. 2b is a signal diagram of the bits 2 ^t and 2 ^{t + 1 of the} counter 6 of the write addresses, in FIG. 2a and 2c are signal diagrams of bits 2 ⁿ and 2 ^{n + 1 of the} bus 10 of read addresses for cases when the read frequency is lower and higher than the write frequency. The diagrams show that the change in the state of bits 2 ⁿ and 2 ^{n + 1 is} carried out synchronously with the arrival of the comparison frequency (F _cf = F _Th / n) of the correction signal once per cycle, and this change occurs according to the law of division into two and only in the indicated on the diagrams, time instants I, i.e., at the moments of bitwise coincidence of signals 2 ⁿ and 2 ^t , 2 ^{n + 1} and 2t + 1, the next read address changes, which ensures the mismatch of the cells of memory unit 1 during recording and reading.

 Shaper 5 recording signals "conditionally" works as follows.

 As already indicated, it generates read and write signals that are control signals for the memory unit 1 and switch 2, eliminating the possibility of their simultaneous appearance. The possibility of the simultaneous appearance of read and write signals arises due to the fact that the phases of the write and read frequencies in the general case differ from each other and the duration of the periods of the indicated frequencies is different, and this can lead to a state where the timing of the transmission of read and write signals is possible . The algorithm of the shaper 5 is that in such a situation, only the read signal appears at the corresponding output when the write signal is delayed until the read signal ends. If within one read-write cycle the write signal in terms of duration has time to form before the start of the read signal, then the driver 5 generates a write signal that appears on the corresponding output, otherwise the output of the write signal is delayed, as noted above. Thus, the possibility of the simultaneous appearance of read and write signals at the outputs of the shaper 5 is excluded.

Consider a signal diagram explaining the principle of operation of the shaper 5 of the recording signals "conditionally" (Fig. 3). In FIG. 3a shows a sequence of read addresses (A _Th ), FIG. 3b - read frequency signals (F _Th ), and in FIG. 3c is a sequence of read signals at the output of the driver 5.

As can be seen from the above diagrams, the read signal is synchronized with the read frequency signal F _Th and, accordingly, with the read address signal A _Th , i.e. in one reading cycle (one period of reading frequency T _Th ), one reading signal is generated.

In FIG. 3d shows a sequence of signals with a recording frequency F ₃ , which in the general case is asynchronous with respect to the frequency F _Th and differs from it by the duration of the period (T _Th ≠ T _sn ). In FIG. 3g shows the sequence of write addresses A ₃ , and in FIG. 3e - a sequence of recording signals at the output of the driver 5.

From the operation algorithm of the former 5 and the diagrams shown in FIG. 3, it can be seen that a change in the write address synchronous with the write frequency F ₃ causes the write signal to appear only if at that moment a read signal is not generated. In addition, the diagrams show that the recording signal can take place within the recording period both before the formation of the read signal and after (positions I and III, respectively).

Claims (1)

 A RECEIVING AND TRANSMISSION DEVICE FOR ASYNCHRONOUS INFORMATION, which contains a memory block, a switch, a read address counter and a write address counter, the outputs of which are connected through the write address bus to the write address inputs of the switch, the read address counter outputs are connected to the read address inputs through the read address bus, and the outputs of the switch through a common address bus are connected to the address inputs of the memory block, while the inputs of the counters of the write addresses and read addresses are respectively the inputs of the write clock frequency and so on a new read frequency of the device, characterized in that a read address correction block, a conditioner of the write signals are inserted into it, and a D-trigger, the output of which is connected to the information input of the memory block, the read signal output is connected to the read permission input and the first control input of the switch a recording signal shaper according to a condition, the output of a recording signal of which is connected to a recording permission input of a memory block and a second control input of the switch, the first output of a recording signal shaper The condition is the input clock frequency of the device, the input clock frequency of the recording of which is the second input of the shaper of the recording signals by condition, connected to the control input of the D-trigger, and the outputs of the upper bits of the counter of the write addresses via the bus of the upper bits of the write addresses are connected to the inputs of the read address correction block the outputs of which are connected through the bus of the upper bits of the read addresses to the inputs of the high bits of the read addresses of the switch, and the output of the correction signal of the counter of the read addresses is connected the control input of read address correction unit, and the data input D-flip-flop is a data input device, the output of which is the output of the storage unit.

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