SU1193836A1 - Device for transmission of digital information - Google Patents

Description

The invention relates to telecommunications and can be used to transmit discrete information.

The purpose of the invention is to increase the amount of information transmitted.

FIG. I shows a block diagram of the proposed device; FIG. figure 2 - the same, the time switching unit, the control unit and the multi-generator; fig.Z - the same unit of a single switching; figure 4 - the same, the spatial switching unit.

2

A device for transmitting discrete information contains a unit 1 time switching, unit 2 control, multi-cycle generator 3, unit

5 4 adaptive switching, unit 5 spatial switching.

The time switching unit consists of receivers 6, a two-stage U multiplexer 7, a decoder 8 commands and an operational storage node (RAM) 9 of the channel state.

3

Π 93836

The control unit consists of a block of 10 registers, driver 1! commands, semi-permanent storage unit (PROM) 12, permanent storage unit (ROM) 13 and random access memory unit (RAM) 14.

The multi-cycle generator consists of a generator of 15 rectangular pulses, a distributor of 16 clock pulses, a counter of 17 addresses and a driver of 18 time stamps.

The adaptive switching unit consists of a discriminator 19. input marker, comparator 20 input packets, first, second, third, fourth, fifth, sixth and seventh elements And 21-27, accumulator 28 packets, valve 29, first delay line 30, trigger 31, pulse shaper 32, first 33 and second 34 inverters, outgoing packet comparator 35, address comparison node 36, packet transmitter 37, OR 38 element, marker shaper 39, second 40 and third 41 delay lines.

The spatial switching unit consists of a two-stage demultiplexer 42 and transmitters 43.

The device works as follows.

The device can operate in one of three modes: receipt of information in the mode of switching channels with empty pauses between individual messages; the arrival of information in the channel switching mode — with packets filled with pauses; channel information is not received.

Starting the device in all three modes is similar, it differs only in the operation of the adaptive switching unit 4.

The entire service cycle of one channel consists of four cycles. The decoder 8 commands provides synchronous cyclic scanning of channels and RAM 9 channel status, in which one bit is allocated for each channel, indicating the channel status at the previous time: "1" - the channel is busy;

"0" - <channel is free.

Upon detection of a channel status mismatch with the state of the corresponding bit of the RAM 9 of the channel status, the second cycle occurs

Organizing the next command to the driver 11 commands (the first command is the initial state of the program part of the RAM 9 of the channel status and is encoded as eight "0") · The decoder of 8 commands in this mode works out the entire algorithm for servicing this channel. The address of the next command is contained in the previous one. This algorithm is terminated by space-time switching, when the decoder of 8 commands at the appropriate time sprinkles into the spatial switching unit 5 the address of the channel that needs to be connected to the channel that is in this temporal position for service. / Address of the desired subscriber is stored in the cell RAM 9 channel status, the number of which corresponds to the channel number, etc. which received the request for transmission.

The shaper I1 of commands performs centralized control of the entire switching process, operates in: interrupt mode from block 1 of temporary switching. Depending on the address of the served subscriber, the driver of the 11 commands reads from the ROM 13 an algorithm of its service in the form of commands for the decoder of 8 commands.

In the cycles of treatment unit 1 time switching to the driver 1 1 co-mand last command it. broadcasts. ROM 13 is a memory ’in which the subscriber service program is stored; the read command is controlled by the driver of 11 commands. EPROM 12 — memory in which data is stored for each channel — priority, category, rating zone, etc. Depending on this data, the service is carried out according to the appropriate algorithm. .

RAM 14 is a memory in which information for operational purposes is transferred from the PROM 12 and ROM 13.

Block 10 registers stores the address

Last team worked on each channel. In this area, the counter 17 addresses is entered information from the driver 11 commands 5 for the temporary switching unit.

! Block 10 registers is designed to

"Unloading ¹ 'control block 2. Shaper 11 commands reads from

RAM 14 and writes to block 10 re5 I

Gistrov is the next team for servicing the channel of this address, while the address of the previous command from block 10 of registers is taken as the "starting point". The developed command is stored to the current until it is read by the decoder of 8 commands. In addition, each command contains the address of the next. The shaper 11 commands controls the process of reading information from the EPROM I2. Reprogramming of the EPROM 12 may be carried out electrically or by ultraviolet light. Memory capacity is determined by the capacity of the device by the number of channels served. The key to accessing the required information stored in the EPROM 12 is the address of the channel being served.

The ROM 13 stores the service program for subscribers of various cateronies. The capacity of this memory depends on the number of subscriber types serviced by the device. The ROM 13 refers shaper 1I commands to read, depending on the channel address of a certain fragment of the service program in the form of commands for block 1 time switching. This information is rewritten in RAM 14 for further operation with it.

The address of a command selected from RAM 14 is determined by the address from the previous command stored in block 10 of registers. The generator 15 rectangular pulses generates rectangular pulses that arrive at the distributor 16 clock pulses, built on the basis of a four-stroke ring shift register with four outputs, on which "1" alternately appears, position number "1" corresponds to the tact number. The counter 17 of the address cyclically recalculates the clock pulses in the address of the served channel, which enters the block 1 temporary switching and block 2 control. The address changes after four cycles. The time stamper 18 generates time-based timestamps for time interval samples in time switching unit 1. The parameters of these labels are selected on the basis of the specific conditions of the functions of 193836 6

device - from the type of signals

transmitted through the channels.

Starting the device as described above. Further, when and the signals arrive at the adaptive switching unit 4, the device operates as follows.

In the first mode of switching channels with empty pauses between

¹⁰ separate messages ^ - the beginning of work as described above.

Then from the decoder 8 commands block 1 time switching in the comparator 35 outgoing packets and block 5

15 spatial switching transmits the address of the desired subscriber in the form of the number of the desired transmitter.

43. From the information output of the unit 1 time switching is fed subsequently

20 is an information pulse that enters the discriminator 19 of the input marker. In the case of receipt of the input marker,

- which is different amplitude (not

²⁵ less than 2 MB), on the second control output of the discriminator 19 of the input marker appears "1" (in the normal state - "0" and then the chain of service packages, starting

30 comparator 20 input packets, disabled). Through the discriminator 19 of the input marker and the element And 23 information pulses arrive at the delay line 30. In this moment

35, the trigger 31 generates a trigger pulse for the (single) pulse shaper 32. Delay line 30 delays information pulses by 10–50 µs with the aim of

40 ensure the response time of the shaper 39 marker and the generation of pulses inhibit the read from the drive 28 packages. The exact value of the delay time can be determined by binding to specific equipment. At the time of the disappearance of information pulses, the impulse to prohibit reading of packets from the accumulator 28

50 address from the comparator 35 outgoing packets through the valve 29 read packets from the drive 28 packages.

Further packages through the element And 27

55 enters the transmitter 37 packets,

which produces momentum for

forming a marker that through

the element OR 38 enters on (one

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multiple) marker shaper 39, where the marker is produced, in this case it is incoming. From the information output of the transmitter 37 packets through the delay line 41, which delays the packets for the response time of the marker shaper 39, the AND 24 element enters the synchronous digital group path and then into the spatial switching unit 5. The pause ends with the appearance of a sequence of information pulses transmitted in the mode of switching channels. The first pulse through the element 23 arrives at the delay line 30, the trigger 31 and the single pulse shaper 32, where a read inhibit pulse is generated. This pulse arrives in parallel at the first input (prohibition) of reading packets from packet accumulator 28 and onto element OR 38. Through element OR 38, this pulse arrives at (one-time) marker maker 39, after which the marker (which in this case is closing) through element And 24 enters the synchronous digital group path and then in block 5 spatial switching, closing the sequence of packets.

In accordance with the address transmitted from the decoder 8 commands of the time switching unit 1 to the demultiplexer 42, a synchronous digital group path will be connected to the required transmitter 43, In this case, one of 128 transmitters 43 is connected in accordance with the address of the called subscriber.

The operation of the block 4 adaptive switching in the second mode.

In the initial state on the second control output of the discriminator 19 of the input marker appears "0".

Upon the arrival of the incoming marker on the control second output of the discriminator 19 of the input marker, an "I" appears, which is a signal for connecting the comparator 20 of the input packets 20 to the channel, after which the system of suppressing the marker of the discriminator 19 of the input marker suppresses the input marker. The comparator 20 of the input packets reads the packets from the "pause", after which the discriminator 19 of the input marker produces their deletion. After the input packet comparator 20 determines the desired direction of transmission by the packet header, a write enable pulse appears at the first output of the input packet comparator 20, and the second output shows the address of the required channel for transmission to the address comparison node 36, where it compares with the address received from the decoder 8 commands. In case of coincidence of addresses, the packet immediately, bypassing writing to the accumulator 28 packets, through the element And 26 is fed to the input of the transmitter 37 packets (at the output of the address comparison node 36 in this case "0").

If the address mismatch, the packet through the AND 25 element is recorded in a specific sector of the accumulator of 28 packets. The sector number of the accumulator 28 packets corresponds to the desired direction of transmission of the packet.

The transmitter of the 37 packets enters the contents of that sector, whose address is in the comparator 35 of the outgoing packets, this is done by valve 29.

Next, read packets from the accumulator 28 packets arrive at the transmitter 37 packages, which produces a pulse for (single) shaper 39 marker. Through line 40 of the delay and the element And 21 after the incoming marker packets arrive in the synchronous digital group path and then in block 5 spatial switching. The end of the pause is preceded by the appearance of the closing marker, which is perceived by the discriminator 19 of the input marker and translates the state of its controlling second output to "0", which disables the comparator 20 input packets and the entire packet service chain. This marker is also suppressed by the marker suppression system of the discriminator 19 of the input marker. After the arrival of the first pulse of information transmitted in the switching mode of the channels (it is transmitted through the discriminator 19 of the input marker, the element 23 and the delay line 30), the trigger 31 is triggered and outputs a starting pulse to (once) the pulse shaper 32, which generates a pulse to prohibit packet readout and on closure generation9

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marker. After a delay, information is passed to spatial switching unit 5.

In accordance with the address transmitted from the decoder 8 commands of the block I time switching to the demultiplexer 42, the synchronous digital group path will be connected to the required transmitter 43.

In this case, in accordance with the address of the called subscriber, one of the 128 transmitters 43 is connected.

The operation of the proposed device in the third mode is as follows.

In this case, at this time position, in the spatial switching unit 5, packets are transmitted from the accumulator 28 packets to the previous address, which remained in the outgoing packet comparator 35, being entered there by the decoder 8 commands at a previous time point. The generation of incoming and closing tokens, packet transmission occurs as in the first mode.

Yu In accordance with the address transmitted from the decoder 8 commands of the block 1 time switching to the demultiplexer 42, the synchronous group path will be connected.

15 with the required transmitter 43. In this case, one of 128 transmitters 43 is connected in accordance with the address of the called subscriber.

Fig 2

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Claims (2)

1.DESIGNER FOR TRANSFER OF DISCRETE INFORMATION, containing-control unit, multi-clock generator, clock, address and control outputs of which are connected respectively to the clock, address and control inputs of the temporary switching unit, the address output of which is connected to the address input spatial switching unit, characterized in that, with the goal of increasing the volume of transmitted information, an adaptive switching unit is entered into it, the output of which is connected to the information input of the spatial switching unit, whose address input is connected to the address input of the adaptive switching unit, whose information input is connected to the information output of the temporary switching unit, the control output of which is. go connected to the control input _p the control unit, the clock input of which is connected to the clock output I * of the multi-clock oscillator, whose output ρι is connected to the address input of the control unit, the control output of which is connected to the control input of the time switching unit. FIG. one Ζ0 eo SaE her > 1193836 2. The device according to claim 1, which is based on the fact that the adaptive switching unit contains seven AND elements, two inverters, an OR element, three delay lines, an input packet comparator, a packet accumulator, an address comparison node, an outgoing packet comparator, a valve , packet transmitter, marker shaper, trigger, pulse shaper, pulse and discriminator of the input marker, the first output of which is connected to the first input of the input packet comparator, the second input of which is connected to the input of the first inverter, to the first inputs of the first and second {element in And to the second discriminator input marker, the third output of which is connected to the first input of the third element And to the second input of the second element And, the output of which is connected to the output of the first delay line, to the output of the fourth element And, and to the output of the first element And, the second the input of which is connected to the output of the second delay line, the input of which is connected to the input of the third delay line and to the first output of the packet transmitter, the second output of which is connected to the first input of the OR element, the output of which is connected to the input form a marker whose output is connected to the output of the third delay line and to the first input of the fourth element I, the second input of which is connected to the output of the first inverter and to the second input of the third element And, the output of which is connected to the input of the first delay line nd with the input of the trigger, the output of which is connected to the input of the pulse former ". The output of which is connected to the second input of the OR element and to the first input of the packet accumulator, the second input of which is connected to the first output of the input packets comparator The second output of which is connected to the first input of the address comparison unit, the second input of which is connected to the output of the comparator of the outgoing packets and to the first inputs of the valve, the second inputs of which are connected to the output of the packet accumulator, the third the stroke of which is connected to the output of the fifth element And, the first input of which is connected to the third output of the comparator of input packets and to the first input of the sixth element And, the second input of which is connected to the output of the second inverter, whose input is connected to the second input of the fifth element And, with the output of the comparison node addresses and the first input of the seventh element And, the output of which is connected to the output of the sixth element And and to the input of the transmitter packages, the valve outputs are connected to the second input of the seventh element And, while the comparator input of the outgoing packet a data input is adaptive switching unit, the address input of which is input an input token discriminator output adaptive switching unit is output first delay line. one