SU1446621A1 - Simulator for testing the components of single-channel local computing network - Google Patents

Abstract

The invention relates to the field of computer technology and can be used to test test components of a mono-channel local computer network (subscriber systems, transport stations and channel stations, controllers of the mono channel, blocks of access to the physical data transmission medium). The purpose of the invention is to expand the functionality by introducing additional simulation modes. The goal is achieved by the fact that the addressing unit and the counting unit are entered into the simulator containing the memory and control blocks, the driver of the frame control sequence, the pulse generator, the data output unit. frame length, error block, data multiplexer, data multiplexer counter, and delay block. The simulator makes it possible to form various test frames for C4et changes within wide limits of the frame length, introducing an error dir combination into the control field, adjusting the interframe interval that. ultimately, it allows to increase the reliability (completeness and accuracy) of diagnosing network components. 8 np. WITH

Description

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The invention relates to computing and can be used to test the components of a mono-channel local area network, in particular for testing testing subscriber systems, transport and channel stations, mono-channel controllers and blocks of access to the physical data transmission medium.

The aim of the invention is to expand the functionality by introducing additional simulation modes.

FIG. 1 shows a block diagram of the simulator of FIGS. 2-8 — examples of the implementation of functional blocks of a memory unit, a control unit, an addressing unit, a frame length counting unit, an error fixing unit, a delay unit, and a data output unit.

The simulator (Fig. 1) contains a memory block 1, a control block 2, a data output block 3, a data multiplexer 4, a data multiplexer counter 5, an addressing block 6, a frame length count unit 7, a control frame sequencer 8 (PDA), an error fixing unit 9, a delay unit 10, and an 11 pulse generator.

Memory block 1 contains (Fig. 2) switch 12 addresses, the first 13, 14 and the second 15, 16 groups of storage nodes (RAM) and v multiplex cop 17. Memory block 1 uses groups of memory 2 x (8 x 2048) bits, filled on a 16-bit data bus by sequentially addressing memory cells. When writing, a message is formed that is a multiple of 16 and contains up to 4096 octets. The division of the memory into two groups is designed to record the current and subsequent frames.

The control unit 2 contains (FIG. 3 the elements OR 18-20 and the distributor 21 pulses.

Unit 6 addressing contains (4) the decoder 22, the switch 23 counting pulses and address counters 24 and 2

The frame length counting unit 7 contains (FIG. 3) address counters multiplexer 26, a comparison circuit 27 and a frame length register 28.

Block 9 fixing errors contains (6) counter 29 SOZH, register 30 errors and the adder 31 modulo 2.

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The delay unit 10 comprises (FIG. 7) serially connected delay element 32 and programmable delay element 33.

The data output unit 3 comprises (FIG. 8) an OR element 34, a counting trigger 35, an output multiplexer 36, an encoder 37, a data transmission unit 38, a tunable frequency divider 39, and a control signaling transmission unit 40.

The drawings also show links 41-61 between simulator blocks.

Shaper 8 implements a standard algorithm for constructing a control sequence using a shift register to divide by the 32th degree polynomial by analogy with dividing by the 16th degree polynomial in the X.25 standard.

During the operation of the device, test frames are generated representing the simulation of network data. The simulator is connected with its outputs either to the access unit from the subscriber system or to the subscriber system from the access unit. In the first case, the operation of the subscriber system is simulated, in the second - mono-channel data. Network data is simulated on a standard access unit interface with a subscriber station. The output interface of the simulator conforming to the ISO 8802/3 standard is supported by node 38 and node 40 of block 3. Manchester coding is used to transmit data on the output of the Simulator data: on the Control output, 5 or 10 MHz rectangular pulses are transmitted. The moments of the output voltage drops are set by the generator 11. On the Data output, either the information supplied to block 3 is transmitted, or the signal is set to no signal, which is determined by the corresponding signals from the outputs of blocks 2 and 9. The output state is Control (presence of signal as rectangular pulses of different frequency or lack of signal) is set externally by the input Control.

The device works as follows.

Prior to the formation of test frames by an input signal, the Installation is performed by the initial installation of simulator blocks. When this signal arrives at the input of block 1, (input Setting the address switch 12, Fig. 2), the input bus of the Address is connected to the first group of memory 13 and 14, and the output of block 6 of addressing is connected to the second group of memory 15 and 16. At the same time, block 1 of memory These are transferred to the state that provides data sampling from the outputs of the second group of memory 15 and 16 by acting on the input to the installation on multiplexer 17 (Fig. 2). When a signal arrives. Installation at the input of the unit 2 by signals from the outputs of the distributor 21 blocks the transmission of pulses from the generator 11 to the inputs of the counter 5, the error fixing unit 9 and the former 8. At the same time, the same signal from the output of the element OR 18 makes the initial installation of the counter 5, unit 6 (reset address counters 24 and 25 and blocking of switch 23, figure 4), driver 8 and block 9 (reset of counter 29, figure 6). When a signal is received Setting the input of unit 3 activates its input with the connected multiplexer 4 (affected by a. Setting the input of the counting trigger 35 resets it and the output multiplexer 36 connects the output of multiplexer 4 to the input of the encoder 37, Fig. 8), the output Data is blocked (set to no signal) the function is passed to the encoder 37 Manchester coding).

After the simulator is set to the initial state by a signal at the input Record, the data received on the input bus is written. Data is in memory block 1 (memory 13 and 14, figure 2), block 7 (frame length register 28, figure 5) and block 9 (error register 30, FIG. 6). In this case, during the recording of data in block 1, the following actions are performed:

on the input Address on the address bus sets the address of the memory cells, which through the switch 12 is transmitted to the address inputs of the memory 13 and 14 (FIG. 2),

on input The data on the input bus is set to the data that you want to hang at the selected address,

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by the input signal Record, data is recorded in the memory cells 13 and 14 (Fig. 2).

Writing data to block 7 of the frame length and block 9 fixing errors is performed without addressing. In this case, the number of bits of information recorded in memory 13 and 14 is entered into the length register 28 of the frame length. The register 30 of the PDA error is entered into the register 30 as units of those bits in which it is supposed to simulate errors.

After recording all the data signals by input Switching from the output of the element OR 19, the input bus is switched to the Address and output of block 6 to the memory groups of memory 1. This signal is fed to the inputs of the switch 12 and the multiplexer 17; input bus The address is connected to the address inputs of the charger 15 and 16, the output of block 6 is connected to the inputs of the charger 13 and 14.

The input signal Start via the element OR 20 and the distributor 21 (Fig. 3) reads the frame data recorded in memory block 1 (in the memory 13 and 14): the generator 11 is transmitted from the outputs of the distributor 21 to the inputs of the counter 5 and shaper 8. In addition, the same signal from the sixth output of control unit 2 (from the output of element OR 20) allows output of information from the output of data multiplexer 4 to the output of Data from output data unit 3 (via output multiplexer 36 and node 38 after the Manchester-enabled transform 37 m (Figure 8).

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The data from memory block 1 is sampled using counter 5 and addressing block 6.

The Start signal in the multiplexer counter 5 starts the pulse counting of the generator 11 modulo 16: the count is 0-15. The output signals of counter 5 affect multiplexer 4 in such a way that, during the counting process, the input of multiplexer 4 is connected in series to each of the 16 outputs of block 1. In fact, multiplexer 4 performs a transfer function when sampling data from the first group of memories 13 and 14 of memory block 1 ti, since the input of the multiplexer 4 (Fig. 1 and 2) is connected to the memory device 13 and 14 through the multiplexer 17.

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The addresses of selectable data from the indicated group of the memory of block 1 are set by block 6 using address counters 24 and 25 (FIG. 4), the outputs of which are connected via the switch 12 of the address of memory block 1 to the address inputs of the corresponding memory 13 and 14 (FIG. 2). Address counters 24 and 25 are switched and, therefore, addressing of memory 13 and 14 is changed through switch 23 by signals in the form of output 1 pulses by decoder 22 with corresponding counts 12 and 14 of counter 5, and the first switch of address counter 24, since switch 23 triggered by a pulse emitted at the output of the decoder 22: when the counting is eight, the counter 5 (the lock on the switch 1 of the switch 23 is released, made to the signal Set). In addition to the pulsed pulses 22, the pulse At is also extracted as an output signal. the account O of the counter 5, which, together with the pulse of the account 8, goes to the multiplexer 26 (FIG. 5).

Thus, the sampling of data from memory block 1 is cyclical. The cycle consists of 16 clock cycles eight clock cycles (counting 0–7) for sampling eight bits of memory unit 13 and eight clock cycles (counting 8–13) for sampling eight bits of memory unit 14. Changing the address of cells in memory unit 13 is performed while reading data from memory unit 14 and vice versa.

The bit stream formed at the output of data multiplexer 4 is fed to the input of the imaging unit 8 and the data output unit 3. Unit 3 (Fig.8) provides information transfer through the output multiplexer 36, the encoder 37 and the node 38 to the output of the Simulator data. Encoder 37 implements the Manchester coding of the binary sequence from the output multiplexer 36J and the moments of possible differences in the signal values in the Manchester code are given by an 11-pulse generator. In addition to the encoder 37, the oscillator 11 pulses with a frequency of 20 MHz are also fed to a tunable frequency divider 39, which, depending on the signals on the input. The control issues rectangular pulses with a frequency of 10, 5 or O. MHz. The node 38 and the node 40 carry out level conversion and galvanic isolation of the corresponding signals.

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according to standard 150 on the interface with the access unit with the subscriber system.

5 The shaper 8 is transferred by the bit sequence from the output of multiplexer 4 to the state corresponding to the calculated value calculated by the algorithm for determining the frame's control sequence in ISO 8802/3. The PDA is calculated according to the well-known cyclic coding scheme by dividing by a 32-degree polynomial

15 The division function of the input nominal (binary sequence at the output of multiplexer 4) is provided by clock pulses and leads to the formation of a control code, 20 times 32 bits, the remainder of the produced polynomial division. The code generated in this way is preserved until the signal from the output of block 7 arrives.

25 The bitstream at the output of multiplexer 4 is interrupted by the signal of block 7. In the Simulator, the frame length is proposed to be limited to just above 4096 bytes. The absence of 30 restrictions makes it possible to vary the frame length from test to test over a wide range. Information on the number of bits to be transmitted is recorded in block 7 during data recording and in

35, this number is compared with another number corresponding to the current value of the number of transmitted bits. The number of bits transmitted is determined in block 7

40 depending on the value of the signals from the outputs of counter 5 and block 6. Information about the number of bits to be transmitted is written to register 28, younger than the current bit.

The 45 numbers of transmitted bits are specified by counter 5, the bit output signals of which are fed to the comparison circuit 27, and the upper bits of the number of transmit bits are set by multiplexer 26.

50 When allocating the account O of the counter 5 with the descriptor 22 (fg 4), in accordance with the said 16-clock cycle, the address counter 24 is connected to the comparison circuit 27 (FIG. 4), and when the score 8 is split, the multiplexer 26 switches to forwarding the data of the address counter 25. Thus, the low part of the chip shows the current number of data bits modulo 16;

the twelve most significant bits define the number of 16 clock cycles. In sum, the length of the transmitted frame is formed.

In case of equality of the current and specified values of the frame from the output of the comparison circuit 27 (figure 5), a signal is received at the inputs of block 2, block 3 and shaper 8. At the same time, shaper 8 stops the computational functions, by definition, PDA, the transition from the state of computation to The state of the control code output in block 3 of the data output stops receiving data from the output of multiplexer 4 and connects the output of the adder 31 (Fig. 6) of block 9. In block 2, when a signal from the output of block 7 arrives at the input of the distributor 21 (Fig.З) pulse generator 11 on with a clock 5, as a result of which the data sampling from memory block 1 is stopped (from memory device 13 and 14, Fig. 2); The output of generator 11 (via distributor 21) is switched to the input of block 9, in which the test control sequence (total signal of control values and errors) and its length are determined. The pulses on line 52 are fed to the inputs of counter 29 and register 30. The contents of error register 30, specified during data recording, are shifted and fed in series to the adder 31. The control sequence from the output of the former 8 enters the other input of the adder 31 after it terminates calculating the PDA from the signal from the output of block 7. The control code is output from the imaging unit 8 in a sequential form under the influence of the same pulses coming from the output of block 2, which were previously intended for calculating QOL. The total signal of the control values and errors from the output of the adder 31 through line 46 is fed to the input of the block 3 data output and then to its output data. At the same time, counter 29 calculates the length of the test sequence. After the arrival of 32 bits, i.e. 32g-x pulses from the output of the distributor 21, the output of the counter 29 generates a signal of the end of the check-sequence, which is fed to the inputs of block 2, block 3 data output and block 10. At the same time, in block 2

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The PDA end signal blocks the generation of generator pulses 11 (at the outputs of the pulse distributor 21, FIG. 3) in Data output block 3, the Data output is blocked (line 47, the PDA end signal enters the input of encoder 37, which terminates the Manchester coding function).

In delay block 10 (Fig. 7), the delay value of the element 32 is selected taking into account the minimum interframe interval, the delay value of the element 33 is changed. The delayed: element 32 volume of the PDA end signal (on line 48) enters the input of data output block 3 and re-activates its input connected to the output of multiplexer 4 (through the OR 34 element this signal switches counting trigger 35, the signal from which output acts on output multiplexer 36). In block 2 (FIG. 3), the signal delayed by element 32 is used to translate

25 of the simulator in the initial state of readiness for transmission of the following frame, coming from the output of the element OR 18 to the inputs of the counter 5, block 6, block 9 and the formation 8 of the PDA, delayed

30 signal of the end of the PDA resets the counter 5 of the data multiplexer, resets the address counters 24 and 25 and locks the switch 23 of the addressing unit 6 (Fig. 4), resets the counter 29

-jg of block 9 (Fig. 6), and also sets the initial state of the driver 8. The same signal from the output of the OR 18 element blocks the outputs of the distributor 2.1 by a pulse (g).

40 In addition, the signal delayed by element 32 (Fig. 7) through the element OR 19 (Fig. 3) is fed to the input of the mode of memory block 1 (Fig. 2) and affects the switch 12 and multiplexer 17, preparing a sample of data from the memory 13 and 16 at the addresses determined by block 6. The moment of the beginning of the transfer of the next frame is determined by the delay of the signal of the end of the PDA by the programmable delay element 33, from the output of which it enters the input of the OR element 20 (FIG. 3). The effect of this delayed signal is similar to the initial launch of the simulator with a signal at the Start input.

Thus, the simulator is prepared for transmitting a new test frame containing in memory 15 and 16 of block 1- (figure 2). Record this data frame.

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as well as the data on the number of bits in block 7 (in register 28, fig. 5) and data on PDA errors entered in block 9 (register 30, fig.6), is recorded during the count of the first frame up to the signal at the output of the element 32 delay (Fig. 7). Conversely, during the acquisition of the next frame contained in memory 15 and 16, the data of the next frame are recorded in memory 13 and 14 (FIG. 2), as well as the data associated with this frame.

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A simulator for testing components of a mono-channel local computer network containing a memory block, the first address input, the information input and the recording strobe input of which are the Address, Data, and Simulator Records inputs, and the mode input is connected to the first output of the control unit, the second and the third outputs of which are connected respectively to the setup and clock inputs of the frame control sequence generator, the data output unit, the first and second outputs of which are respectively the outputs D Simulator control, and a clock input and a conversion factor setting input are respectively connected to the output of the pulse generator and the control input of the simulator, the first mode input and the start input of the control unit are respectively inputs of the Switching and Start signals of the simulator, and the setup input is connected to the installation input of the device and the installation inputs of the memory unit and the data output unit, characterized in that, in order to increase the functionality by introducing additional simulation modes, an addressing block, a frame length counting block, a data multiplexer, a delay block, an error fixing block, and a data multiplexer counter are entered into the simulator, with the output of the pulse generator connected to a clock input

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control unit, the fourth, fifth and sixth outputs of which are connected respectively to the counting input of the data multiplexer counter, the clock input of the error fixing unit and the enabling input of the data output unit, the first and second information inputs and the gate input of which are connected respectively to the output of the data multiplexer and the first and the second outputs of the block of fixation of errors, “the first and second information inputs and the entry gate of the recording of which are connected respectively to the output of the control sequence generator frame and to the Data and Recorder inputs of the simulator, and the installation input to the second output of the control unit and the installation inputs of the addressing unit and the data multiplexer counter, output connected to the data multiplexer address input, information input of the addressing unit and the first information input of the frame length counting unit, The second information and synchronization inputs of which are connected respectively to the first and second outputs of the addressing unit, and the third information input and input of the recording strobe, respectively, from the input Data and Recording of the H-1itator, the output of the Block | Account of the frame length is connected to the second input of the control unit mode and the inputs of the output block mode and the frame control sequence generator, the information input connected to the output of the data multiplexer, the group of information inputs of which are connected to the output group of the memory block the second address input of the addressing unit connected to the first output, the strobe inputs of the end of the control sequence, the beginning of the cycle and the end of the cycle of the control unit are connected accordingly It is connected with the second output of the error fixing unit and the first and second outputs of the delay unit, the input and the second output of which are connected respectively to the second output of the error fixing unit and synchronizing the input of the data output unit.

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Claims (1)

Formula of the invention A simulator for testing the components of a mono-channel local area network containing a memory block, the first address input, the information input and the input of the recording strobe of which are respectively the addresses Address, Data, and Simulator record, and the mode input is connected to the first output of the control unit, the second and third outputs of which are connected respectively to the installation and clock inputs of the driver of the control sequence of the frame, the data output unit, the first and second outputs of which are respectively GOVERNMENTAL outputs data ^and: simulator control and clock 'input, and the input job scale factor are respectively connected to the generator output pulse and the control input of the simulator, the first modal input and input trigger inputs are the control unit accordingly signals Switching and Start simulator and adjusting input coupled with the installation input of the device and the installation inputs of the memory unit and the data output unit, characterized in that, in order to expand the functionality by introducing an additional of the simulation modes, the addressing unit, the frame length counting unit, the data multiplexer, the delay unit, the error fixing unit and the data multiplexer counter are entered into the simulator, the output of the pulse generator being connected to the clock input of the control unit, the fourth, fifth and sixth outputs of which are connected respectively with the counting input of the counter of the data multiplexer, the clock input of the error fixing unit and the enable input of the data output unit, the first and second information inputs and the gate input of which are connected respectively with the output of the data multiplexer and the first and second outputs of the error fixing unit, “the first and second information inputs and the input of the recording strobe of which are connected respectively to the output of the driver of the control sequence of the frame and to the inputs Data and Record of the simulator, and the installation input to the second output of the control unit and the installation inputs of the addressing unit and the counter of the data multiplexer, the output connected to the address input of the data multiplexer, the information input of the addressing unit and the first information input of the unit frame length counts, the second information and synchronizing inputs of which are connected respectively to the first and second outputs of the addressing unit, and the third information input and recording strobe input, respectively, with the Data ”and“ Record ”inputs of the simulator, the output of the block, frame length counting is connected to the second input the control unit mode and the output mode inputs of the output unit and the driver of the control sequence of the frame, the information input connected to the output of the data multiplexer, the group of information inputs of which are connected to the output block of the memory block, the second address input connected to the first output of the addressing block, the strobe inputs of the end of the control sequence, the beginning of the cycle and the end of the cycle of the control unit are connected respectively to the second output of the error block and the first and second outputs of the delay unit, the input and second output of which are connected respectively, with the second output of the error fixing unit and the clock input of the data output unit. FiL SB Fia. 5 SB fi g. 6