SU862135A1 - Data input device - Google Patents

Description

(54) DEVICE FOR INPUT OF INFORMATION

one

The invention relates to the field of computer technology, automatic data transfer and can find a name in information input systems in a digital computer.

A device for receiving information used by the data processing systems using a computer, which provides hardware for the exchange of information of variable length t4, is known.

The closest in technical essence of the invention is a device containing an input register, a command register and a control unit, the first, second and third inputs of which are connected respectively to the clock signal, the digital computer control unit and the output of the command register. The inputs of the input register and the command register are connected respectively to the source of information and the computer memory block. The output of the control unit is connected to the second input of the input register,

This device receives a serial code from an external device, converts it into a parallel code and outputs it to the memory of a digital computer. From external device

Arrays of information of various lengths can arrive, and the number of information bits is not a multiple of the exchange format of the information exchange device with the computer memory block. Since the number of remaining bits at the end of the array can be different, the interval for receiving two adjacent requests for issuing information 0 at the end of the array can be less than the BpeiMeHH information record from the input device to the DVR memory block. In this case, a loss of information may occur, which is unacceptable in information processing systems, ayavdh work in real time.

The aim of the invention is to increase the reliability of the device. 20 this goal is achieved by introducing into the device containing the first register, second register and control block the third register, the delay block, the request signal generator and the end signal generator of the message end, the first input of which is connected to the second 1 control input of the control unit, the second input is from the second output of the second register, and the output of the connector Ian with the first inputs of the delay unit and the sanpoqa signal conditioner, the second input of which is connected to the third output of the control unit, and the third input - with the output of the delay unit, the second input of which oedinen with the fourth output of the control unit, a fifth output is connected to the first input of the third register, a second input coupled to an output of the first register. The outputs of the requestor and the third register are the first and second outputs of the device, respectively.

The drawing is a block diagram of the device.

It contains the input register (first) 1, the control unit 2, the command register (second) 3, the output register (third) 4, the delay unit 5, the signal generator at the end of message 6, the signal conditioner of request 7 and external and internal communications 8-23.

The device works as follows.

Register 3 of the computer memory on bus 8 records an input command, which indicates the type of external device, the method of packaging the information entered into the computer, and other signs.

Depending on the type of information received, the output of the command register 3 to block 2 is given to the initial setting of the bits of the counter controlling the reception of information to register 1. In addition to the counter, block 2 contains a clock generator triggered by strobe signals coming from bus 10 from the device computer control. These signals synchronize the transfer of information to the computer memory. The bus 11 from the subscriber receives the clock frequency signals, with the help of which the synchronization is performed when receiving information B register 1.

Register 1 consists of a receiving part and a reception permitting circuit, made in the form of a decoder. The input 12 of the register 1 receives information signals from the external device. The register is filled by the control signals from output 13 of block 2.

Since the information from the external device is encoded in different ways, i.e. differs in the order of the weights of the bits and the number of bits in the physical unit of information, then the data word displayed in the computer may have a different length. The data word format is generated using control signals at output 14 of block 2. When register 1 is filled, information from its output 15 in parallel code goes to register 4. Register 4 capacity is determined by the exchange format of the input device and the computer memory block.

After the data word has been formed in register 4, the availability and formation signal arrives at block 7 at input 16 of block 2 and arrives at block 7. If there is no signal The end of the message from the output 17 of the generator 6 at the output 18 of block 7 forms a request to the computer control block ., and information from the output 19 of register 4 enters the computer memory.

In the presence of a signal. End of the message, a request for an information availability signal is blocked. The end of message signal is formed from the current coordinate code of the array, coming from the output 20 of block 2, and the code {determining the type of external device, coming from the output 21 of register 3.

At the end of the array, when only one bit of data can appear in a data word issued by a computer, an artificial duplication to the multiplicity of the exchange format is performed, in order to avoid loss of information. The formation of a pause is carried out in block 5 by the signals from outputs 17 and 22, respectively, of the driver. 6 and block 2. When a signal arrives at the end of the message in block 5, the register filling code, coming from the output 22 of block 2, starts the pause duration. At that moment, when the length of the pause becomes a multiple exchange format, a signal is output to the output 23 of the block 5, which in block 7 forms a request to the computer control block, and the information from the register 4 enters the computer memory.

Thus, the device provides hardware tools for analyzing the number of bits of the received information at the end of the array. By the number of bits in the input register, at the end of the array, a delay in issuing a request to the computer is formed, which ensures reliable information transfer without loss of useful information in the exchange path.

The proposed device is especially effective when building large computing systems that serve a large number of subscribers in real time, as it ensures reliable transmission of information to a computer.

Claims (2)

Invention Formula A device for entering information containing a first register, a second register and a control unit, the first, second and third inputs of which are connected respectively to the first, second inputs: the device and the first output of the second register; the first output is connected to the first input of the first register, the second input connected to the third input of the device; the input of the second register is connected to the fourth input of the device; it is connected with the fact that, in order to increase the reliability of the device, a third register, delay unit, simulator catch request signal genera- tors and end the message, the first input of which is connected to the second output of the control unit, the second input - to the second output of the second register, and an output coupled to the first inputs of the delay block and shaper request signals, a second input coupled to the third output. the control unit, and the third input - with the output of the delay unit, the second input of which is connected to the four output of the control unit, the fifth output of which is connected to the first input of the third register, the second input of which is connected to the output of the first register, and the third register are the first and second outputs of the device, respectively. Sources of information taken into account in the examination 1. T. e W.P. Avion appl cation of qdvahced LSt mlcroprocrammed pfocessor4 Proc. 3EEE Conf. 1974, CTpi. 2. Ovchinnikov B, H. Automatic information exchange device. 5 M., Energie, 1971, p. 141. fig. 511, (prototype). // // / 15 f f nineteen W eight Lj f / / U f7 //