SU1432539A2 - Multichannel device for connecting data sources to common trunk line - Google Patents

Abstract

The invention relates to a digital computing technology, can be used in systems named dich several asynchronous sources of information, and is an improvement of the known device in a. with. No. 1290325 The goal is to increase the capacity of the device. The goal is achieved by introducing into each channel of the device an IL1 1 element. The device increases the number of fixing signals in the channels, compresses the transmission of data over the 11 i-sh in time.

Description

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The invention relates to the field of digital computing I, can be used in data processing systems to control access to shared resources, and is an improvement to the device under the basic author. St. No. 1290325,

The purpose of the invention is to increase the pro- duction capacity of the device for the jC4eT formation of an additional I-signal Fixation, I Figure 1 shows the structural 1-diagram of the device in FIG. 2 - the structure of the channel diagram in FIG. 3-8 - Functional diagrams of the unit, the buffer memory node, the synchronization node, the switching elements and the Poll Signal Generator; nafig.9

| data placement in RAM; in fig 10 and

111 - time diagrams of data recording in channel RAM and data transfer

| channel

 The device (FIG. 1) contains the channel: ly 1, bus 2 of the generalized application, bus 3 of the input / output of the priority signal,

: bus 4 and 5 signal inputs / outputs

fixing for the signal and ring signal

i interrogation, input bus 6 data bus

: 7 and 8 channel control and sync

Inal, output data bus 9 and input

110 logical units

Each channel 1 (FIG. 2) contains an outgoing block 11, trigger 12, sixth, fifth, fourth and second elements AND-NOT 13-16, third switching

; Element 17, first and third, elements

; AND-NOT 18 and 19, - the second are switching

element 20, signal generator 21 | op | dew, first switch element 22, internal communications 23-25 and external communications 36-44 of channel 1,

Block 11 of FIG. 3 contains a buffer memory node 45, a synchronization node 46, elements HE 47 and 48, AND 49, trigger 50, AND-NE 51 and OR 52, internal links 53-60 of block 11. ,

The buffer memory node 45 (FIG. 4) contains a memory (RAM) 61, a group of elements And 62, a register 63 of the final address, a multiplexer 64, a pulse shaper (bdnovibrator) 65, a comparison circuit 66 and an address counter 67.

The node 46 synchronization (Fig, 5) contains the first element And 68, triggers 69 and 70, the second element And 71, the elements NOT 72 and 73, the third trigger 74, the first element AND NOT 75, the element OR NOT

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76, the second element AND-NOT 77, the third element AND 78, the reinforcing elements OR 79 and 80, the third element is NOT 8t, the third element is AND-NOT 82,

The switching elements 17, 20 and 22 (FIGS. 6 and 7) contain an element AND-NO 83, element NO 84, elements AND 85 and 86, elements AND-HE 87-89, 0 Generator 21 polling signals

(FIG. 8) contains an element NOT 90, a trigger 91, an element SH-NOT 92, an element NOT 93, and a pulse shaper (single-oscillators) 94 and 95. The drawings IL-5 also show the element OR 96 and its input 97,

The device works as follows.

The signal at input 10 (logical 1) enters line 34 through the switching element -22 of channel 1 ,, if the enable signal is present at input 44, otherwise logic 1 at output 3i goes to

next channel input. The presence of a signal at input 44 indicates that this channel 1 is included in the set of channels organizing the connection of information sources to the channel.

about highway

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Thus, the signal (logic level O) at the second output of the switching element 22 is one of the conditions for generating a ring-scan signal in the channel. Consequently, only in one channel can a ring interrogation signal be generated, the device bus enters the bus 2 to send a signal to the output to the common line from all channels - sources of information. At input 43 of each channel 1, a signal is received for a connection from one source of information. The latching signal in the bus 4 is generated by the generator 21 in the presence of a signal Log, 1 in bus 2 and a signal (logic level O) at the second switching output

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element 22,

The fixation signal generated by the generator 21 through the | AND-NOT 19 element is fed to the input of the recording of the trigger 12 and simultaneously via the bus 4 inputs0

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em to the input of the second channel 1, through the element OR 96 and the open element AND-NOT 18 and the element AND-NOT 19, the fixation signal of the order is fed to the recording input of the trigger 12 and the output 4 "of channel 1

and t, d., through all channels to the output

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channel 1, where the signal is fixation

 attenuates on closed element AND-NOT 18. Passage through the internal chains of the channel (input F31 - elements OR 96, AND-NOT 18, element AND-NOT 19, output FZO) the fixation signal captures (records) the leading edge, in each channel, the presence of the application (Log.G) for connection to the common trunk, if it is presently present at the information input of trigger 12,

Trigger 12 controls the switching element 17. The internal ring interrogation signal at output 29 (worked on the falling edge of the lock signal in the line 35 by the generator 21) goes to the switching element 17. If there are applications for triggering 12 to connect to the common highway, the ring signal polling comes from the output of the switch 17 through the element AND-NOT 15 to the input of the record trigger 69, thereby starting the mechanism for issuing information to the common highway. At the end of the cycle of issuing information at the output of the NAND 82 element, a ring interrogation signal is generated in line 25 (level

25 and the order of their placement in RAM 61 is shown in FIG. The first word in the data array is the array identifier. It is entered in the first cell of RAM 61 (at the zero address). In the sloping O), which, through the following cells of RAM 61, is placed an IS-NOT 16 cop at input 5

the data array itself. The address of the last cell of RAM 61, in which the last word of the output array is placed, is entered into the register 63 of the final address 63. The time diagram of the writing of the final address into the register 63 of the final address is shown in Fig. Yu. On Fig shows a time chart for recording information in the cell RAM 61.

channel 1 (the entrance of the next channel in the ring). In the absence of an application in the trigger 12 of channel 1, the ring interrogation signal arrives at output 5, through output 31 ger 69.

the switch 17, the minus of the TrigV, depending on the turn-on signal at the input 44 of the channel, the ring interrogation signal from the input 5 can pass through the switching element 20 either to the input 33 of the generator 21 and the elements AND-NOT 13 and 14, or to the input of the element AND-16

In the first case (the turn-on signal at input 44 has a logic level: 1) the ring interrogation signal is either regenerated (if generator 21 has conditions for generating the ring interrogation signal) or is output to channel 5. In the absence of an application in this channel (trigger 12 is not cocked, i.e. the logic level O at the direct output), the ring interrogation signal through the elements AND-HE 14 and 16 enters output 5, and in the presence of an application in trigger 12, the signal ring survey through the elements AND NOT 13 and 15 enters the block 11,

In the second case (the enable signal at input 44 has a logic level O, which means the channel is turned off from the number of trunk transmitters), the ring interrogation signal is output to channel 5 through the AND-NOT element 16. This means that this channel is disabled and the priority signals (P1 ), fixing a quotation (FZ), a ring interrogation (co), is simply transmitted through this channel further along the chain to the input of the next channel.

The above-described logic of operation of a multi-channel device synchronizes the operation of all channels and directly includes a mechanism for transferring data from the channel to the common highway. In each channel, record, store and store

data to the common highway occurs through block 11.

The data needed to be inserted into the common highway is pre-loaded into the RAM of the 61 channels. The data structure and the order of their placement in RAM 61 is shown in FIG. The first word of the data array is the array identifier. It is entered in the first cell of RAM 61 (at the zero address). In the following cells, RAM 61 is located

the following cells RAM 61 is located

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the data array itself. The address of the last cell of RAM 61, in which the last word of the output array is placed, is entered into the register 63 of the final address 63. The time diagram of the writing of the final address into the register 63 of the final address is shown in Fig. Yu. On Fig shows a time chart for recording information in the cell RAM 61.

Array of the array in a common highway. happens in the order in which it is recorded in RAM 61, i.e. the first one is with the identifier, then the first word of the array, then the second, and so on. The contents of counter 67 (RAM address 61) are incremented by one with each word entered (input +1 MF 53). The output continues until the contents of the counter 67 (constantly increasing) are equal to the contents of the register 63. When they are equal, the signal of the logical unit is output from the output of the comparison circuit 66 (ShSr 55). And the transfer of information to the trunk stops. Figure 11 shows a detailed timing diagram of the signal transmission channel of the device,

The timeline diagram is divided into three parts. The first (top) shows the process of requesting the transmission channel of the device. The second part shows the response of the channel that has the highest priority to this request. And in the third: the main one, the part of the diagram shows the whole process of building the array in the main trunk of the device by the channel.

The organization of information transmission to the common highway starts with a signal. Start at input 43, Triuger 50 switches on the front edge of this signal and, via the OR 52 element, puts the signal into the bus 2,

the level in line 54 Strobe, and logical 1 at the direct output of the trigger 70 prepares the element AND 71 to skip the frequency pulse F, which through the element OR 79 enters the bus 56 (signal C1) and the bus 4 FZO, simultaneously with this signal from the RAM 61 the contents of the first cell, where the identifier is stored, the data array, i.e. The impulse Cf is an impulse to the bus channel b, having a height; on the leading edge of the signal, the start starts the one-shot 65 and generates a setting pulse to the initial state (reset pulse) of the sweeper 67. The difference from the logical level to logical 2 | enters channel 1, your priority. This differential, through the epi- element 93, arrives at the inverted input of the one-vibrator 94, which forms a pulse of fixation of the channels in the device channels and, through the element AND-HE 19, outputs it to the output of channel 4. On the trailing edge of this 14-pulse, a one-shot 5 is launched, which forks the ring pulse.

The signal (impulse) of the ring oprog through the switching element 17, the element AND-NOT 16 enters the output of the channel 5

; the transfer to the transmission receives a lock-fix signal (F31) through the chain-KJe, which enters its input 4. By the leading edge, the F31 signal captures the transmission in the trigger 12 of channel f (the forward output of the trigger 12 sets the level logical 1) And then the fixation signal of the application through the elements AND-NOT 18 and 19 is transmitted along the chain further to the input of the next channel

Then, the ring interrogation signal received at the 1st channel (at input K01) through the switching element 20, the AND-NE elements 13 and 15 switch the trigger 69 and firing after setting up the logical level at its inverse output. On the trailing edge of the channel frequency Ff, the census of logical 1 from trigger 69 to trigger 70, Logic O from the inverse shoulder of trigger 70 through the element Y-HE 75 sets the resolving

15

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Sampling with identifier array Backstage, signal 01 switches trigger 74, which by logic level O from its direct output, through IS-NE 75 element supports the resolving level of logic 1 in line 54 Strobe and simultaneously with frequency pulse F, through trigger I-HB 77 69 and trigger 70. Logic 1 on inverted trigger output 74 prepared

element 78 and to pass a pulse --- frequency F, which, after passing through 25 elements 78 and 1118 80, enter 57 (signals C2), each issued pulse C2 accompanies (builds) the contents of RAM cells 61.

The generated signal C1 through the element OR 96 G enters the .4 circuit of the FZO signal. While the data is being output, from the i-ro transmitter (application processing), the new signal at input 4 captures the new applications that appeared. . in channels 1 during this time, it is confirmed by the channel that issued the old ones, and the signal generated by the ith channel QO in bus 5 also serves these newly recorded applications ,. thereby increasing the throughput of the trunk, since the data transfer from subsequent channels in this case begins immediately after the end of the transmission by the i-th channel.

On the element SHS-HE 76, the signals C1 and 02 generate the counting signals (+ 1 C, 53) for the counter 67. The Ready signal at input 42 connects (for the whole time of issue) through the multiplexer 64 to the address input of the RAM 61 the contents of the counter 67, Thus The contents of the RAM 61, starting from the zero slot, are connected in series through the AND element 62 to the data bus 9. After the second to last word of the array is increased, the contents of the counter 67 become equal to the contents of register 63 and therefore the signal Log, 1 from the output of the comparison circuit 66, resolves simultaneously with the output of the last 40

45

50

55

the level in line 54 Strobe, and logical 1 at the direct output of the trigger 70 prepares the element AND 71 to skip the frequency pulse F, which through the element OR 79 enters the bus 56 (signal C1) and the bus 4 FZO, simultaneously with this signal from the RAM 61 the contents of the first cell, where the identifier is stored, the data array, i.e. The impulse Cf is the impulse of the tracking data C2 through the elements AND 82, OR 81 of the signal KP in line 58. This signal indicates the end of the transfer of the array data to the common line On the leading edge of the signal KP through the element And A9 is reset the trigger 50 and with it the Ready signals in line 42 and Bus bar 2. At the same time, the signal KP through the element I-HE 16 is output further along the chain in the form of a ring interrogation pulse on output 5 of the CC from the i-ro channel.

This completes the data transmission cycle of the i-M channel to the common trunk.

Thus, due to the asynchronous nature of the appearance of the transmission request signals (requisition), the following situation occurs. When vivsha from the first application causes the triggering of the formation of the FZ and KO signals in the canape with the highest priority. The signal of the Federal Law, the passage through all channels, fixes the presence of a transfer to the front with a leading edge. And the applications that came a little later will not be fixed, since the leading edge of the FZ signal has already passed. Therefore, only the fixed application is serviced, and the ring interrogation signal bypasses all other channels of the device and returns to the channel with priority. There he discovers that a request for service has remained on the system in the Bus Service. And the transmitter with high priority re-launches the chain of formation of the fixation signal of the FZ application and the ring QoS demand. They will again register the applications received by this time in the device and begin their processing. Thus, every time, the time is lost for the initial stage of forming the signals of the PV and QO. And with a big

the intensity of the arrival of a quotation at Dineny, respectively, with additional and their asynchrony, it turns out that for some channels are processed

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faster / than others. This leads to an accumulation of demand in the channels, an increase in unproductive losses; time due to the presence in the system of a single mechanism for the formation of the FZ signal, i.e. Special time is required for the generation and distribution of the FZ signal over the channels of the device, and this time consistently enters the total time of recording and processing the applications in the channel (i.e., is summed up with the processing time of the application), thereby increasing the unproductive time and reducing the throughput devices. And in the proposed device, each channel can generate the FZ signal at the beginning of processing its own application. In this case, the fixation of new quotes by this signal FZ occurs in parallel with the data channel, since the FZ signal is generated from the signal C1, which is developed first, and the data starts after this and is accompanied by a light pulse C2. It is this effect that allows to increase the capacity of the device.

Claims (1)

Invention Formula A multichannel device for connecting information sources to a common highway by aut. St. 1290325, characterized in that, in order to increase the capacity of the device, an OR element is inserted into each channel, the first input of the OR element i-ro (, n) of the channel connected to the output of the third AND-NOT element (il) -ro channel, the first input of the element OR of the first channel is connected to the output of the third element AND-NOT of the n-th channel, in each channel the second input and output of the element OR with the output of the synchronization node and the first input of the first element AND-NOT. FIG. one Figg Fi.d W A J)% r 36 37 D With h J) 65 Q vi 53 sixteen f6 6f 62 63 67 66 I five t 55 4k KOI 5L-1 t di-l FC, .6 85 J2 1 53 L P 87 3i4 no 3L ZB 27 Z9 h 91 Jj J4 90 l 89 W n J / Phage. 7 D li ffS n. J 9 29 2 FIG. eight Turning on " opt for A 42 fJycK Application one P1 FZO koo fzp koi. 5t h 5i- J2 69 M p p m p p p G F Tg C1 Tr cr. 1Chr, CP fnpof Ann (e, F301, KOOi. 40 60 N p p n p p p 59 70 66 7f 1 l 53 55 eight 55 I-m I-1 r A A P S g§ m I one f-ljt and | - ||| I $ 11 Jh P P P I-1 r A A p ±: H P 1 P f st t sll v , P