RU2043658C1 - Method for multichannel transmission of information packets and device for implementation of said method - Google Patents

Abstract

FIELD: devices for reading and transfer of digital information. SUBSTANCE: method involves generation of basic samples for each information source, conversion of said samples to asynchronous sequences of information packets, generation of group asynchronous packet sequence. Rate of pulses in said sequence is not greater than sum of pulse rates in asynchronous sequences of information packets from information sources. This rate also does not exceed transmission rate of communication channel. This sequence is then transmitted through communication channel. Asynchronous sequences of information packets for each information source are stored in the same order they were generated. Transmission of group asynchronous sequence of information packets is performed for high-priority information sources. If signal from a priority information source is absent in transmission cycle during given moment, signals from other information sources are transmitted. Device that implement said method has information sources 1, units for elimination of redundancy and for packet generation, first and second double registers units 3 and 5, first and second cyclic commutators 4 and 6, master oscillator 7, timer 8, first and second counters 9 and 18, first and second memory units 10 and 14, decoder 11, channel memory units 12, switch 13, comparison unit 15, writing counter 16, reading counter 19, register 17. EFFECT: increased reliability of transfer, order of generation of information packets is retained. 3 cl, 3 dwg

Description

 The invention relates to techniques for collecting and transmitting digital information and can be used in collecting asynchronous information streams and forming a common stream for transmission over a synchronous communication channel.

 A known method of synchronous data collection, which uses a cyclic poll, which consists in periodically alternately polling the buffer registers of the input messages and forming a single message stream with a frequency equal to the sum of the frequencies of the input streams (1).

 A device for implementing this method includes signal sources, buffer message registers according to the number of signal sources, a switch, a synchronizer, a unit for generating cyclic polling programs.

 The disadvantages of this method and a device for its implementation, using cyclic polling and message switching, are the large redundancy of the information received, since the polling frequency is calculated based on the maximum frequencies of information output by the sources, and the complexity of processing and decoding the received stream at the receiving side, in particular, selecting a specific user data array. At the same time, difficulty arises with the search and retrieval of official information necessary for the interpretation and processing of this array.

 These shortcomings are eliminated (2). The first drawback is overcome by using the means and methods of reducing redundancy both in the general path and in the paths of individual sources; the second drawback associated with message switching is overcome by using the principles of packet information transmission by forming in the paths of individual sources, the so-called signal packets from these sources. Packages are arrays of data with a volume of several thousand bits.

 However, the use of the principles of reducing redundancy in information collection devices in this method leads to non-uniformity of the information flow at the output of these devices, to asynchrony of messages or packets in the compressed information path.

 There are many ways to collect information, including packetized, from asynchronous sources to the common path. The collection method (3) consists in the direction from the central computer to the sources of information of programmable cyclic queries, the collection of response information arrays, the rejection of idle arrays, the formation of a single stream of asynchronous arrays and its leveling. The device for its implementation contains signal sources, information compression units, buffer registers, response bus, request bus, information processing unit, timer, master oscillator, processor, address counter.

 The disadvantages of this method and device are low speed, a large amount of hardware, in addition, a large amount of buffer memory is required to equalize the asynchronous packet stream.

 The first two drawbacks are eliminated (4). This is a well-known method of collecting information messages consists in programmatically polling the input registers and forming a single synchronous stream with a frequency equal to the sum of the frequencies of the input streams, reducing information redundancy and forming addressable information messages, forming a single asynchronous message stream, and also recording the entire asynchronous message stream in output block of buffer memory and synchronous reading of information from it with the repetition rate of output messages.

 A device for implementing this method contains information sources, memory registers according to the number of input paths, a cyclic switch, a polling program generation unit, consisting of a master oscillator, timer, counter, memory unit and decoder; a second counter, a second memory unit, a third counter, a memory register, a message former, an individual channel address former, a redundancy reduction unit.

 The disadvantages of this method and device for its implementation are as follows.

 Firstly, the required buffer memory for equalizing the asynchronous stream is large (5). Through this memory, the entire information flow passes to the output, acquiring a large time delay, which in some cases is unacceptable.

 Secondly, information arrays are transmitted to the output channel in the order of receipt, which excludes the organization of priority servicing of sources.

 The closest in technical essence (prototype) should be considered a method of multi-channel transmission of a sequence of signal packets and a device for its implementation (6). This method consists in collecting, generating significant reports for each signal source, converting them into corresponding asynchronous sequences of signal packets of all sources, combining them into a group asynchronous sequence of packets with a repetition rate of at least the sum of the frequencies of the sources and the output signal in the transmission channel, in transmission channel packet group asynchronous sequence, the repetition rate of which corresponds to the frequency of the output signal in the transmission channel, in the delay ti group asynchronous packet sequence whose frequency exceeds the frequency of the output signal in the transmission channel and transfer it in subsequent transmission frames, when the sum of the frequencies of the source signals is less than the output speed of the transmission channel.

 A device for implementing this method contains signal sources, redundancy reduction units in terms of the number of sources, two blocks of double buffer registers, two cyclic switches, a clock, a timer, five counters, three memory blocks, two switches, a buffer register, a key, three registers, a block comparisons.

 The disadvantages of this method and device for its implementation are as follows.

 Firstly, when using this method and device for its implementation, there is a potential possibility of violating the order in time of signal packets from those channel sources whose previously formed packets were delayed for transmission in subsequent cycles. Let us explain this with the following example (6), Fig. 1.

 Let the priority of signal sources decrease from left to right, and the intensity of the appearance of packets at the first outputs of blocks 2 is approximately the same. When the device (6) is functioning, the signal packets of the highest priority sources (they, according to the prototype, n / 2 n are selected as the total number of signal sources) will freely pass into the main memory unit 14 for transmission to the synchronous channel. In this case, the number of packets in the transmission frame is chosen equal to n / 2 (for our case, 2). Signal packets of other sources (if any of the latter) will be accumulated in the buffer memory block in the general queue. Suppose that the first in this queue is a packet from the third source on the left, and during the next polling cycle, only the buffer register corresponding to the third channel contains the newly formed packet, i.e. Priority source buffer registers are empty. Then, according to the logic of the prototype in this transmission cycle, the first frame will include a packet from the buffer register of the third channel, and then the first one in the queue from the memory block, i.e., a packet of the same channel source, but formed several cycles earlier, t i.e. preceding the first transmitted. Thus, these method and device that implements it do not provide a sequence in time of occurrence of source packets from non-priority sources. This leads to the fact that when transmitting on a synchronous channel, the signal packets of some sources will be transmitted in the wrong order in which they were formed on the respective outputs of the channels. At the receiving end, in order to restore the sequence of succession (by the time attribute that each packet is equipped with), additional hardware costs (buffer memory, blocks for allocating packet numbers, etc.) will be required. In order to avoid these difficulties, and sometimes simply because of the impossibility (for example, limiting the weight of aircraft onboard equipment) of installing additional equipment, it is advisable to avoid such a transmission method and require the transmission of packets from all sources in the order they occur in time.

 Secondly, the use in a known method and device for its implementation of a common memory block for the accumulation of packets that did not pass into the channel requires that this memory block has a very large capacity. In the prototype, the volume of this memory block is determined by the product of the maximum difference flow between the input and output streams by the duration of the communication session.

 A memory block with a large volume requires a complex write and read circuit with multi-bit counters for input / output of information. It is much simpler to organize a memory of the same size using a combination of smaller blocks. In addition, a memory block with a large amount of memory is less reliable (8).

 The aim of the invention is to increase the reliability of transmission, taking into account the time of formation of information by eliminating the possibility of violation of the sequence in time of packets of any channel source.

 Figure 1 shows the functional diagram of the device; figure 2 the implementation of the channel memory block; figure 3 the structure of the survey sources.

 The device (Fig. 1) contains n sources 1.1-1.n of digital information, n blocks 2.1-2.n of redundancy reductions, m buffer registers 3.1-3.m, where m is the number of packets in the transmission cycle to the synchronous transmission channel forming the first block of registers, the first cyclic switch 4, n buffer registers 5.1-5. n, a second cyclic switch 6, a master oscillator 7, a timer 8, a first counter 9, a first memory block 10, a decoder 11, m channel memory blocks 12-12. n, key 13, second memory unit 14, comparison unit 15, third write counter 16, register 17, second read counter 18, fourth counter 19.

 The device and operation of blocks 1-11, 14-19 of the device are similar to the device and the operation of the corresponding corresponding blocks of the prototype.

 The channel memory unit 12 contains (FIG. 2) an OR element 24, a delay element 33, a recording counter 21, a playback counter 22, a memory unit 20, a comparison unit 23, the first 30 and second 29 inputs of the OR element 24 form the first and second clock inputs of the block, respectively , the output of the OR element 24 is connected to the control input of the comparison unit 23 and the input of the delay element 33, the output of which is the clock output 31 of the block, the information input of the memory unit 20 is the first 25 information input of the block, the second 28 information input of which is the installation input d of the recording counter 21, the clock input of which is connected to the first 30 clock input of the block, the first information output of the block 26 is the information output of the memory unit 20, the recording input of which is connected to the output of the recording counter 21 and the first information input of the comparison unit 23, the output of which is the second information output 32 unit, the read input of which is the installation input of the counter 22 playback, the output of which is connected to the read input of the memory unit 20 and the second information input of the comparison unit 23.

 The device operates as follows.

 Signal sources 1 are polled with polling frequencies generated by timer 8 and selected based on the satisfaction of the maximum polling requirements of each source. The streams of samples of sources 1, which are streams of parallel digital combinations of constant length, are supplied to the corresponding inputs of the redundancy reduction blocks 2, in which information signal packets are generated. The functioning of blocks 2 fully coincides with the functioning of similar blocks of the prototype. Since the frequency of words (digital combinations), i.e. the clock frequency of operation of unit 2 is selected to be twice as high as the frequency of polling sources, then the identification of significant samples will occur in the first half of the periods of polling sources.

 The output of block 2 asynchronously receives packets of constant composition. These packets arrive at the first inputs of the corresponding buffer registers 3.1-3.m, where m is the number of packets in the transmission frame in the asynchronous transmission channel and at the first inputs of the channel memory blocks 12.m + 1-12.n. The length of the buffer registers 3 and block cells 12 depends on the duration of the packets. Simultaneously with the beginning of the transfer from blocks 2 to registers 3 and blocks 12 of the generated packets from another output of blocks 2, the signal is received at the first input of the corresponding buffer registers 5.1-5.m, or at the second input of the channel memory blocks 12.m + 1-12.n "1", which is a ready signal, i.e. informs that in the corresponding register 3 or block 12 from the beginning of the sequence of the polling cycle is a finished package. The considered ready signal, passing through block 12, is recorded in its corresponding buffer register 5 (it goes to input 28 of block 12 and goes from output 32 to the first input of register 5). Thus, by the beginning of the next cycle of operation of the entire device, i.e. polling cycle by the first 4 cyclic switch of buffer registers 3.1-3.m and the channel memory blocks 12.m + 1-12.n and the second cyclic switch of 6 buffer registers 5.1-5.n, in registers 3.1-3.m and blocks 12. m + 1-12.n packets, and in registers 5.1-5.n signals "1" can either be present or absent, with a random distribution of these events. The operation of the device for recording packets and ready signals is synchronized by the master oscillator 7, the output signal of which forms in the timer 8 a grid of the necessary clock frequency. In FIG. 1 shows only the main connections of the master oscillator 7 and the timer 8 with synchronized blocks. This figure does not show the synchronization of device blocks by bits and parallel words and the synchronization of digital information sources 1 by polling frequency, which is half the word frequency of blocks 2. The operation of the device, primarily switches 4.6, is described by correlating the packet repetition rate and the cyclic frequency, received from the output of timer 8.

 In order to program the priority of polling channel sources, and, respectively, nodes 3, 5, 12, the device contains the first memory block 10 of the polling program, in the cells of which the sequence of addresses of nodes 3, 12, 5 is recorded in the required order. using the first counter 9, which with a packet repetition rate generates consecutive cell addresses of the first memory block 10, the digital combinations read from which, passing key 13, after decryption in block 11, control the channel keys iklicheskih switches 4 and 6, and resetting registers 3, 5 and interrogation unit 12.

 For a clearer understanding of the flow of information flows through the main units of the device, we consider a specific case, which is illustrated in Fig.3. Let each stream of one of the 4 sources (Fig. 1) have a transmission rate of 1.024 mb / s. The total speed of the output streams at the input of the first cyclic switch 4 is equal to a discrete random variable in the range from 0 to 4.096 mb / s. Let the given output speed in the transmission channel be equal to 2.048 mb / s, therefore, packets with a speed equal to 2.048 mb / s should follow at the input of block 14 from the output of switch 4. The switching frequency of switch 4 is selected not less than the sum of the maximum frequencies of the input and output streams, i.e., at least 6.144 mb / s. Let (figure 3) all sources have ready-made packets for transmission. With the beginning of the next cycle of polling (transmission), high-priority (first and second) channels are initially interrogated, and the signal packets freely pass through the switch 4 to the memory unit 14 for transmission. In parallel, the transmitted packets are counted in a cycle using blocks 6, 15, 17, 19, and when the threshold number of packets is transmitted (in this case, it is 2), a signal is generated that closes key 13, which in turn does not allow polling and transmission of packets to block 14 from the remaining sources of the switch 4. In this case, packets of unsolicited channels are accumulated in the order of their arrival in the corresponding blocks of channel memory 12.

 The reading of the signal packets from the blocks of channel memory 12 will occur every time in subsequent cycles on the principle of “first recorded first read”, when after polling priority sources (first and second in Fig. 3) they will not have one or more ready-made packets for transmission. The operation of switches 4 and 6 is as follows. The number of positions in the polling cycle of the switches is chosen equal to the sum of the maximum number of input packets (4 for the case considered in Fig. 1, n 4) and output packets (in this case, m 2), while the frequency of the master oscillator 7 is always selected as a multiple of the output frequency.

 A program for interrogating registers 3, in which current ready-made input packets can be found, and channel memory blocks 12, in which there are packets that did not go out in previous switch cycles, as well as current packets, and packets previously written to block 12 are earlier in the queue for transmission, composed in such a way that first high-priority sources were interrogated (buffer registers 3 correspond to them), and then all the rest (channel memory blocks correspond to them). The polling sequence of the registers 4 and blocks 12 is determined by the user and recorded in block 10.

 In accordance with the readiness of the input packets during the next polling cycle at the output of the first cyclic switch 4, an asynchronous sequence of finished packets takes place.

 Simultaneously with this sequence at the output of the second cyclic switch 6, there is a corresponding asynchronous sequence of ready signals "1". The last sequence goes to the input of the counter 16 to form the next recording address of the corresponding packet in block 14 and to the counting input of the fourth counter 19. The number stored in the counter 19 increases with the passage of the next packet. Before the start of operation, the number of output packets in the transmission cycle (in this case, 2) is entered into the register 17, based on the given output speed. After the count number of the counter 19 is equal to the number stored in the register 17, the output of the comparison unit 15 generates a signal "1" that closes the key 13, which in turn stops issuing the polling addresses to the decoder 11, polling and transmitting the remaining signal packets from sources stops in this cycle, since the number of recorded packets during this cycle in block 14 is equal to the threshold. As a result of this, accumulation in the order of arrival of packets in time in the blocks of channel memory of non-priority sources occurs. With the beginning of the next cycle of operation of the device, the counter 19 is reset to zero by the timer 8. The first packets of each cycle (in this case, 2), the number of which is equal to the number of output packets and also corresponds to the number of the highest priority sources, are recorded in the second memory block 14, which serves for leveling the output stream. Recording addresses are generated using the third counter 16, which is controlled by packet ready signals from the output of the switch 6. Read addresses are generated using the counter 18 using the corresponding signals from timer 8.

 The channel memory block operates as follows.

 The first input 25 of block 12 receives the current finished packet from block 2, which is recorded in the memory block 20. Record addresses are generated using the write counter 21, which is controlled by the packet ready signal received at the second input 28 from the second output of block 2 and the clock signal at the first sync input 30 from the first timer 8. Read addresses are formed using the counter 22 according to the corresponding cyclic polling signals generated by the decoder 11 and fed to the input 27 of the block 12. The clock signal received at the input 30 from timer 8, cl INH to write (if necessary) a new packet, passing the OR gate 24 and delay element 33, it enters the sinhrovyhod 31 unit 12 for supplying the clock corresponding to the double buffer register 5, which stores information about the availability of the finished package for transmission in the channel. The clock signal from the output of the OR element 24 is supplied to the control input of the comparison unit 23, which compares the previously recorded values of the recording counters, the number in the counter 22 (this indicates that in block 20 there are packets for transmission previously not transmitted) gives a ready signal "1 "to the second information output 32, which is fed to the first input of the corresponding register 5 and sets it to" 1 ".

 Performing the operations of the method using the described device does not require significant explanation. The memory capacity of block 14 corresponds to twice the number of packets in the polling-transmission cycle, the memory blocks of the channel memory do not exceed the product of the maximum packet stream of this channel by the duration of the communication session.

 The proposed method of collecting information provides matching with the synchronous output stream of asynchronous input streams, while eliminating the possibility of disruption in the transmission of signal packets from non-priority sources, the packets of which were previously accumulated in the corresponding channel buffers. Obviously, the greatest probability (P ≈ 1.0) of direct passage to the exit (Fig. 1) is in the packets of the first input paths by the polling number, which allows organizing priority service with a direct correspondence between the number of the polled channel and its priority.

Claims (3)

 1. A method of multi-channel transmission of information packets, based on the formation of signals of significant readings for each information source and converting them into the same asynchronous sequence of information packets, from which a group asynchronous sequence of packets is formed, the pulse repetition rate in which is not less than the sum of the pulse repetition rate in the same asynchronous sequences of packets of information of information sources and transmission frequencies over the communication channel, and transmit over the communication channel , characterized in that, in order to increase the reliability of the transmission, taking into account the time of formation of information packets, delay asynchronous sequences of information packets in order of formation in time for each information source, the transmission of a group asynchronous sequence of information packets is carried out from priority information sources and in the absence of which - Some of them in the transmission cycle at a given point in time transmit signals from other sources of information.  2. A device for multi-channel transmission of information packets containing an information source, redundancy reduction units, buffer register groups, first and second cyclic switches, first, second, third and fourth counters, a master oscillator whose output is connected to the timer input, register, first and the second memory blocks, the decoder and the comparison unit, the outputs of the information sources of the first and second groups are connected to the first inputs of the same blocks of redundancy reduction of the first and second groups, the second inputs of which are combined They are the first control input of the device, the first and second outputs of the redundancy reduction blocks of the first group are connected to the first inputs of the same buffer registers of the first and second groups, the first output of the timer is connected to the input of the first counter, with the second inputs of the buffer registers of the first and second groups and the sync input of the fourth counter, the outputs of the buffer registers of the first and second groups are connected to the inputs of the first group of the first and second cyclic switches, the outputs of the buffer registers of the third group are connected to the inputs and the second group of the second cyclic switch, the outputs of the buffer registers of the third group are connected to the inputs of the second group of the second cyclic switch, the output of the first counter is connected to the first input of the first memory block, the second input of which is the second control input of the device, the outputs of the decoder are connected to the third inputs of the buffer registers of all groups, with control inputs of the first and second cyclic switches, the second timer output through the second counter is connected to the first input of the second memory block, input p the register is the third control input of the device, the output is connected to the first input of the comparison unit, the second input of which is connected to the output of the fourth counter, the input of which is connected to the output of the second cyclic switch, the output of the third counter is connected to the second input of the second memory block, the output of which is the output of the device, the output of the first cyclic switch is connected to the third input of the second memory block, characterized in that, in order to increase the reliability of information transfer, channel blocks are introduced into it memory by the number of differences between the number of information sources and the number of packets in the transmission cycle over the communication channel and the key, the first input of which is connected to the output of the first memory block, the output is connected to the decoder input, the second key input is connected to the output of the comparison unit, the first and second outputs the redundancy reduction blocks of the second group are connected respectively to the first and second inputs of the same channel memory blocks, the first information outputs of which are connected to the inputs of the second group of the first cyclic switch, the first inputs of the buffer registers of the third group are connected to the second information outputs of the same name blocks of channel memory, the first clock inputs of which are connected to the first output of the timer, the clock outputs are connected to the second inputs of the same names buffer channels of the third group, the outputs of which are connected to the second clock inputs of the same blocks of memory channel channel memory connected to the corresponding control inputs of the second cyclic switch, the output of which is connected to the input of the third counter a.  3. The device according to claim 2, characterized in that the channel memory unit contains an OR element, a delay element, a recording counter, a playback counter, a memory unit, a comparison unit, the inputs of the OR element are the first and second clock inputs of the channel memory unit, the output of the OR element is connected with the control input of the comparison unit and the input of the delay element, the output of which is the clock output of the channel memory block, the information input of the memory block is the information input of the channel memory block, the second information input of which is there is a setting input of the recording counter, the sync input of which is the sync input of the channel memory block, the first information output of which is the information output of the memory block, the recording input of which is connected to the output of the recording counter and the first information input of the comparison unit, the output of which is the second information output of the channel memory block, the input reading which is the installation input of the playback counter, the output of which is connected to the reading input of the memory unit and the second information progress of the comparator.

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