GB1573758A - Symmetrical time division matrix - Google Patents

Description

(54) A SYMMETRICAL TIME DIVISION MATRIX (71) We, THOMSON-CSF, a French Body Corporate, of 173, Boulevard Haussmann-75008 Paris-France, do hereby declare the invention, for which we: pray that a patent may be granted to us, and the method by which it is to be performed., to be particularly described in and by the following statement:- The present invention relates to symmetrical time division matrices which make it possible, in particular in exchanges., to switch a signal from a given position in an input frame to a given position in an output frame. These matrices are so-called because they externally perform the role of a matrix.

It is well known, where the transmission of telephonic communications is concerned, to sample the speech signals at a frequency of 8 kllz and then to convert the samples thus obtained to an 8-bit form, each sample being represented by an 8-bit word. These words are then multiplexed in accordance with a frame of 32 time slots IT (2 for signalling purposes and synchronisation) so that it is then possible to transmit through a multiplex link 30 simultaneous calls represented by a binary signal occurring at a rate of 2.048 MHz.

This kind of processing of telephony signals, known as PCM (pulse code modulation), makes it possible to use fully electronic automatic switching centres and numerous designs have been proposed which make it possible to create switching centres of this kind.

These designs often comprise an element known as a time switch which makes it possible to modify the distribution of a channel in a frame. To do this, a memory is filled with the 32 words of a frame in the order of their arrival, and the memory emptied by reading out the 32 words in the order required to obtain the desired frame format.

A time switch of this kind, quite obviously, only enables switching to be performed within one and the same frame, so that in order to change the frame it is necessary to use more complex structures which more often than not have recourse to other circuits which are referred to as spatial switches.

According to the present invention there is provided a symmetrical time-division matrix for switching input time-slots of a first set of input series PCM junctions to time-slots of a second set of output series PCM junctions, said matrix comprising: parallel/series converting means connected to receive simultaneously and synchronously in serial form said input timeslots from each one of said input parallel array of series PCM junctions and to deliver in series all the PCM codes of said input time-slots, during the duration of one timeslot, in parallel format; time division switching means connected to receive said series of parallel PCM codes in input time-slots from said parallel series converting means in a first serial order, and to deliver successively the PCM codes in parallel format in output time-slots in a second serial order;; series/parallel converting means connected to receive during the duration of one time-slot from said time division switching means said series of parallel PCM codes in the output time-slots, and to deliver simultaneously and synchronously the PCM codes in serial form in said output time-slots distributed in parallel array to said output series PCM junctions; and a counter for providing to said parallel/series converting means signals for controlling the delivery of the input time-slots, and providing to said time division switching means signals for controlling said memorising according to a first order.

For a better understanding of the present invention, and to show how the same may be carried into effect, reference will now be made to the accompanying drawings in which: Figure 1 represents the diagram of a matrix according to the invention Figure 2 represents a graph symbolising the states of some elements of the matrix; Figure 3 represents the diagram of the element SP represented in Figure 1; Figure 4 represents the diagram of the element PS represented in Figure 1; Figure 5 represents the diagram of the element EA represented in Figure 1.

The circuit shown schematically in Fig. 1, and which represents the internal organisation of a symmetrical matrix, comprises an input circuit SP, an output circuit PS, a speech memory MP, an address memory MA, a time counter CT, an address counter CA, an address circuit EA and a control circuit SA. A connection shown in the form of a single line corresponds to a single wire carrying the signals made up of series bits, whilst a connection shown in the form of a line accompanied by a circle showing the figure n, corresponds to n wires carrying signals made of n bits in parallel, this in accordance with a normal convention. Connections which carry service signals and which are of no importance when an understanding of the invention is concerned, these signals in particular comprising the clock signals designed to operate the registers, have been omitted from this illustration.These various service signals are formed internally in the elements illustrated, or in an element which has not been shown here and which furnishes clock signals whose frequencies and phases are appropriate, from the sole external clock signals which are 112048 (bit rate clock) and H8 (field rate clock).

Eight incoming junctions jeO to je7, each carrying a sequence of PCM frames each made up of 32 time slots ITo to IT31, arrive at the input circuit SP. These frames succeed one another at the rate of 8 kHz, in phase with the clock H8. Each ITX corresponds to an 8-bit coded sample, and the rate of the bits arriving in series on each junction is thus 2.048 MHz, in phase with the clock 112048. This rate corresponds to elementary times of 488 ns.

In the example described, the ITx'S arriving in series on the eight incoming junctions are in phase and the function of the circuit SP, which will be described in more detail hereinafter, is to successively present in parallel on the eight wires of the output connection 101 of SP, the eight IT 's which have arrived together on the eight junctions. Each bit of ITX is allocated to one wire and the IT's leave the circuit SP one after the other with a shift from one to the next of one time element, this corresponding to a first order.

The number of ITx's leaving the circuit SP per unit time is thus, under these circumstances, equal to the number of ITx's arriving there per unit time, and the binary rate is therefore constant.

The connection 101 thus, every 488 ns, supplies to the input of the memory MP an ITX from one of the eight incoming junctions. This ITX is recorded in the memory MP at a position marked by the number jek corresponding to the incoming junction from which it stems, and by its order ITX in the particular frame.This memory is thus organised in the form of 32x8=256 words of 8 bits each, and the address of each of these words is represented by a number of eight-bit binary coded form, the three bits of lower weighting factor representing the jek and the five bits of higher weighting factor representing IT. These addresses being fixed and corresponding to a first given order, are obtained by the read-out of a 256state time counter CT which operates at the rate determined by the clock 112048. MP is supplied with the eight bits representing each state, through the medium of the connection 102.The counter CT is also supplied with the signal from the clock H8 making it possible for it to lock into phase with the development of the frames, for example virtue of an operation of resetting to zero with each ITo from the incoming junctions.

Since it is necessary to record in and read out from said memory, with each time element, the time elements of 488 ns each are divided into 244 ns half-times, this being a straight forward matter since the block signal is a square-wave signal at the frequency 2048 MHz. This clock signal is illustrated in Fig. 2 by 112048. Recording in MP is carried out during the high states of the clock signal and read-out during the low states. The signal MP shown in Fig. 2 symbolises the sequence of cycles of the memory MP and the line CT the sequence of states of the counter CT, between the states 128 and 131.Recording is therefore initiated by the logic combination in the internal circuits of MP, of the states of CT and the high states of HZQ48. this yielding the cycles E,28 to E,3, which are located during the first half-periods of the time elements. The counter CT leads in phase by a half-time, in order to enable correct transmission of the recording address to MP to take place.

With each read-out half-period or halftime in other words, there is read out from MP a word located at a random address, which is given in eight-bit form by the address memory MA, the sequence of these addresses defining a second, given order.

The words thus read out from MP leave the latter one after the other, in parallel, on the eight wires of the connection 103. Thus, the order of succession of the words has been changed between their input to MP through the connection 101 and their output therefrom through the connection 103, so that at this point in the system in effect time switching has been performed.

The circuit PS which will be described later on, makes it possible to present in series and simultaneously on each of the outgoing junctions jsO to 57, eight words which have arrived successively on the connection 103. The distribution thus achieved corresponds to a second, given order. Thus, on each of these eight outgoing junctions is, a PCM field made up of 32 of the total of 256 channels arriving on the set of eight incoming junctions je, is obtained.

It will be seen, therefore, that the switching function which, within the speech memory proper, is purely a time switching function, also becomes a spatial switching function due to the distribution between the eight-ontgoing junctions. It should of course be pointed out that the element PS, and for that matter the element SP, are not spatial switches in the conventional sense since they distribute the words in accordance with given, constant cyclic orders. In fact, it is the time switching of the words within each group of eight words intended for sequential distribution to the eight outgoing junctions, which brings about a spatial switching effect. This is the prime advantage of this matrix which directly allows time switching and space switching without introducing the blocking effect so characteristic of actual spatial switches.It now becomes possible, using this circuit as the sole basic element, to construct large automatic exchanges which have a low, even zero blocking ratio.

It can also be pointed out that this matrix is entirely symmetrical between the input and output, this on the one hand justifying the name given to it on the other hand making for major simplification in the design of automatic exchanges for the series connection of these matrices.

The addresses of the words to be read out from MP are contained in the address memory MA. The latter is memory organised in the form of 256 eight-bit words and is read cyclically in 125 ,ets under the control of the address counter CA; the words thus read out are transmitted through the connection 104 to MP. The counter CA cycles at the rate determined by the clock H2048 and also receives a signal from the clock H8which keeps it in place in just the same way as CT.

The line MA in Fig. 2 symbolises the succession of cycles of the store MA and the line CA the succession of states of the counter CA. Read-out is therefore initiated by the logic combination in the internal circuits of MA of the states of CA and the high states of H2048, this yielding the cycles L,28 to L121 which are located during the first half-periods of the elementary times. CA also leads in phase by a half-period for the same reasons given in relation to CT. The states of CA are thus transmitted in eight-bit form, in parallel, through the connection 105 to MA.

The word read out at the address thus defined represents the address of the word in MP which is to be read. It is transmitted through the connection 104 to MP. The internal circuits of MP decode this addresss and initiate the read-out of the word in MP, which corresponds to this address, this during a second half-period. This, considering Fig. 2, for example the read-out in MA of the words located at the addresses 128 to 131 (L,28 to L,3,) brings about readout in MP of the words 23, 29, 32 and 127 (L23, L29, read-out L32 L127).

Each word which is read-out in MA represents the position of a word for readout in MP, and since this position is defined by an incoming junction jek and a time slot ITX in this junction, we will designate this word in MA by the notation "ITc, jek" where jek corresponds to the three bits of low weighting factor and ITX to the five bits of high weighting factor.This word is readout from MA at the instant at which the word in MP is to be read out, so that its address in MA t represents an outgoing junction js, and a time slot ITV in said junction and we will designate this address by the notation "ITy, js,", with the same distribution of bits.

The memory MA thus contains the information on 256 space time routes between the 256 ITx'S of the junctions je and the 256 ITy'S of the junctions js. It goes without saymg of course, that it is necessary to be able to modify the content of MA as a function of changes to be made to these routes in accordance with whether new connections are to be established or current ones broken.

To do this, on the connection IE there are transmitted a marking signal comprising the word "ITx, jek" of 8 bits length which is to be fed into MA, and 8 bit word "ITy, js," indicating the address at which this work is to be recorded in MA, and several service bits.

The addressing circuit EA which will be described hereinafter, then simultaneously transmits to MA the word "ITx, jok" on the connection 106, the word "ITy, joe," on the connection 107 and a signal E/L on the connection 108. This signal E/L is a single bit which furnishes to MA the command to record the word "ITx, jsk" at the address "ITy, js,", This recording takes place during the first half-period of an elementary time, for example 129 in Fig. 2, since the second half-period is used for normal read-out. This corresponds to the recording En in Fig. 2.

Since, more often than not, it is required to check the result of this recording operation, the thus recorded word is read out during the first half-period of the elementary time following recording, namely 130 in Fig. 2, this giving us the read-out Ln. In the example described, a circuit inside MA, for example a flip-flop, memorises the information carried by the signal E/L in order to perform this read-out function, since this signal only has two states and the low state must not be allowed to trigger permanent read-out. In another embodiment, it would be possible to separately control read-out and recording by using two wires for the connection 108.

The words read out from MA are also transmitted through the connection 104 to the control circuit SA which is also supplied with the signal E/L through the connection 108. The circuit SA is a simple register, likewise equipped with a memory device for E/L and makes it possible to feed out serially on a wire an output piece of information IS which for checking purposes reproduces the word recorded in MA at the address "ITy, ;f" which word should therefore be "ITy, jek .

Fig. 3 provides a fragmentary illustration of an embodiment of the input circuit SP, comprising eight input registers REo to RE7, a decoder DC1, eight AND-gates P0 to P7 and an OR-gate SO.

The incoming junctions jeO to je7 are respectively connected to the registers REo to RE7. The bits arriving serially on these junctions progress through the registers as they arrive, under the control of the clock 112048.

Each of these registers has eight input information stages 0 to 7 located at the right-hand in the figure and corresponding to the eight bits arriving during the course of an ITx. They also comprise additional input stages located at the left-hand in the figure; the number of these stages is equal to the index of the register.

Thus, at the end of eight elementary time periods of an ITx, the eight bits which have arrived on each junction will be memorised in the eight first left-hand stages of the registers RE, although whereas the eight bits of the IT, of the junction je, would all be in the information stages 0 to 7 of REn, only the first 7 bits of the ITX on the junction je, will be memorised in the information stages O to 6 of RE" and so on up to RE7 in which only one bit of the IT, on the junction je7 will be stored in the information stage 0.

The bits which are not at the information stages are in the additional stages.

The information stages are respectively connected to the AND-gates P0 to P7. These gates are represented in a highly symbolic manner as acting upon the assembly of wires of a connection. They receive operating signals from the decoder DC1.

The decoder DC, receives from the counter CT via the connection 109, the three bits of low weighting, these three bits defining a cycle of eight states during eight elementary time intervals. It successively opens the gates P,to P7 through the medium of the connections 300 to 307. Thus,.during the first elementary time of an IT,, the gate P0 allows the eight bits coming from the information stages 0 to 7 of REo, these being the eight bits of the IT,~, of the junction je,,, to pass in parallel.

During the next elementary time, the bits will have progressed by one stage through each RE and the eight bits of the IT,~, of the junction je1, will be in the information stages O to 7 of RE,. The decoder then opens P, which allows these eight bits to pass in parallel.

The cycle continues until, with the seventh elementary time, the decoder opens P7 allowing the eight bits of the IT,~, of junction je7, these being located in the information stages 0 to 7 of RE7, to pass in parallel.

The OR-gate SO, also illustrated in a highly symbolic way here, combines the outputs of the AND-gates P0 to P7 and on the connection 101, during each elementary time, delivers the eight bits of an ITX of one of the junctions jeO to je7. Thus, during the time for which the ITx's of the incoming junctions arrive in the circuit SP, the eight ITx~,'s of these junctions leave successively via the connection 101.

The output circuit PS essentially operates in the reverse fashion to the input circuit SP.

It has therefore been illustrated in a more simplified fashion and limited to two outgoing junctions in Fig. 4, its operation will be described very briefly. The circuit PS comprises, in the embodiment of Fig. 5, a decoder DC2, eight AND-gates Q0 to Q7 and eight output registers RSo to RS7.

The decoder DC2 operates in the same fashion as DC1, on the three low-weighted bits from the address counter CA, which arrive via the connection 110. These three bits code eight states which serve to successively open the eight gates Q0 to Q7 during the successive arrivals, in the course of eight elementary times, of ITy'S on the connection 103.

These ITy'S are then fed in parallel as the gates Q supply them, into the output information stages of the output registers RSo to RS7. These information stages 0 to 7 are in this instance at the ends of the registers, namely at the left-hand side in the figure. The IT;s thus progress through the register stages, leaving serially on the outgoing junctions j50 to js7.

The registers RSn are also equipped with additional output stages, numbering 7-n, located at the right-hand side of the figure.

Thus, a delay which varies in accordance with the register is introduced in the time of output of the IT;s on the junctions is. This delay compensates for the delay introduced by the successive loading of the eight registers so that the IT;s are synchronous in the PCM frames fed out on the junctions is.

It should be pointed out that the words read out from MP and then serially arranged in PS are available at the output of PS synchronously with the words fed into SP, this meaning that the symmetrical time matrix retains the synchronism of the IT's and thus makes it possible to arrange the matrices in series without any matching being needed.

Fig. 5 schematically illustrates an embodiment of the addressing circuit EA, which comprises a main register RA, four AND-gates P8 to P11, a counter CE, a flip flop BT and a delay circuit MN.

The marking signal, which, in this example, is transmitted serially at the rate of 2048 MHz on the connection IE, is here made up of 20 successive bits comprising a starting bit ST, eight bits lo to I7 representing the word "IT,, jek" which is to be recorded in MA, eight bits Ao to A7 representing the address "ITy, bus,", at which this word is to be recorded, a record/read out bit which furnishes the recording or read-out command, and two stop bits SP, and SP2.

This signal is applied through the connection EI to the main register RA through which it passes at the rate determined by the clock H2048. For this purpose, IE is also applied to the input S of the flip-flop BT which is of the "RS" type.

The first bit of the signal, which is the starting bit, this always having a value equivalent to a logic "1", places the flip-flop in such a fashion that at its output Q a "1" appears; this flip-flop will remain in this state until a "1" is applied to its input R so that its state is changed, causing it to produce a "O" at Q. The output Q of BT is applied to the AND-gate Pss which is also supplied with the signal 112048. P8 is therefore opened when the output Q carries a "1", and allows H2048 to pass to RA as well as to the counter CE.

At the end of 20 elementary time periods, the marking signal will therefore have been stored in RA and the 20 stages of the latter will then contain the bits shown in the figure. It should be pointed out that the twentieth stage at the right contains the starting bit ST which is not used in this embodiment; this stage can therefore be omitted and is represented in broken line for this reason.

When it has counted 20 elementary time periods, the counter CE furnishes a bit "1" to the input R of BT; this bit is also applied to the delay circuit MN. It should be pointed out that at this same instant, the second stop bit SP2 is received, this being a "O", as also is Sup1, the result of this arrangement being that there is no ambiguity caused between the inputs R and S of BT. The presence of two stop bits is merely a precaution. The flip-flop BT therefore resets to give Q="O", this resulting in the closing of the gate P8 and disconnecting the signal H2048 from RA. The marking signal is thus fixed in the register RA in the manner indicated in the figure.

The delay circuit MN is then triggered by CE and supplies an opening signal to the gates P8 to P". The delay in this signal is adjusted in such a fashion that during the first half-period of the ensuing elementary time period, the arrival of SP2 occurs so that we are in fact dealing with a phase of recording in MA. These three gates are thus opened and allow the following bits to pass: P8 passes the bits 1o to I7 in parallel on the connection 106; P,O passes the bits Ao to A7 in parallel on the connection 107; P" passes the bit E/L on the connection 108.

The value of the bit E/L is a function, as we have seen earlier, of whether it is required to record or to read out MA. If read-out is required, MA takes nb account of the content of 1o to I7 so that the actual form of this content does not matter.

The time-division matrix which has been described is particularly significant when designed in the form of an integrated circuit. Indeed by counting off the inputs and outputs required for this kind of embodiment, we arrive at a figure of 22, arranged as follows: 8 jeO to je7 8 jso toys7 IS 1 IS 1 H8 1 112048 1 supplies 2 Thus, in a single standard 22-pin housing, it is possible to accommodate a symmetrical time-division matrix, involving no blocking, which makes it possible to achieve 256 simultaneous paths between eight incoming 32-channel PCM junctions and eight outgoing 32-channel PCM junctions.

WHAT WE CLAIM IS: 1. A symmetrical time division matrix for switching input time-slots of a first set of input series PCM junctions to time-slots of a second set of output series PCM junctions, said matrix comprising: parallel/series converting means connected to receive simultaneously and

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (5)

1. **WARNING** start of CLMS field may overlap end of DESC **.

   output of the IT;s on the junctions is. This delay compensates for the delay introduced by the successive loading of the eight registers so that the IT;s are synchronous in the PCM frames fed out on the junctions is.

   It should be pointed out that the words read out from MP and then serially arranged in PS are available at the output of PS synchronously with the words fed into SP, this meaning that the symmetrical time matrix retains the synchronism of the IT's and thus makes it possible to arrange the matrices in series without any matching being needed.

   Fig. 5 schematically illustrates an embodiment of the addressing circuit EA, which comprises a main register RA, four AND-gates P8 to P11, a counter CE, a flip flop BT and a delay circuit MN.

   The marking signal, which, in this example, is transmitted serially at the rate of

   2048 MHz on the connection IE, is here made up of 20 successive bits comprising a starting bit ST, eight bits lo to I7 representing the word "IT,, jek" which is to be recorded in MA, eight bits Ao to A7 representing the address "ITy, bus,", at which this word is to be recorded, a record/read out bit which furnishes the recording or read-out command, and two stop bits SP, and SP2.

   This signal is applied through the connection EI to the main register RA through which it passes at the rate determined by the clock H2048. For this purpose, IE is also applied to the input S of the flip-flop BT which is of the "RS" type.

   The first bit of the signal, which is the starting bit, this always having a value equivalent to a logic "1", places the flip-flop in such a fashion that at its output Q a "1" appears; this flip-flop will remain in this state until a "1" is applied to its input R so that its state is changed, causing it to produce a "O" at Q. The output Q of BT is applied to the AND-gate Pss which is also supplied with the signal 112048. P8 is therefore opened when the output Q carries a "1", and allows H2048 to pass to RA as well as to the counter CE.

   At the end of 20 elementary time periods, the marking signal will therefore have been stored in RA and the 20 stages of the latter will then contain the bits shown in the figure. It should be pointed out that the twentieth stage at the right contains the starting bit ST which is not used in this embodiment; this stage can therefore be omitted and is represented in broken line for this reason.

   When it has counted 20 elementary time periods, the counter CE furnishes a bit "1" to the input R of BT; this bit is also applied to the delay circuit MN. It should be pointed out that at this same instant, the second stop bit SP2 is received, this being a "O", as also is Sup1, the result of this arrangement being that there is no ambiguity caused between the inputs R and S of BT. The presence of two stop bits is merely a precaution. The flip-flop BT therefore resets to give Q="O", this resulting in the closing of the gate P8 and disconnecting the signal H2048 from RA. The marking signal is thus fixed in the register RA in the manner indicated in the figure.

   The delay circuit MN is then triggered by CE and supplies an opening signal to the gates P8 to P". The delay in this signal is adjusted in such a fashion that during the first half-period of the ensuing elementary time period, the arrival of SP2 occurs so that we are in fact dealing with a phase of recording in MA. These three gates are thus opened and allow the following bits to pass: P8 passes the bits 1o to I7 in parallel on the connection 106; P,O passes the bits Ao to A7 in parallel on the connection 107; P" passes the bit E/L on the connection 108.

   The value of the bit E/L is a function, as we have seen earlier, of whether it is required to record or to read out MA. If read-out is required, MA takes nb account of the content of 1o to I7 so that the actual form of this content does not matter.

   The time-division matrix which has been described is particularly significant when designed in the form of an integrated circuit. Indeed by counting off the inputs and outputs required for this kind of embodiment, we arrive at a figure of 22, arranged as follows: 8 jeO to je7 8 jso toys7 IS 1 IS 1 H8 1

   112048 1 supplies 2 Thus, in a single standard 22-pin housing, it is possible to accommodate a symmetrical time-division matrix, involving no blocking, which makes it possible to achieve 256 simultaneous paths between eight incoming 32-channel PCM junctions and eight outgoing 32-channel PCM junctions.

   WHAT WE CLAIM IS: 1. A symmetrical time division matrix for switching input time-slots of a first set of input series PCM junctions to time-slots of a second set of output series PCM junctions, said matrix comprising: parallel/series converting means connected to receive simultaneously and

   synchronously in serial form said input timeslots from each one of said input parallel array of series PCM junctions and to deliver in series all the PCM codes of said input time-slots, during the duration of one timeslot, in parallel format; time-division switching means connected to receive said series of parallel PCM codes in input time-slots from said parallel-series converting means in a first serial order, and to deliver successively the PCM codes in parallel format in output time-slots in a second serial order; series/parallel converting means connected to receive during the duration of one time-slot from said time division switching means said series of parallel PCM codes in the output time-slots, and to deliver simultaneously and synchronously the PCM codes in serial form in said output time-slots distributed in parallel array to said output series PCM junctions; and a counter for providing to said paralleVseries converting means signals for controlling the delivery of the input time slots, and providing to said time division switching means signals for controlling said memorising according to a first order.
2. 2. A matrix as claimed in Claim 1, further comprising a counter for providing to said time divisions switching means signals for controlling the delivery according to a second order and providing to said series/parallel converting means signals for controlling the delivery of the output timeslots.
3. 3. A matrix as claimed in Claim 2, further comprising means for modifying said second order under the control of an external signal between the delivenn of two successive of said output time-slots.
4. 4. A matrix as claimed in Claim 1, wherein said first set comprises 8 input junctions, said second set comprises 8 output junctions, said input and output junctions comprising 32 time-slots coded over 8 bits.
5. 5. A symmetrical time division matrix substantially as hereinbefore described with reference to Figures 1 to 6 of the accompanying drawings.