SU1328931A1 - Device for phasing time interval with clock pulses - Google Patents

Abstract

The invention can be used in devices for converting time intervals to digital code, in particular, in amplitude and time analyzers, which use the principle of time conversion by filling it with high frequency clock pulses. The invention makes it possible to eliminate distortions of the first and the last of the phased pulses during the period of their following, commensurate with the duration of transients in the device. The device contains a shaper 1 shifted relative to each other in time pulse sequences, N D-flip-flops 2, N elements AND 3, element OR 4, output element AND 5, delay element 6, bus 7, source of pulses of the time interval, input 8 clock pulses, input 9 initial set-up, output 10. 8. device, the D-flip-flops are polled at the end of the transient processes through the time from the moment of operation I, equal to T (I-1), where T is the I period of clock pulses. 2 Il. (L with to 00 with with

Description

The invention relates to a pulse technique and can be applied in devices for converting time intervals into a digital code, in particular, in amplitude and time analyzers, which use the principle of time interval conversion by filling it with high frequency clock pulses.

The purpose of the invention is the elimination of distortions of the first and the last of the phase pulses with a period of their following, commensurate with the duration of transients in the device.

The goal is achieved by the fact that the D-flip-flops are polled after the transients are completed on them after the time from the moment of their triggering equal to T (N-l), where T is the period of clock pulses,

Fig. 1 shows the electrical circuit of the device; figure 2 - the timing diagram of the operation of the device for N 4.

The device contains a shaper 1 shifted one relative to the other in time pulse sequences, N B trigger 2, N elements AND 3, - element OR 4, output element AND 5, delay element 6, bus 7 of the source of time interval pulses, input 8 clock pulses, input 9 initial setup, output 0.

The inputs of the element OR 4 are connected to the outputs of the elements FROM, the input 9 of the initial installation of the device is connected to one input of the imager, the input 8 clock pulses are connected to another input of the imager 1 and through the delay element 6 to one of the inputs of the output element I 5, with the other the input of which is connected to the element OR 4. The information inputs of the D-flip-flops 2 are combined and connected to the bus 7 of the source of pulses of the time interval.

. The first input of each of the elements I. 3 is connected to the C-input cm of the corresponding D-trigger 2 to the corresponding output of the driver 1. The outputs of the D-flip-flops 2 are connected to the second inputs of the corresponding elements K, and the output of the D-flip-flop 2-1 is connected to the second the input element and

3- (K-1), and the output of the D-flip-flop 2-1 - to the second input element And 3-N.

The device works as follows.

A signal is provided to input 8 of the initial setup, which provides installation of the logical 1 at the first output, and O at the remaining outputs.

As such a former

for example, an N-bit ring shear register or an N-bit allocator arranged on a binary counter and a decoder can be used.

The former 1 generates, at its trailing edge, the clock pulses fed to the input 8, at its N. outputs, shifted one relative to the other for a period T, the pulse sequences in which the pulses are also equal to T.

As long as there is no signal on the bus 7 of the source of the time interval pulses, the D-flip-flops 2 are in the state O, which prohibits the passage of pulse sequences through the elements AND 3.

When a time interval arises at the information inputs of Dtriggers 2, they are sequentially set to state 1 (Fig. 2, charts 2-1 ... 2-4), most allowed passing through the elements And 3 pulse sequences. In this case, since the element I 3, corresponding to the K-th triggered D-flip-flop, is impulsive

Since the sequence with (K-l) -ro of the output of driver 1, and the total of outputs N, then (K-1) the pulse sequence will appear at the output of the corresponding element And 3

time t (N-l) T. If this time t is longer than the transition time t, arising in the D flip-flop at certain time ratios of the pulse fronts at the information and synchronization inputs (for example, when the fronts of the signals at the D and C inputs coincide) i, the output of the And 3 element begins pass the pulse sequence without distorting the first and last pulses in it.

The transient time t in the general case may exceed the period of the following clock pulses.

. one

As a result, the pulse sequences produced by the elements FROM (FIG. 2, diagrams 3-1 ... 3-4), combined on the element OR 4, form at its output a time interval (FIG. 2, diagram 4), front and the back fronts are phased with clock pulses.

- Phasing of the trailing edge is carried out similarly. At the end of the time interval, sequential installation occurs in O D-triggers 2 and, consequently, the termination of the pulse sequences at the outputs of the And 3 elements during time t. A transient process, possibly occurring on one of the D-triggers, will not cause (as in the case of the formation of the beginning of the time interval) distortion at the output of the corresponding IZ element.

At the output element I 5, the generation of a pulsed one is possible. Moreover, the possible dips in the phased time interval caused by the inconsistency of the pulses c: in the inputs (Element OR 4, are not important for its correct output, since the I 3 incoming to the second input element clock pulses do not match them.

A delay element 6 is used to compensate for the delay circuit elements.

Thus, at the output of the device, a series is formed phased with a clock frequency, the first and last pulses of which are undistorted at any time ratios of the pulses on the bus 7 of the source of pulses of the time interval and at the input 8 of clock pulses.

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A time interval phasing device with clock pulses containing a driver of pulse sequences that are shifted relative to each other, the first input of which is connected to the source of clock pulses N 3JjeMeHTOB AND, the first inputs of which are connected to the corresponding outputs of the driver of the pulse sequences that are shifted one relative to the other in time, and the outputs are connected to the inputs of the OR element, characterized in that in order to eliminate distortion of the first and last of the phased pulses in the period of their following, commensurate with the duration of transients in the device, N D-flip-flops, a delay element and an output element AND whose first input is connected to the output of the OR element are entered into it, and the second input through the delay element is connected to the first input of the shifter shifted one relative to the other in time of the pulse sequences, the second input of which is connected to the input of the initial installation of the device, while the information inputs of D-flip-flops are connected to the time source pulse bus and the terminal, the C-input of each of the D-flip-flops is connected to the first input of the corresponding element And, the outputs of the D-trigger in connected to the second, the inputs of the corresponding elements And, and the output of each i-ro D-flip-flop, where i 2,3, ..., N, is connected to the second input (i -) - ro of the element And, and the output of the first D-flip-flop is connected to the second input of the N-ro element And,

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Editor A. Shishkin

Compiled by A. Ordered Techred I. Were Corrector; L. Patay

Order 3497/57 Edition 901 Subscription

VNIIPI USSR State Committee

for inventions and discoveries.

113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, st. Project, 4

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Claims (3)

Claim A phasing device for a time interval with clock pulses, comprising a shaper of pulse sequences shifted relative to each other in time, the first input of which is connected to a clock source, N elements And, to the first inputs of which are connected the corresponding outputs of the shaper of pulse sequences shifted relative to each other, and the outputs are connected to the inputs of the OR element, characterized in that in order to eliminate distortion of the first and last of the phased pulse s during the period of their succession, commensurate with the duration of the transient processes in the device, N D-flip-flops, a delay element and an output element And are introduced into it, the first input of which is connected to the output of the OR element, and the second input through the delay element is connected to the first input of the shifted shifter one relative to the other in time pulse sequences, the second input of which is connected to the input of the initial installation of the device, while the information inputs of the D-flip-flops are connected to the bus of the pulse source of the time inter tore, the C-input of each of the D-triggers is connected to the first input of the corresponding And element, the outputs of the D-triggers are connected to the second inputs of the corresponding And elements, and the output of each i-ro D-trigger, where i = 2,3 ,. .., N, is connected to the second input (il) -ro of the element And, and the output of the first D-trigger is connected to the second input of the Nth element I. input / t · 1,; UTU 1-2 1-3 7-4 Entrance 7 2-1 2-2 2-3 2-9 3-9 3-1 3-2 3-3 Output 10 UTL. Υ // ΛУ / А__к / Ч. ,,,, ______ UTL UTL u, TTTA ________ UTL ΥΤΤλ __ UTL .........._ UTL UTL 7 ///////////// / L__ - UT7T7 / 77 /// Lk ............ , ........ FW / ^ A ........ __W //////////////////// A - ___-________________________ £ 53 ___ - _________ UTL .__ ______ * - *> UTL UTL - ____ J53 __— 77T \ ___ ........... U7tUTL2t // xU / LT / A U№L7? TUU \ P UL Fig!