JPH11218564A - Timing signal generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a timing signal generating circuit capable of generating accurate timing signal. SOLUTION: A coarse timing signal 7 varying its level in accordance with the pulse of an input clock signal 6 is generated and when multiple phase clock signals 8 with different phases are generated in a timing synchronizing with the input clock signal 6, a pulse is generated in accordance with the phase of the clock signal of one of the multiple phase clock signal 8 selected following the fine timing data 5 at the time coarse timing signal 7 is '1'. As it is output as a fine timing signal 9, the fine timing signal 9 can be produced regardless of the constitution that delays the timing signal varying the pulse intervals. By this, the degradation of the timing accuracy due to a pattern effect and so accurate timing signal can be generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit suitable for use in an apparatus such as an IC tester, and more particularly to a timing signal generating circuit for changing a pulse interval of a generated timing signal for each pulse.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a configuration of a conventional timing signal generating circuit. In this figure, the coarse timing signal generating means 1 supplies a pulse signal whose pulse interval changes at an integral multiple of the input clock signal 6 to the variable delay circuit 4 as a coarse timing signal 7. The variable delay circuit 4 delays the coarse timing signal 7 to generate a fine timing signal 9. The delay time of the variable delay circuit 4 is
It changes with a time resolution shorter than the cycle of the input clock signal 6 according to the fine timing data 5, and the delay time resolution is the time resolution of the pulse interval of the fine timing signal 9.

[0003]

In the conventional timing signal generating circuit described above, when the coarse timing signal 7 whose pulse interval changes is delayed by the variable delay circuit 4, a cause such as an increase in jitter due to a pattern effect is caused. Therefore, there is a disadvantage that it is difficult to obtain the timing accuracy of the output fine timing signal 9. The present invention has been made in view of such circumstances, and has as its object to provide a timing signal generation circuit that can generate a timing signal with high accuracy.

[0004]

In order to achieve the above object, according to the first aspect of the present invention, at least a coarse timing signal (7) that changes in level every time a pulse is input to the input clock signal (6). Generated coarse timing signal generation means
(1), a multi-phase clock signal generating means (2) for generating multi-phase clock signals (8) having different phases at timing synchronized with the input clock signal (6), and the coarse timing signal (7). ) Is "1", fine timing data
A pulse is generated according to the phase of the clock signal of any one of the multi-phase clock signals (8) selected according to (5),
A fine timing signal generating means (3) for outputting as a fine timing signal (9).

According to the second aspect of the present invention, the fine timing signal generating means (3) comprises:
A plurality of AND gates (32) having at least the coarse timing signal (7) as one input; and the plurality of AND gates
(32) as the respective D inputs, individual D flip-flops (33) using the respective phases of the multi-phase clock signal (8) as the respective clock inputs, and the plurality of D flip-flops (33 ) As an input and the fine timing signal
An OR gate (34) that outputs (9) and the fine timing data (5) are input, and the other input of the plurality of AND gates (32) changes according to the value of the fine timing data (5). And a decoding circuit (31) for sending independent output signals of which only one becomes "1".

According to the third aspect of the present invention, the fine timing signal generating means is provided.
(3) a plurality of AND gates (32) having at least the coarse timing signal (7) as one input, and the multi-phase clock signal (8) having respective phases as respective inputs, and the plurality of AND gates (32). 32) each output as an enable input,
When a pulse is sent to the input when the signal to the enable input is "1", a separate one-shot multivibrator (35) that outputs a pulse having a specific pulse width to the output, and the plurality of one-shot multivibrators (35) An output of the fine timing signal (9) as an input, an OR gate (34) for outputting the fine timing signal (9), and the fine timing data (5) as an input, and the other input of the plurality of AND gates (32) A decoding circuit (31) for transmitting an independent output signal which changes in accordance with the value of the fine timing data (5) and in which only one becomes "1" is provided.

In the present invention, a coarse timing signal generating means is provided.
(1) generates a coarse timing signal (7) whose level changes according to the pulse of the input clock signal (6), and the multi-phase clock signal generation means (2) generates the coarse timing signal at a timing synchronized with the input clock signal (6). , Polyphase clock signals with different phases
When (8) is generated, the fine timing signal generating means (3) selects one of the multi-phase clock signals (8) selected according to the fine timing data (5) when the coarse timing signal (7) is "1". A pulse is generated in accordance with the phase of the clock signal of the phase (1), and is output as the fine timing signal (9). In other words, the fine timing signal (9) can be generated without depending on the configuration in which the timing signal whose pulse interval changes is delayed by the delay circuit, so that deterioration of the timing accuracy due to the pattern effect can be avoided as in the related art. , An accurate timing signal can be generated.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a timing signal generating circuit according to an embodiment of the present invention will be described as an example with reference to the drawings. (1) Schematic Configuration FIG. 1 is a block diagram showing a schematic configuration of an embodiment according to the present invention. In this figure, an input clock signal 6 is supplied to a coarse timing signal generating means 1 and a multi-phase clock signal generating means 2, respectively. The fine timing data 5 is supplied to the fine timing signal generating means 3. The coarse timing signal generating means 1 generates a coarse timing signal 7 whose level changes every time a pulse is supplied to the input clock signal 6 and supplies it to the fine timing signal generating means 3.

The multi-phase clock signal generating means 2 generates a multi-phase clock signal 8 having a different phase at a timing synchronized with the input clock signal 6 and supplies it to the fine timing signal generating means 3. The fine timing signal generating means 3
When the coarse timing signal 7 is “1”, a pulse corresponding to the phase of the clock signal of any one of the multi-phase clock signals 8 selected according to the fine timing data 5 is generated. Output.

(2) Specific Configuration Next, a specific configuration of the fine timing signal generating means 3 will be described with reference to FIG. In FIG. 2, 31 is a decode circuit, and 32-1, 32-2,..., 32-n are AND gates. 33-1, 33-2, ...
33-n is a D flip-flop, and 34 is an OR gate. The coarse timing signal 7 is supplied to the AND gate 32-1,
A plurality of D flip-flops 33 each having one of the multiphase clock signals 8-1, 8-2, 8-n as a clock input through one input terminal of 32-2,..., 32-n.
-1, 33-2,..., 33-n. The decode circuit 31 changes according to the value of the fine timing data 5, and only one becomes “1”.
The independent output signals are supplied to the fine timing data 5 to the other input terminals of the AND gates 32-1, 32-2,..., 32-n.

Next, the operation of the embodiment when the fine timing signal generating means 3 having the above configuration is used will be described with reference to FIG. 3A shows a waveform example of the input clock signal 6, FIG. 3A shows a waveform example of the coarse timing signal 7, and FIG. 3C shows a waveform example of the fine timing data 5, respectively. (D) -1 and (d)
−2, (d) -n are the multi-phase clock signals 8-1,
The waveforms of each phase of 8-2 and 8-n are shown in FIG.
(E) -2, (E) -n are AND gates 32-
The waveforms of the output signals 1, 32-2 and 32-n are shown in FIG.

First, as shown in FIG. 1A, a pulse 61 is input to the input clock signal 6, and the coarse timing signal 7 changes from "0" to "1" in FIG. -1, 32-2,..., 32-n, the AND gates 32-1, 32-2,.
..., the other input terminal of 32-n is supplied with a signal selected according to the fine timing data 5 and only one of which is "1" and the others are "0". FIG. 3 shows a case where only the input of the AND gate 32-1 is "1" in this state, and the output of the AND gate 32-1 changes to "1" in FIG. When a pulse is input to the D input of the D flip-flop 33-1 and a pulse is input to the multiphase clock signal 8-1 which is the clock input of the D flip-flop 33-1 in FIG. 3
The output of 3-1 becomes "1" and is sent to the OR gate 34.
The fine timing signal 9 becomes "1" in FIG.

In FIG. 1A, a pulse 62 is input to the input clock signal 6, and in FIG.
0 "and AND gates 32-1, 32-2,...
When it is sent to 32-n, the output of the AND gate 32-1 changes to "0" at (e) -1 in the figure and is sent to the D input of the D flip-flop 33-1. When a pulse enters the multiphase clock signal 8-1 at -1, the output of the D flip-flop 33-1 changes to "0" and is sent to the OR gate 34, and the fine timing signal 9 changes to "0" in FIG. ".

Next, in FIG.
A pulse 63 is input to the coarse timing signal 7 shown in FIG.
Changes from "0" to "1" and the AND gates 32-1 and 32-1,
32-2,..., 32-n. At this time, when the fine timing data 5 changes and only the signal to the AND gate 32-2 of the output signal of the decode circuit 31 becomes "1", the output of the AND gate 32-2 is shown in FIG. Changes to "1" and is sent to the D input of the D flip-flop 33-2, and a pulse is applied to the multiphase clock signal 8-2 which is the clock input of the D flip-flop 33-2 in FIG. When entering, D flip-flop 3
The output of 3-2 becomes "1" and is sent to the OR gate 34.
The fine timing signal 9 becomes "1" in FIG.

In FIG. 1A, a pulse 64 is applied to the input clock signal 6, and in FIG.
0 "and AND gates 32-1, 32-2,...
When it is sent to 32-n, the output of the AND gate 32-2 changes to "0" at (e) -2 in the figure and is sent to the D input of the D flip-flop 33-2. When a pulse enters the multiphase clock signal 8-2 at -2, the output of the D flip-flop 33-2 changes to "0" and is sent to the OR gate 34, and the fine timing signal 9 changes to "0" in FIG. ". As described above, according to the present embodiment, since the timing signal whose pulse interval changes is not delayed by the delay circuit, the deterioration of the timing accuracy due to the pattern effect can be avoided. This makes it possible to generate a timing signal with higher accuracy than that of the first embodiment.

(3) Modified Example Next, a modified example of the fine timing signal generating means 3 will be described with reference to FIG. .., 32-n are AND gates, 35-1, 35-2,..., 35-n are one-shot multivibrators, and 34 is an OR gate. It is. The coarse timing signal 7 is supplied to the AND gates 32-1 and 32-
, 32-n via one input terminal of each of the one-shot multivibrators 35-, each phase of which is a clock input of each of the multiphase clock signals 8-1, 8-2, 8-n. , 35-2,..., 35-n.

This one-shot multivibrator 35
-1, 35-2,..., 35-n have an enable input of "
When a pulse is supplied to the input when the value is 1 ", a pulse having a specific pulse width is output to the output.
Inputs the fine timing data 5 and inputs the AND gate 3
2-1, 32-2,..., 32-n are supplied with independent output signals which change according to the value of the fine timing data 5 and only one becomes “1”. I do.

Next, with reference to FIG. 5, the operation of the modification of the above configuration will be described. 5A shows the waveform of the input clock signal 6, FIG. 5A shows the waveform of the coarse timing signal 7, and FIG. 5C shows the waveform of the fine timing data 5. D) -1, (d) -2 and (d) -n are the multi-phase clock signals 8-1, 8-
The waveforms of each phase of 2, 8-n are shown in FIG.
2 and (e) -n are AND gates 32-1,
The waveforms of the output signals of 32-2 and 32-n are shown in FIG.

First, as shown in FIG. 1A, a pulse 65 is applied to the input clock signal 6, and the coarse timing signal 7 changes from "0" to "1" in FIG. , 32-2,..., 32-n, and at this time, the AND gates 32-1, 32-2,.
... the other input terminal of 32-n is fine timing data 5
, Only one is "1" and the others are "0". FIG. 5 shows an AND gate 32-1.
In FIG. 3E, the output of the AND gate 32-1 changes to "1", and the input of the one-shot multivibrator 35-1 is changed to "1". When a pulse is input to the multi-phase clock signal 8-1 which is the input of the one-shot multivibrator 35-1, the one-shot multivibrator 35-1 generates a pulse having a specific pulse width. It is generated and output to the fine timing signal 9 via the OR gate 34 as shown in FIG.

Next, in FIG. 3A, a pulse 66 is input to the input clock signal 6, and the coarse timing signal 7 changes to "0" in FIG.
,... 32-n, the output of the AND gate 32-1 changes to "0" in FIG. Further, a pulse 67 is input to the input clock signal 6 in FIG. 9A, and the coarse timing signal 7 is changed from “0” to “0” in FIG.
1 "and AND gates 32-1, 32-2,...
It is supplied to one input of 32-n.

FIG. 5 shows that the fine timing data 5 changes at this time, and the AND gate 3 of the output signals of the decode circuit 31 is output.
FIG. 2E shows that the output of the AND gate 32-2 changes to "1" and only the signal to the 2-2 changes to "1".
When the pulse is sent to the enable input of 5-2 and the multiphase clock signal 8-2 which is the input of the one-shot multivibrator 35-2 in FIG. A pulse having a specific pulse width is generated and output to the fine timing signal 9 via the OR gate 34 as shown in FIG.

In FIG. 2A, a pulse 68 is input to the input clock signal 6, and the coarse timing signal 7 changes to "0" in FIG.
2-2,..., 32-n
Changes the output of the AND gate 32-1 to "0". As described above, even in the timing signal generation circuit according to the modified example, since the configuration is not adopted in which the timing signal whose pulse interval changes is delayed by the delay circuit, the deterioration of the timing accuracy due to the pattern effect can be avoided, and the accuracy can be improved. A timing signal may be generated.

[0023]

According to the present invention, the fine timing signal (9) can be generated without depending on the configuration in which the timing signal whose pulse interval changes is delayed by the delay circuit. Deterioration of timing accuracy can be avoided, and as a result, an accurate timing signal can be generated.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a basic configuration of one embodiment of a timing signal generating circuit according to the present invention;

FIG. 2 is a block circuit diagram showing a specific configuration of a fine timing signal generating means.

FIG. 3 is a time chart showing an operation.

FIG. 4 is a block circuit diagram showing another specific configuration of the fine timing signal generating means.

5 is a time chart showing the operation of the timing signal generation circuit according to the present invention when the fine timing signal generation means having the configuration of FIG. 4 is used.

FIG. 6 is a configuration diagram of a conventional timing signal generation circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Coarse timing signal generation means 2 Polyphase clock signal generation means 3 Fine timing signal generation means 31 Decoding circuits 32-1, 32-2,... 32-n AND gates 33-1, 33-2,. −n D flip-flop 34 OR gate 35-1, 35-2,... 35-n one-shot multivibrator

Claims (3)

[Claims] A coarse timing signal (7) whose level changes at least every time a pulse is input to an input clock signal (6).
And a multi-phase clock signal generating means (2) for generating multi-phase clock signals (8) having different phases at timings synchronized with the input clock signal (6). When the coarse timing signal (7) is "1", a pulse is generated according to the phase of the clock signal of any one of the multi-phase clock signals (8) selected according to the fine timing data (5). And a fine timing signal generating means (3) for outputting as a fine timing signal (9). 2. The fine timing signal generating means (3)
A plurality of AND gates (32) having at least the coarse timing signal (7) as one input; and each output of the plurality of AND gates (32) as a respective D input; Separate D flip-flops with each phase as its own clock input (33)
And the outputs of the plurality of D flip-flops (33) as inputs,
OR gate (34) for outputting the fine timing signal (9)
And the fine timing data (5) as an input, and the fine timing data to the other input of the plurality of AND gates (32).
2. A timing signal generating circuit according to claim 1, further comprising a decoding circuit (31) for sending an independent output signal which changes according to the value of (5) and only one of which is "1". . 3. The fine timing signal generating means (3)
A plurality of AND gates (32) having at least the coarse timing signal (7) as one input, and each phase of the multi-phase clock signal (8) as a respective input;
Each output of the plurality of AND gates (32) is used as a respective enable input, and when a pulse is sent to the input when the signal to the enable input is "1", a pulse having a specific pulse width is output to the output. A one-shot multivibrator (35), an OR gate (34) that receives the outputs of the plurality of one-shot multivibrators (35) as input, and outputs the fine timing signal (9), and the fine timing data (5). A decode which sends an independent output signal which changes as an input to the other input of the plurality of AND gates (32) according to the value of the fine timing data (5) and only one becomes "1" The timing signal generating circuit according to claim 1, further comprising a circuit (31).