SU1672501A1 - Television signals display unit - Google Patents

Abstract

The invention relates to telemechanics and is used to output television signals for display on a control panel. The device provides the possibility of retransmitting the television signals entered into it upon the request of an external device, including the input of information into the computer. The aim of the invention is to increase the information content of the device. The device contains a setting device 1, registers 2-5, amplifiers 6, counters 7-9, triggers 10-16, elements OR 17-20, pulse formers 21, 22, demultiplexer 23, elements EXCLUSIVE OR 24, 25, delay elements 26, 27 , elements 28-30, switches 31, 32, inverters 33, 34, generator 35. 1 ill.

Description

The invention relates to telemechanics and is intended to display television signals on a control panel using lamps, LEDs and other indicators.

The purpose of the invention is raising awareness.

The drawing shows a block diagram of the device.

The device for reproducing television signals contains setpoint 1, informational 1-1 and 1-2 clock signals, input commands 1-3, output commands 1-4, handshake commands 1-5 and control commands i-1-6, input register 2, buffer registers 3, 4, output register 5, consisting of sections, amplifiers 6, connected to the bus Output devices and associated with indicators of the control panel (not shown), counters 7-9, the number of bits in the counter is 7, its outputs labeled 7-1. 7- (l-3), 7- (p-2), 7- (p-1), 7-p, with the 7-p output of the most significant bit of the counter, triggers 10-16, elements OR 17-20, drivers 21, 22 pulses, a demultiplexer 23 that converts the binary code from the outputs 7- (p-3), 7- (p-2) and 7- (p-1) of counter 7 to eight positional signals 23-1 .23-8, elements EXCLUSIVE OR 24, 25, delay elements 26, 27, elements AND 28-30 switches 31, 32, inverters 33, 34, generator 35, forming on the first and second outputs periodic sequences of pulses with different frequency of their following, restrictive element 36.

The operation of the device is carried out in stages. At the first stage, the reception of information signals coming from setpoint 1 is made. Signals 1-1 are accompanied by clocks, signals 1-2 and an input command 1-3. The serial information code is entered into register 2. Since during operation of the device at other stages, register 2 is used as

ABOUT

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source of input signals operating in other modes for extracting control signals for each stage switch 31 is used. Signals are sent to the switch via two inputs of 6t generator 35 and 1-2. The signal passed to the output of switch 31 is determined by one of two control signals 1 3 or from the element OR 17 In the mode of inputting the information signals 1 1 into the register 2, the switch 31 by the signal 1 3 is switched to the skip of signals 1 2

The information is entered into register 2 at the addresses specified by counter 7 and fed to the first (address) input group. The number of code combinations of counter 7 and the number of address buses of register 2 must be chosen depending on the number of television signals and the method used to control the reliability of received information B. In the considered variant of the device, to increase the reliability, it uses with the method of retransmission with the inverse data of the main premise.

When the number of television signals in the information code is l / 2, the number of information bits, taking into account the repetition of pz n. Therefore, the number of code combinations c1 i tik 7 is 2p, and the number of bits - n, the first group of inputs of the register 2 signals from outputs 7-1 7 (p 1) of counter 7 The state of the counter is increased by one for each period of the clock of the BLIX signals received on the bus 1 2 and accompanying the serial information code 1 1 for separating in time the control signals of the counter 7 and the register 2 enters counter 9 and item OR 19 from gene The clock 35 at the first output is fed to the counter 9 by a clock signal with a relatively high frequency exceeding the frequency of the signals 1-2 corresponding to the frequency of entering the information code. During the pause of each signal 1-2 passing through the switch 31, the signal for blocking the counter 9 is removed. signals from generator 35 When signal 1 is formed at one of the outputs of counter 9, a signal 1 is formed at the output of the element OR 19 which passes to the input of register control 2. The signal from the second output of counter 9 is formed with respect to the signal from the element OR 19c delay for one period of the signal of the generator 35 and fed to the second input (blocking) of the counter 9 Thus, in each period of the signals 1–2, the control signal for writing to the register 2, and then signal transfer counter 7 to a new position, and

Known signals are shifted by the front of the signals 1 1 for about half the period of the signals 1 1 le echi are formed in the zone of the most reliable at-ml

hence o and nt of the space code-j

After the completion of J, not even a ps. / 21 h juloz P register i ifn1, 1 n i x 7 1 7 (n 1) beginning jr i n mrr n j and feast on i r those / Ґ pi and i r st rl which

0 n preceding m // - period - information i 1 records dt. | element formed and And -10 g to t- at its inputs bppi n T, IH r i i I 1 and ot invert ora 1ge r-u i n my ne t p

5 d e N i p / 2 (i g i l v j i s i i i v j c de 7 (n 11 ianop4icf r-hn, m 1 ik cum invertor ° lg to chu obs

1 НЈ -.W AND Н J J t I I p

is translated to, PM scam i i i start 0 from the zero address AND,. pb.) itp / 2do (. periods 1 2 sings 1 h ps from go

second information chonp ° e

the inverse of ti is t oi if it is one that is i. i,

4 Oh to n / 2 periods (nh, ,, n

THE EXCLUSIVE OF IPI - tse (About f one-part of g "mercury in

Is made synchro H 1 I HE f | p ij, O

data fidelity, i- in 0 Thanks to the fact that

USED AND IN GR i needles aphids 3 G

I read it 4 i and, l reliably r. gnzha source and kan 11 t ijq i i

5 part apar 1 pi i v ((r r j

Signal 1 IM uut i u / i P iv. l I GO OR 25 of1 Muechch with net j signals from 1 i c4iHr maerio and- nm-gtr 2 In decay of sig i TIT 1 o ln ,,, p (, НР

0 is set to 1 oPpi IT vr; r, and the signal is on; t rpnrr i. iO uo ryu in this case, the us 1 | argon11nats to the state determined by the signal wi its first input. Thus, the triiso 10 chtn nevlivt

5 in 1 when fixing the mismatch of the 25 CHI element compared to the filter, and the trigger after this is determined to -pts in 1-stage regardless of re - / / comparison signal of other signals before the signal

O start signal 1 on and m-. One trigger, the first input of the trigger O (D), is supplied with the controlling determining condition Tfiiirrt p Koiopoi on r1 in the front of the signal by the motor (C IAC

5 De Signal by tri, f y. (By the Rhotsu trigger the translate in with the oscillation 0 The absence in the drawing is p. O, and it means that it is constantly connected with 1 te of the signal to the front of, from the trigger i, p ig m P i

Taking into account the on-line and other triple pa 10 at the time of the formation of signal 1 at the output of the 7th idea, the reception of information F is correct and the cable 10 remains in state 0 and the previously received information is enabled. the second input is transferred to the state TI pnirep 11 Since at the moment of controlling the trigger 11 by a signal from the inverter 34, the third input returns to O the trigger 10. To eliminate ambiguity, the trigger control signal 1 1 between the output / trigger of the trigger 10 and the trigger input 1 1 sets the element 26 The value of enter com th delay must compensate the possible time shifts fronts si1 catch reset flip-flop 10 to 0 and set to 1 trsh ger 11

Trigger 11 is held in the R state of the G before the arrival of the 1A output command. Simultaneously with the reset to 0 (signal on the third input) of the trigger 11 is transferred to 1 trigger 12 Element and airborne and 27, similar to the 2b obec signal, the unambiguous control signal supplied to the first input trigger 12 The interval during which trigger 12 is held in state 1 must correspond to the reading time of the n / 2 signals from register 2 and rewriting to the source 3 Since the reading process, the rewriting is not associated with the time nepe / ui low speed BUT | 1 channel BLOOD speed of this process is high (taking into account the capabilities of the flammable base), and the time is short that there is practically no delay in receiving information packages, even if they follow another, the speed of the process of reading and rewriting is set the frequency at the second output of the generator 35 which through the switch 31 passes to the output instead of the signal 1-2 that was previously connected to the output. Since the time shift between the control signals of the register 2 in the input modes and the information and its rewriting and register 2 to register 3 is determined by the frequency of the same signal formed at the first high generator / zl of the generator. For normal operation of the device, the signal frequency at the second output of generator 35 is at least three times lower Frequency on the first output. The control signal of the switch 31 is formed by the element OR 17 to one input of which signal 1 is connected from the output of the trigger 12. In this mode, the counter 9 forms., described for the tripple code reception mode, section i. The glands that control the gchggtkpm 7 and the input register 2, and the controller is set to the O position by the shaper 22 on the front of the signal of the OR element 20, that is, when the trigger 12 is switched to the 1 input setting to the O (R input) driver 22. implemented on the trigger, connected via RC integrating chain with output

0 trigger, and the time constant of the integrating chain, determining the duration of the generated pulse, should be significantly less than the period of clock pulses to prevent

5 control loss on the first clock.

The mode of reading information from register 2 is synchronized with respect to writing it to register 3, which is achieved by combining the address inputs with registers and

0 gating inputs, respectively. The write mode setting signal for register 3 is generated by trigger 12; input data register 3 is connected to the output of register 2. The completion of the recording mode corresponds to

B the time of occurrence of signal 1 at the output of / - (n 1) i. after passing p / 2 clocks to the input of the counter 7.

The output of information from buffer register 3 to output register 4 is combined with

0 transmission of information to a computer communication unit. The signal for requesting information from an external device is received via the bus. The request is from an eleg-rnta with the third state. In this case, the first input of the trigger 15 generates a signal I hook as it is also connected to the supply voltage bus Unm through the limiting element 36. Thanks to this connection, the input of the trigger 15 ensures the normal operation of the device and

0 autonomous operation, i.e. without communication with an external device. Obviously, in the absence of this device by signal 1 at the first input, trigger 15 is continuously prepared for transfer to state 1. Ac5 setting of trigger 15 in 1 occurs at the front of the signal 1-2 , if the input, output or acknowledgment of information is not recorded at a given time interval. Otherwise, signal 1 at the output of the element

0 OR 18 trigger 15 on the third input is forcibly held in the state O. If trigger 15 is not blocked, and a request is received from the external device (or this device is not present) on the signal edge 1-2

5, the trigger 15 is converted to 1. A trigger is set to a 16 in 1 signal (since a constant signal 1 is constantly applied to its first input).

The signal from the output of the trigger 16 through the OR elements 17 and 20 transforms the forron 22, which sets the counter 7. The initial (zero) state to the working state. Switch 31 signal from the element OR 17 mouth; 1navl1; 1detega to pass. on the counter 9 with a step with -. code 35, which reached work force R pg: osmagri nom mode with high: mt: g - ..

(significantly. 1- - -. / 1. -;, MEAT SOUTH AT rtli.iO BVT}:. //: s; V ;; i g (V. 1 o

for h //, i: i-- v. Goth signals passed - o-,: .-. . .. that op 31, that is, the course of vrs; er, g., ... with and about the register of all

IChFOrMap ,. . - :: ..: -I -1 - .. I 3 К КЯ К С ЦС ЛЬЬ Ю

...,:. ,, Hi: ..; h is used mode 1n; 1 .. to; D Hb-: I - yr. Data in d

H.iCTpS: 1O. :. . : measures: d; 1Г1 decrease

time cm-1-; .:;.:; them in register 5, in i-iOTHO1 1; -;; ; -. ; : ien on co-chi ;. Cattle and .. i.- ... r-.i;, - ::; And-. - matsii on pfy-i- c tpu n. ;; pc-ii: chr distortion displayed p .-; and -----nor. Miofii.i h g about the distortion. (1 / i--. But ggispg; tp p: /, time nepOMCiJi:

be MALYGL I am ..:. . -CH; 1OM INSOTS:

ONNIA AND (.-., C .-- L MKiii

Izvedenich and .. M. cpgo. Sectional and black ..i. iv-5.:;

divided by sh.-..-; .. m. -r bins HHIJ.;, matsii, ogrnmchch-1; ellme one. CIM - tion. In 1 pi: .iui..Ht ie, usgro, the number of sections tuv: .- -: K .U is equal to eight P.

COMPLIANCE: -. :, |, D 1uL Unnei:.:; .

23. Section two. chn: i i Hibi uprailenmch og / liiribHHf:: S. ;. : p.-ken o6pf) 3Oiib RYa:,

r- | l; 0 i indie id- ....: .. chi-wools. tgch1-. ; ; / work sections n pugra 5.

Formed 1 / 21. similarly for- cally. 21. Fori fi es pulsed gigabytes on bnciiMv: gigzp control so.) Control 1: n-sp mBy information: my no pet, p.

 . (tsletg-. h from wear l - but

time. information from register 3. With this npf, the influence of transients on the front of the read signal is ruled out. Simultaneously with the control of the register 5, signals are formed for transmitting data to an external device, for example, into a computer-wetted DRY block; The trigger 16 generates the Ready signal, which is an asynchronous signal to the signal. Over the output of the register 3, the signals are formed. e at the output of the driver 21 signals Gakty.

In the device drawing shown in the drawing, the time interval between the cycles of input, output and output of data for reproduction is minimal and equals one signal period. 1 J With the JIGM, the minimum is reached. The program information is adjusted: () . -: ... it is enough to reproduce the information between the output of Lemsng OR 18 and the input of the trigger 1b to set the timeout; And g, m: i p and and; p g C u m u y th time y k. e d er: to v, y

Information, Dota tm -l n i: - ere individual / - | b: -. amplifiers ..;: io: -, -; parallel to the extension - mC. l.) -o,. iicop:. eii v. None Hiivre DSPH (MCH;: RR G POM OY yyyy-p

diodes, lamps on to an mpchn and and dru1 / indicators. In register 3 :: {dfuiTrq --- (information received: -or- ici-5 U: 1 e

WITH TNYALOV.

Equal to them 1 and his register 4 ispgg., .-; s for drying p. her yus

formltsy. Thanks to the atom.: 1. (

POSSIBLE C), -; iiiU1 ian., PrG NTP -. YU ;

P (H -: - I .-. П: .т. ,,,. Nnij: -h; g., Nk) g. PJ-., OL1 visually pre-gtv-pgg diggsettsru dzn

FY O 39 FI XI g, O 3; : and:. . , 1s, the state of the television signal - -. g, - ;;: o. th luminosity indiro ji / o: - -.m 5; g

Shihs telesig nalo. ..; ..

Flashing light chip chip hours; ,; 1 groystva providing - i;:; ir, i:,; Registration in the register 5 of Infomasch M with: m,: i-sfov 3 and 4. If asg.,.; (El. ..... Registers 3 and 4 have i riuoi iiii non (v. c: r:,. ILI chenie, in adjacent cycles of ligenia-pfpg

mation to register 5 and

IOOGfGN i-e M ..:.

through amplifiers ratio m y. -, ,. :: (The indications will be:, -} ic;, .. rh-: creating an effect mi -..iu.a..G / .-. G, ... / casein red chzue with - .. ., one-bit bottom dio1. nsch about; i: t: / -: .g

PMY upon receipt of tries. fom; l, - h1 trigger 16 changes its:. well, the opposite. Moreover, l-.mem :: C signal control .-: neither: 1 KOMMVI. -. /. . -H; -;., :) to the logical switch 31. L log. psim; The values of the control signal-hmm-.Matir 3 / skip the signal output from pet ister 3 or 4 pa. which skull element is EXCLUSIVE OR 24 (working in the mode in question when the signal O is at its second input as a repeater on the first input) arrive at the information input all sections of register 5

Installed pot cheat between l

Information OT or g and ..; - ;;, O B 3 M f V i

the melting luminescence of the paddle indicators is held until the receipt of the acknowledgment command 1 5. according to which; His Vep.th. with between the newly received informatien per.- 1: 1 ps 3 and previously raising the information center. 4th register 4 should disappear Naturally, rip and atom will disappear and blink; there are no indicators that are in line with the received television signal -:. G ,, - .; : og; g 1 n pn; -KWM even luminescence t / v: g. (, - Sishal 1 5 receives an IR trigger trigger 13 which is on the front of the signal of command 1-5 in cocroflHHf 1 Signal from trigger 13 action-on input triprer 14 makes it possible to set it to state 1 on a tooHT0-contact signal 1 2 if, when this signal is received, n is fixed

CYCh H BBO I OR CONCLUSION T 6 OGELVMONTE

OR 18 to the inverting input element And 30 does not receive a blocking signal 1 Signal 1 from trigger 14 returns the trigger C-p 13 to state 0 providing one

PATCHING THE CYCLE OF THE MOVEMENT noMf that signal from trigger 14 through eleptente / M 20 and shaper installed iri counters 7 in the chalet position a - 1 4 / TJ p31 gear / ni / od high i id. It is light | about igts; ъ j r sec (m 1kg / yes of the 35 Ztmm gtsnhroni-i-ru-t hr operation of all the device nodes and it is guaranteed to be three times the oni of the confirmation

In paei with a multiplayer mode, regig 3 is set to one ohim GCIHPRTShPa 4 p | Tapio 3f mode (input) (rot) pingigunap 1 of output 14 During the time i used the make-up artist 14 v ha -uplRn to 1 boarder information from information from the register 3 to pm-tr} Trigger 1 1 mouth to O in L - a post, n lpmiq cap of 7 p / 2 i, xw by signal 1 PONCH) (n I / It is obvious that after the cycling ri has been performed, the state is triturated (switch 32 does not

It is based on the information about the “4-by-4 and issued on the chorexplo- sion or withdrawal / re-counting before registering in register 3 of the new npe / jnapnTent information but register in the RBO register

yes 2

In those THU (at the exit from the display element elements (not shown in the drawing) the reproducible information in the device is distorted, measures are taken for their dynamic control. The health of the indicators is performed by the control command. The command as a signal I is fed to the input of the AND WITH KEY А- OIU, FF OR 24 KOTOI when VTOM is transmitted to the pe, i im HI f pty.oornni coming to him about one another hey to / from the commutator 3 For l (IK information is entered i pr i i i i b i the sun is inverted that

MUST PRICH I TI MSMJHf and 1. NZ NG PG LIVO

pdinator's positive agreement; This is due to the fact that yLipuiicisa Indiators are from | the following CBJs and the three states are submitted by the Yumandm rumpn / i are recognized as non-hygienic by the fact that in the p-th schemes -nr tp is able to do it) e o; n o -) / IR i iriTOpo

and a substantial part of the apparatus of the device sections of the register 5 and amplifiers 6

Claims (1)

Due to the construction of the device, not only the autonomous operation and reproduction of television signals on the controller's board is provided, but also the input of television signals to the computer. At the same time, it controls the reliability of the received information, combining the verification of the absence of distortions of the television signals by interference in the communication line and dynamic control. indicators and control units thereof. Formula of the invention. A device for reproducing television signals comprising a setpoint generator. which is connected to the first input of the input register; the second output of the setter is connected to the first input of the first trigger; the pulse formers of the first output generator are connected to the first input of the first output controller; the connections to the corresponding address inputs of the input register of the first buffer register, demultiplexer, demultiplexer outputs connected to the first inputs of the corresponding amplifiers, the outputs of which are connected to the corresponding input of the output pins which is the first output The first third third fourth fifth fifth trigger i output of the second trigger is connected to the first BV-ODE of the first OR element and the second output of the device is the first element AND the first element OR the second element is decercated, the first element of the deceleration is The third fourth fifth fifth sixth seventh triples are introduced into it. Switches elements EXCLUSIVE or inverters second delay element and second buffer register limiting element third counter second third and fourth element nty OR the second third elements AND the first and second outputs of the generator are connected respectively to the first input of the first switch and the second counter whose first and second outputs are connected respectively to the same inputs on the OR element and the second output of the second counter is connected to its second input and the second input of the first counter whose penultimate output through the first inverter is connected to the first input of the first element And the output of which is connected to the second input of the input register whose output is connected to the first the first input of the first buffer register and the first element EXCLUSIVE OR the first output of the setting device is connected to the second pass of the first element EXCLUSIVE OR, the second output to the first input of the third trigger and the OR element, the third output to the second input of the first switch, the first input of the second, third elements AND and the fourth trigger, the fourth output - with the third output of the first switch, the second input of the first AND element, the first input of the fourth OR element and the second input of the third OR element, the fifth output - with the first input trigger, the sixth output is connected to the first input, the second element EXCLUSIVE OR, the output of which is connected to the second inputs of the amplifiers, the outputs of the first element EXCLUSIVE OR, the second element And the second inverter are connected respectively to the first, second and third inputs of the sixth trigger, whose output connected to the second input of the second element I and through the first delay element to the second input of the first trigger, the output of which is connected via the second delay element to the first input of the third trigger, the output of which is connected to the first input of the first OR element and the buffer register, the first element OR you are connected to the fourth input of the first switch and the second input of the fourth OR element, the output of which is connected to the input of the first pulse shaper, the output of the first switch is connected to the third input of the second counter, output n This trigger is connected to the first input of the seventh trigger, the output of which is connected to the third input of the first, third OR elements, the second the input of the fifth trigger and the first input of the second buffer register, the output of which is connected to the first input of the second switch, the output of which is connected to the second the input of the second element EXCLUSIVE OR, the output of the first buffer register is connected to the information input of the second switch and the second input of the second buffer register and is the third output of the device, the output of the second element OR is connected to the third input of the input register of the first, second buffer registers, through the second pulse shaper - to the first input of the demultiplexer and is the fourth output of the device, the output of the second trigger is connected to the second input of the demultiplexer and through the third counter to the third input of the second switch, the output of the third element I is connected to the second input seven seconds of the trigger, the output of the third element OR is connected to the second input of the third element And the fourth trigger, the output of which is connected to the first input of the second trigger, the third the fourth trigger input is the input of the device and is connected to the power supply terminal through the limiting element, the output of the second to last digit of the first counter is connected to the second input the second trigger, the third input of the third, seventh trigger, the input of the second inverter and is the fifth output of the device; the output of the last digit of the first counter is connected to the third input of the first trigger; the address inputs of the second buffer register are combined with the corresponding address inputs of the first buffer register