KR100210815B1 - Apparatus for generating read signal about memory for announcement message - Google Patents

Abstract

The present invention is a read mode control signal for the announcement message memory for generating a read mode control signal for the announcement message memory to test the read / write function for the announcement message message using a microprocessor A generator, comprising: a switch having a memory for an announcement broadcast message accessed by a clock signal provided through a subhighway from a time switch and a first read mode control signal generated by a frame synchronization signal; When the test request signal for the read / write function of the announcement message memory is applied from the operator, a second read mode control signal, a read selection control signal, and a read selection clock signal for accessing the announcement broadcast memory can be generated. Microprocessor; Read mode control, which is controlled by the read selection control signal output from the microprocessor, selects one of the first read mode control signal and the second read mode control signal and transmits the read mode control signal for accessing the memory for the announcement broadcast message. It is configured to include a signal transmitter.

Description

Read mode control signal generator for memory for announcement message

The present invention relates to an apparatus for generating a read mode control signal for a memory for announcement broadcast messages, and more particularly, to an apparatus for generating a read mode control signal for testing a read / write function for a memory for announcement broadcast messages.

In the exchange, the memory for announcement messages is a memory that stores announcement messages for special services or other subscribers. This announcement message memory has been previously provided to the announcement broadcast message memory by generating a read mode control signal using a clock signal and a frame synchronization signal (Frame SYNC) provided from a time switch through a subhighway (SHW). In particular, it is provided to continuously send a message at a designated time.

However, when the microprocessor tries to test the read / write function of the announcement message memory, the frequency of the clock signal provided from the time switch to generate the read mode control signal and the main clock signal used in the microprocessor are different. As a result, the microprocessor could not detect the read timing of the memory for the announcement message and could not perform the read mode control signal test (or debugging) process.

Accordingly, the present invention has been made to solve the above-described drawbacks, and to generate a read mode control signal for the announcement message memory to test the read / write function of the announcement message memory using a microprocessor. An object of the present invention is to provide a read mode control signal generator for a memory for announcement broadcast messages.

In order to achieve the above object, the apparatus for generating a read mode control signal for an announcement broadcast message memory according to the present invention includes a first read mode control signal generated by a clock signal and a frame synchronization signal provided through a subhighway from a time switch. A switch having a memory for announcement messages accessed by a second read, wherein if a test request signal for a read / write function of the announcement message memory is received from an operator, a second read capable of accessing the announcement message memory can be accessed. A microprocessor for generating a mode control signal, a read select control signal and a read select clock signal; Read mode control, which is controlled by the read selection control signal output from the microprocessor, selects one of the first read mode control signal and the second read mode control signal and transmits the read mode control signal for accessing the memory for the announcement broadcast message. It characterized in that it comprises a signal transmission unit.

1 is a block diagram of an apparatus for generating a read mode control signal for an announcement broadcast message memory according to the present invention in an exchange.

FIG. 2 is a detailed circuit diagram of the read mode control signal transmitter shown in FIG.

* Explanation of symbols for main parts of the drawings

100: time switch 110: read mode control signal generator

120: microprocessor 130: read mode control signal transmission unit

140: memory for announcement message

The above and other objects and various advantages of the present invention will become apparent from the following description of the preferred embodiment.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an apparatus for generating a read mode control signal according to an embodiment of the present invention, wherein the announcement broadcast message memory 140 and the subhighway store the announcement message information so that the subscriber can provide various announcement messages. For the announcement message in the normal mode by using the frame synchronization signal of the clock signal transmitted from the time switch 100, the time switch 100 and the clock signal used when generating the read mode control signal through The microprocessor 120 performing the control to test the read / write function of the read mode control signal generator 110 for generating the read mode control signal for the memory 140 and the memory 140 for the announcement broadcast message. The read mode control signal and the read mode control signal provided from the microprocessor 130 are controlled by the control signal provided from the microprocessor 120. It consists of a read mode control signal transmission unit 130 for selectively transferred to the read-mode control signal outputted from the generator 110.

The read mode control signal generator thus constructed is driven as follows.

First, the read mode control signal generation unit 110 always receives the clock signal CLOCK and the frame synchronization signal generated from the time switch 100 regardless of the read / write function test of the memory 140 for the announcement broadcast message. FS generates a read mode control signal SHW_RD of the announcement broadcast message memory 140. The generated read mode control signal SHW_RD is transmitted to the read mode control signal transmitter 130.

As shown in FIG. 2, the read mode control signal transmitter 130 includes a D flip-flop FF1, an inverter IN, and buffers B1 and B2. The read mode control signal SHW_RD and the read mode control signal CPU_MEM_RD transmitted from the microprocessor 120 are selectively transmitted.

That is, when the read / write function test request signal for the announcement broadcast message memory 140 is not applied, the read select control signal RD_SEL_DATA output from the microprocessor 120 is provided in a 'high' state. The D flip-flop FF1 outputs a 'high' state signal applied to the input terminal D in synchronization with the read select control signal RD_SEL_CLK provided from the microprocessor 120 through the output terminal Q. The signal output from the D flip-flop FF1 is transmitted as an input signal of the inverter IN and an enable control signal of the buffer B2.

Accordingly, the buffer B2 is disabled, and the inverter IN transmits the signal converted to the 'low' state as the enable control signal of the buffer B1. Accordingly, the buffer B1 is enabled to transmit the read mode control signal SHW_RD provided from the read mode control signal generator 110 to the read mode control signal MEM_RD of the memory 140 for announcement broadcast message. .

However, when a read / write function test for the announcement message memory 140 is required, the read select control signal RD_SEL_DATA provided from the microprocessor 120 is output in a low (0) state so that the D flip-flop ( FF1) outputs a 'low' signal in synchronization with the read select control signal RD_SEL_CLK.

Accordingly, the buffer B2 is enabled and transmits the read mode control signal CPU_MEM_RD transmitted from the microprocessor 120, while the buffer B1 is connected to the enable control signal provided through the inverter IN. It is disabled by the read mode to block transmission of the read mode control signal SHW_RD transmitted from the read mode control signal generator 110. Therefore, when testing the read / write function of the announcement broadcast message memory 140, the read mode control signal CPU_MEM_RD provided from the microprocessor 120 is transmitted to the announcement broadcast message memory 140.

The announcement broadcast memory 140 transmits a predetermined announcement message accessed by the read mode control signal MEM_RD and an address provided from the microprocessor 120 to the microprocessor 120 to read the above-described read / write message. Allows you to test the write function.

As described above, the present invention blocks the read mode control signal provided to the conventional announcement message memory and tests the read mode control synchronized with the main clock signal of the microprocessor when the read / write function of the announcement message memory is tested. By providing a device for generating a read mode control signal to provide a signal, the memory for the announcement message can be accessed without any confusion with the read mode control signal that was previously provided as the announcement message memory when the memory read / write function was tested. It can be effective.

Although the present invention has been described as the above-described embodiment, those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (2)

In an exchanger having a memory 140 for announcement broadcast messages accessed by a first read mode control signal SHW_RD generated by a clock signal and a frame synchronization signal provided from a time switch 100 via a subhighway, When a test request signal for a read / write function of the announcement broadcast message memory 140 is applied from an operator, a second read mode control signal CPU_MEM_RD capable of accessing the announcement broadcast message memory 140 and a read selection A microprocessor 120 generating a control signal RD_SEL_DATA and a read select clock signal RD_SEL_CLK; Controlled by the read selection control signal output from the microprocessor 120 to select one of the first read mode control signal (SHW_RD) and the second read mode control signal (CPU_MEM_RD) for the announcement broadcast message memory ( Read mode control signal generator for the announcement broadcast message memory, characterized in that it comprises a read mode control signal transmission unit 130 for transmitting as a read mode control signal for access. The flip line of claim 1, wherein the read mode control signal transmitter 130 transmits the read select control signal RD_SEL_DATA in synchronization with the read select clock signal RD_SEL_CLK transmitted from the microprocessor 120. Flop FF1; A first buffer B1 for transmitting the first read mode control signal SHW_RD; A second buffer (B2) for controlling an enable state by a signal output from the flip-flop (FF1) to transmit the second read mode control signal (CPU_MEM_RD) output from the microprocessor (120); Inverter (IN) for providing a signal for controlling the enable state of the first buffer (B1) by inverting the signal output from the flip-flop (FF1) for reading the announcement broadcast message memory Mode control signal generator.