KR960009557A

KR960009557A - Matching Circuit Using High Speed Parallel Synchronous Control Bus

Info

Publication number: KR960009557A
Application number: KR1019940019851A
Authority: KR
Inventors: 최철완
Original assignee: 박성규; 대우통신 주식회사
Priority date: 1994-08-12
Filing date: 1994-08-12
Publication date: 1996-03-22
Also published as: KR970003140B1

Abstract

본 정합회로는 전전자교환기의 하위프로세서와 외부장치간에 고속 병렬동기 버스방식을 이용하여 고속의 데이타를 전송할 수 있도록 정합하는 것이다. 이를 위하여 본 회로는 다수의 외부장치를 연결하여 통신하고자하는 하나의 외부장치를 선택하여 인에이블 시키고, 상기 선택된 외부장치의 상태를 주기적으로 스캐닝 또는 인터럽트 처리하여 정상적일 시 버스 제어동작을 수행하도록 하며, 상기 하위브로세가 상기 외부장치를 제어할수 있도록 어드레스와 데이타를 고속병렬동기 제어버스로 다중화하여 송수신하고, 상기 하위프로세서의 제어신호를 수신하여 외부장치로 정합되는 고속동기 병렬 버스제어신호인 어드레스 인에이블신호(AE), 데이타 인에이블신호(DE), 데이타 기록신호(WR), 데이타 독출신호(RD), 직렬 가입자 데이타 표시신호(CD)를 버퍼링 출력하므로 전송데이타를 정합하도록 구성된다.In this matching circuit, a high speed parallel synchronous bus method is used to transfer high-speed data between a subprocessor of an electronic switching system and an external device. To this end, the circuit selects and enables one external device to communicate by connecting a plurality of external devices, and periodically performs scanning or interrupt processing of the selected external device to perform a bus control operation during normal operation. In order to control the external device, the sub-Brose multiplexes and transmits the address and data to the high speed parallel synchronous control bus, receives the control signal of the subprocessor, and receives the address signal which is a high speed synchronous parallel bus control signal matched to the external device. The enable signal AE, the data enable signal DE, the data write signal WR, the data read signal RD and the serial subscriber data display signal CD are buffered and output, so that transmission data is matched.

Description

Matching Circuit Using High Speed Parallel Synchronous Control Bus

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 고속 병렬동기 제어버스 방식을 이용한 정합회로의 블럭구성도.1 is a block diagram of a matching circuit using a high speed parallel synchronization control bus method according to the present invention.

제2도는 제1도에 도시된 외부장치 선택회로의 구체회로도.2 is a detailed circuit diagram of an external device selection circuit shown in FIG.

제3도는 제1도에 도시된 외부장치 상태 보관회로의 구체회로도.3 is a detailed circuit diagram of the external device state storage circuit shown in FIG.

제4도는 제1도에 도시된 어드레스/데이타 다중화회로의 구체회로도.4 is a concrete circuit diagram of the address / data multiplexing circuit shown in FIG.

Claims

In a matching circuit using a high speed parallel synchronous control bus method connected between a lower processor and an external device, a plurality of external devices are connected, and an external device selection means for selecting and enabling one external device to communicate with; External device state storage means for periodically scanning and interrupting the state of the external device selected from the external device selection means to perform a bus control operation during normal operation; and address and data so that the subprocessor can control the external device. Address / data multiplexing means for multiplexing and transmitting the signals to the high-speed parallel synchronous control bus, and bus control signal generating means for generating a signal for controlling the high-speed parallel synchronous bus to match the external device by receiving the control signal of the subprocessor; By the bus control signal generating means Data enable signal (AE), data enable signal (DE), data write signal (WR), data read signal (RD), and transmit / receive data, which are high-speed parallel synchronous bus control signals matched to external devices. And bus control signal buffering means for buffering and outputting the enable signal (CD).

2. The apparatus of claim 1, wherein the external device selecting means comprises: a first address decoder 21 for receiving addresses IA10-IA18 from the subprocessor and decoding the external device selection signal to generate and output the decoded addresses BS0-BS8; A second address decoder 22 which receives the addresses IA10-IA18 from the subprocessor and generates and decodes the decoded addresses BS9-BS17 by the external device selection means, and the address decoded and output from the first address decoder 21; The external device enable signal includes a first address buffer 23 that buffers BS0-BS7 by an external device enable signal and outputs the address to the external device, and addresses BS8-BS15 decoded and output from the second address decoder 22. A second address buffer 24 buffered by an external device and output to an external device, and an output address BS16-B decoded from the second address third decoder 22. And a third address buffer (25) buffering S17 by the external device enable signal and outputting the buffer to the external device.

3. The third address decoder 31 according to claim 1 or 2, wherein the external device state storage means receives an address from the subprocessor and decodes the control signal output from the subprocessor to output a state enable signal. And a first data buffer circuit 32 for receiving data from the external device and latching the data to the data buses BOF0-BOF7 by a buffer enable signal output from the third address decoder 31. A second data buffer circuit 33 for receiving data from the third address decoder 31 and latching the data to the data bus BOF8-BOF15 by the buoy enable signal output from the third address decoder 31, and inputting data from the external device. And a third data buffer circuit 34 which latches and outputs the data to the data bus BOF16-BOF19 by the buffer enable signal output from the third address decoder 31. The circuit according to claim.

The host / data multiplexer of claim 3, wherein the address / data multiplexing means receives an address IA8-IA15 from the subprocessor and buffers and outputs the buffer by an address enable signal (AA) generated from the bus control signal generating means. An address buffer circuit 41 and a lower address buffer circuit 42 which receives addresses IA0-IA7 from the lower processor and buffers and outputs the address by the address enable signal / AE generated from the bus control signal generating means; An upper data buffer circuit 43 for transmitting data ID8-ID15 from the lower processor by a data direction control signal generated from a bus control signal generating means and buffering and outputting the data ID8-ID15 by an upper data enable signal; The data D0-D7 from the lower processor is converted into a data direction control signal generated from the bus control signal generating means. The lower data buffer circuit 44 for transmitting and determining the transfer direction and buffering and outputting the lower data enable signal and the lower data received from an external device during the lower processor read cycle are enabled when the data loaded on the bus is 8-bit transmission. The 8-bit data is exchanged on the upper 8-bit data bus of the lower processor for the lower processor to read, and the lower 8-bit data of the external device is transferred to the upper 8-bit data transmitted from the lower processor to the bus during the lower processor write cycle. Is exchanged on the bus so that the lower processor reads the data exchange buffer circuit 45, and the upper address A15-A8 and the upper data D15-D8 on the bus are multiplexed from the lower processor and generated from the bus control signal generating means. Enabled by the upper output buffer enable signal, and applied to the output buffer direction control signal. The upper direction / data buffer circuit 46 outputs and the output direction is determined, and the lower addresses A0-A7 and lower data D0-D7 on the bus are multiplexed from the lower processor and generated from the bus control signal generating circuit 14. And a lower address / data buffer circuit (47) which is enabled by the lower output buffer enable signal and outputs the output direction determined by the output direction control signal.

5. The external address / data buffer circuit 46 is configured to output data from a lower processor to an external device when the direction control signal is high and to output an external device when the output control direction signal is low. Circuitry characterized in that it is output from a subprocessor.

The lower address / data buffer circuit 47 is configured to output data from a lower processor to an external device when the direction control signal is high, and to output an external device when the output control direction signal is low. Circuitry characterized in that it is output from a subprocessor.

The method of claim 1 or 2, wherein the address / data multiplexing means receives the address IAS-IA15 from the subprocessor and buffers the address enable signal (AA) generated from the bus control signal generating means. A lower address buffer circuit 41 which receives the address IA0-IA7 from the lower processor and buffers and outputs the buffered address by the address enable signal / AE generated from the bus control signal generating means ( 42) an upper data buffer circuit 43 for transmitting data ID8-ID15 from the lower processor by a data direction control signal generated from a bus control signal generating means and buffering and outputting the data ID8-ID15 by an upper data enable signal; Data direction control generated from a bus control signal generating means for data D0-D7 from the subprocessor; The lower data buffer circuit 44 buffers the output direction by the call and outputs the buffered data by the lower data enable signal, and is enabled when the data loaded on the bus is 8-bit transmission, and the external device is read during the lower processor read cycle. The received lower 8-bit data is exchanged on the upper 8-bit data bus of the lower processor for the lower processor to read, and the upper 8-bit data sent on the lower processor bus is exchanged on the lower 8-bit data bus of the external window. The upper output buffer enable signal generated from the bus control signal generating means by multiplexing the data exchange buffer circuit 45 for reading by the lower processor and the upper addresses A15-A8 and upper data D15-D8 on the bus from the lower processor. Is enabled by the output buffer, and the output direction is determined by the output buffer generation control signal. A lower output buffer enable signal generated from the bus control signal generation circuit 14 by multiplexing the upper address / data buffer circuit 46 and the lower addresses A7-A0 and lower data D0-D7 on the bus from the lower processor. And a lower address / data buffer circuit (47) which is enabled by the output direction and whose output direction is determined by the output direction control signal.

※ Note: The disclosure is based on the initial application.