KR900006830Y1 - Dtmf transceiver - Google Patents

Abstract

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Description

Strobe Signal Generation Circuit of DTMF Transceiver

1 is a block diagram of a DTMF receiver.

2 is an interface circuit diagram of a CPU and a DTMF receiver.

3 is a strobe generation circuit diagram according to the present invention.

4 is a timing diagram of a DTMF receiver.

5 is an operation timing diagram of FIG.

* Explanation of symbols for main parts of the drawings

10: CPU 20: DTMF Transceiver

40: Strobe Generator 30: Decoder

41-43: Inverter 44-45: Gate

46-47: flip-flop 48: buffer

The present invention relates to a DTMF transceiver, and more particularly, to a strobe signal generation circuit of a DTMF receiver.

The DTMF Transceiver is configured as shown in FIG. 1, and inputs 4 digit signals to generate 16 tone signals, and conversely inputs 16 tone signals to input 4 digit signals. Occurs.

4 is an interfacing timing diagram of a DTMF transceiver and a CPU. FIG. 4 (a) is a pulse waveform diagram of φ2 which is a system clock, and FIG. 4 (b) is a read cycle of the CPU. ) Is the write cycle of the CPU and its characteristics are shown in Table 1 below.

Table 1

The DTMF receiver reads and writes data as shown in Fig. 4 (b) and (c) by the φ 2 signal as shown in Fig. 4 (a) applied by the CPU. Conventionally, the DTMF transmitter receives a clock when generating a strobe signal of the DTMF receiver. In the case of the lead cycle, there was a case in which the synchronization was inconsistent with the lead cycle, and the interfacing circuit between the CPU and the DTMF transmitter was presented only to the MOTOROLA Processor, which prevented the interfacing with other types of processors.

Therefore, the purpose of this paper is to provide a circuit that can solve the strobe signal and the timing of the read / write when using a DTMF transceiver in a system using a processor.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is an interface circuit between the processor and the DTMF transmitter, and the CPU 10 and the DTMF transceiver 20 which receives the digits of the CPU 10 and generates the corresponding tone or receives the tone and sends the digit to the CPU 10. And a decoder 30 that decodes the address of the CPU 10 to enable the DTMF receiver 20 at a predetermined address and a strobe by logically combining read / write, clock, and S2 signals of the CPU 10. 3 is a detailed circuit diagram of the strobe generator 40 in FIG. 4 showing an inverter φ2 and an inverter 41-43, a gate 44-45, and a flip-flop 46-47. And a buffer 48, and FIG. 5 shows an output waveform diagram of the strobe generator 40 according to the control signal of the CPU 10. As shown in FIG.

Based on the above-described configuration, the present invention will be described in detail with reference to FIGS. 2, 3, and 5.

In Fig. 2 showing the interface between the CPU 10 and the DTMF transceiver 20, the chip select of the DTMF transceiver 20 decodes the address so that it is enabled only when the specific address is accessed.

That is, according to the output of the decoder 30 decoding the addresses A4-A15 generated in the CPU 10, the DTMF transceiver 20 is enabled when the corresponding address is a specific address.

In addition, the address A3 of the CPU 10 is connected to the RSφ terminal (Regester Select Input) of the DTMF transceiver 20 so as to distinguish a command register and a data register, and the DTMF tone as described above. Data can generate 16 tones in 4 bits (D0-D3).

R / of DTMF Transceiver 20 The terminal of the CPU The terminal is connected to the terminal and the φ 2 terminal receives the strobe signal through the strobe generator 40.

The strobe generator 40 has four control signals from the CPU 10 as shown in FIG. , , CLKout, S2) is received to generate the strobe signal φ2.

FIG. 5 (a) shows the clock signal, the S2 signal, the read signal and the write signal output from the CPU 10. The strobe signal of the DTMF transceiver 20 required by the timing diagram of FIG. (φ2) is generated.

In FIG. 3, the gate 45, which inverts the outputs of the inverter 43 and the gate 44 by being negatively multiplied, resets the second flip-flop 47 because a low state signal is input when no read or write is performed. By making the state, the? 2 signal is kept low.

First, a write cycle will be described with reference to FIG. 5B.

A set of flip-flops 46 by inverting the S2 signal as shown in FIG. 5 (a) and (b) through the inverter 42 ( Is applied to the write signal, as shown in (d) of FIG. ) Is applied to the input terminal, and the clock as shown in (a) of FIG. 5 (a) is inverted through the inverter 41 and applied to the clock terminal of the first flip-flop 46.

Here S2 is used for guard time in the write cycle.

At this time, the light signal ( ) Is a delay of about one clock when the first flip-flop 46 passes by the inverted clock through the inverter 41, and the output and the write signal of the flip-flop 46 ( Inverting and inputting the gate 44 performs an AND operation on the two inputs and outputs the result as shown in (b) of FIG.

At this time The reason for delaying the signal by about one clock is that tRWS (R / before φ2 occurrence) as shown in FIG. To fully satisfy the setup time). When the write signal is generated, the read signal is not active and outputs a "high" signal, and the inverter 43 outputs a "low" signal as shown in FIG. 5 (b) (a). Therefore, since the output of the gate 45 that is negatively multiplied is the same as the output of the gate 44, the reset of the second flip-flop 47 is canceled during the period as shown in (b) of FIG.

Accordingly, the second flip-flop 47 generates a strobe signal φ2 such as (c) of FIG. 5 (b) by a clock such as (a) of FIG. 5 (a). Applied to the φ2 stage of the DTMF receiver 20;

Next, a read cycle will be described with reference to FIG. 5 (c).

When the read signal is in the active state, the write signal cannot be in the active state. Therefore, the write signal is in the "high" state. As a result, the gate 44 remains in the "low" state as shown in (b) of FIG. have.

At this time, since the lead signal through the inverter 43 is in the "high" state as shown in (a) of FIG. 5C, the gate 45 outputs the "high" signal for the same period as that of the output of the inverter 43. The reset of the 2 flip flop 47 is released.

Therefore, the second flip-flop 47 transmits the strobe signal φ2 as shown in (c) of FIG. 5 (c) to the φ2 stage of the DTMF receiver 20 through the buffer 48.

Since the DTMF transceiver 20 outputs valid data only up to 20nSec from the falling edge of the strobe signal φ2 as in the lead cycle of FIG. 4, the lead signal of the CPU 10 is output. The signal must be inactive or inactive at the same time as the fore edge of the strobe signal φ2.

In FIG. 3, when the gate delay is considered, the read of the CPU 10 is performed before the falling edge of the strobe signal φ2. ) Becomes inactive.

As described above, there is an advantage in that the strobe signal of the DTMF receiver and the read and write timing of the CPU can be precisely synchronized.

Claims (1)

In the strobe generation circuit of the DTMF receiver 20 which interfaces with the CPU 10 to generate DTMF tones or converts DTMF tones into digit data and outputs them to the CPU 10, a read signal during a read cycle ( A first flip-flop through a first means for determining whether a lead signal is generated through an inverter 43 for inverting the state of the signal, and an output of the inverter 42 for inverting the S2 signal to determine a cycle of the light cycle during a light cycle. (46) the set end ( And the clock is inverted to the clock terminal CK of the first flip-flop 46 through the inverter 41. ) Is applied to the data input terminal D of the first flip-flop 46 to delay the write signal by one clock to satisfy the set-up time. ) And a second means for determining whether or not a light signal is generated through the gate 44 of the inverse input and the output of the first flip-flop 46, and the input of the first means and the second means inverted input The output of the gate 46 to be negatively multiplied to reset the second flip-flop 47 And a third means for canceling the reset when a read or write signal is generated and generating a read or light stove (φ2) during a corresponding reset release period by a clock. .