JPS6123449A - Transmission system - Google Patents

Abstract

PURPOSE:To eliminate accumulation of distortion of a bit timing of a reception signal by using a transmission clock to control the bit period of a signal transmitted from a node equipment in a loop transmission system. CONSTITUTION:A frame synchronizing signal is supplied to a start field 31, a data to be transmitted between node equipments is put into a data signal, and an idle field 33 consists of idle columns. When the time length of a transmission frame 30 is kept constant, the time length of the idle field 33 is changed according to a change in the bit period to absorb the change in the bit period. Thus, the distortion of the timing of the reception signal is not accumulated.

Description

[Detailed description of the invention] [Technical field of invention] This invention relates to a loop transmission system.

[Prior art]

FIG. 1 is a block diagram showing a conventional system, in which (1) is a synchronization node and (2) is a communication node.

(3) is a loop-shaped transmission path, (4) is a terminal interface, and (5) is a terminal. Multiple communication nodes (2)
are connected to each other in series by a transmission path (3), and data is transferred between the plurality of communication nodes, but only one communication node is representatively shown in FIG. Only one synchronization node (1) is connected within one loop-shaped transmission line (3).

In these nodes, (lla) and (llb) are receivers respectively, (12a) and (12b) are transmitters respectively, a3 fly 2 stick buffer register, (14a).

(14b) is a reception timing circuit, aS is a transmission timing circuit, and ae is a relay shift register.

The synchronization node (1) transmits a bit frame 1 to the transmission path (3) through the transmitter (12a) at a bit period of n determined by the transmission clock generated by the transmission timing circuit aS.
Send out signals in the form of reality. This signal is transmitted to the communication node (
2) is received by the receiver (nb). Receiver (ll
b) extracts timing information, ie, reception clock information of the received signal, from this received signal, and passes this information to the reception timing circuit (14b). Therefore, the received power that is the output of the reception timing circuit (14b) completely coincides with the transmitted sunset time. The output of the communication node (2) TEHA v SEHA (llb) is input to the relay shift register a day, is shifted by the reception clock that is the output of the reception timing circuit (14b), and is sent to the transmission path (12b) via the transmitter (12b). 3).

Therefore, in the communication node (2), the receiving data rate of data input to the receiver (llb) and the transmitter (1
The transmission data rates of the data sent from 2b) are equal.

The relay shift register aG includes a parallel signal output terminal and a parallel signal input terminal, and performs input/output of data between the terminals n and the like and the terminal (5) via the terminal interface (4).

In this way, the rt signal transmitted from the synchronization node (1) is relayed by multiple communication nodes while maintaining the bit period determined by the clock at the time of transmission, and is sent to the receiver (lla) of the synchronization node (1). It is activated. The relationship between the receiver (lla) and the reception timing circuit (14a) is the relationship between the receiver (llb) and the reception timing circuit (14a).
4b), the output of the receiver (Ila) is controlled by the reception clock which is the output of the reception timing circuit (14a) and is input to the elastic buffer register (IIK).The elastic buffer register a3 is , generally FIFO (first-in-
(first -0ut) register 3. The loop-shaped transmission line (3) is provided at the ninth position to absorb the phase shift caused by the delay time for the signal to pass through. The signals inputted to the elastic buffer registers are read out in the order of input by the transmission signal generated by the transmission timing circuit 0, and are sent out via the transmitter (12a).

The conventional loop transmission system is configured as described above, and the maximum number of node devices that can be accommodated in the loop transmission path (3) is determined depending on the performance of the reception timing circuit. This is because distortion of the received signal due to external noise, data pattern jitter, etc. accumulates in each node device, and eventually it becomes impossible to extract a stable timing signal. That is, the conventional system had a drawback in that the number of four node devices that could be accommodated within a loop-shaped transmission path was limited.

[Summary of the invention]

[This invention was made in order to eliminate the runner-up problems of the conventional ones as described above.In this invention, a tactile transmission timing circuit is provided in each communication node device, and a transmission clock oscillated by this transmission timing circuit is used. The bit period of the signal sent from the node device is controlled by this method, and the accumulation of bit timing distortion in the received signal is eliminated.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.
The same reference numerals as in the figure indicate corresponding parts (20a).

(20b) is a notebook device, (4a), (4b)
, are terminal interfaces corresponding to (4) in Figure 1, and (5a) and (5b) are (5) in Figure 1.
Terminals corresponding to (13a) and (13b) are the two-stick buffer registers corresponding to +131c in Figure 1, (15a) and (15b) are -'t rt-Pn, respectively.
A transmission timing circuit (16a) corresponding to aS in FIG.
) and (, 16b) are relay shift registers corresponding to the rtn shown in FIG. 1, respectively. Also (100a).

(100b) So3zojL reception 10y/-(10x
a) and (101b) are the received data. Since the node devices (20a) and (20b) have the same configuration, the operation of the node device (20a) will be described below.

Receiver (11a), received data (101a), reception timing circuit (14a), reception clock (100a),
Relay shift register (16a), terminal interface (
4a), the operation of the terminal (5a) is similar to that of the receiver (1) in FIG.
1b), the reception timing circuit (14b), the relay shift register αe1 terminal interface (4), and the terminal (5). In FIG. 1, the data shifted out from the relay shift register ae is input to the transmitter (12b), but in FIG. and is written to the elastic bag 7 agitator (13a). Transmission timing circuit (15a), two-stick buffer register (13a), ) transmitter (1)
2a) is similar to the operation of the transmission timing circuit aS1 elastic buffer register (131,) transmitter (12a) in FIG.
The bit period of the data sent from a) to the loop transmission path (3) is independent of the reception clock (100a) and is determined by the output of the transmission timing circuit (15a) which is generally asynchronous to the reception clock (100a). determined by a certain transmission clock.

Furthermore, if there is a fairly large difference in the frequency of the transmission clock in each node device, the length of the frame will expand or contract due to the frequency difference, so the frame structure must be able to absorb this expansion or contraction. .

FIG. 3 is a format diagram showing the frame structure used in this invention, where (to) is a transmission frame, 130 is a start field, C31 is a data field, (to)
is the idle field, and the starting field is 0υ
The data field consists of a predetermined number of bits, respectively.The frame synchronization signal starts at 74-/u.
)'work,,,□,7-1. □□, Eo The data to a power of 1 is included in the data signal, and the idle fields (to) from n to n1 are empty. If the time length of the 11 transmission frames (to) is kept constant, the change in the bit period will be The time length of the idle field changes to provide a margin for absorbing changes in the bit period.

〔Effect of the invention〕

As described above, according to the present invention, there is no accumulation of timing distortion of the received signal due to noise or pattern jitter, unlike in conventional systems, and a large number of node devices can be connected within one loop-shaped transmission path. It has the advantage of being able to In addition, in conventional systems, if a synchronization node device were to fail, the entire system would stop, but in this invention, all node devices have the same configuration, so simply bypassing the failed node device can cause the entire system to stop. can eliminate the impact on

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional system, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a frame format diagram used in the present invention. (3)...Transmission path, (4a)...Terminal interface, (51...Terminal, (11a)...Receiver,
(12a)...Transmitter, (13a)...Elastic buffer register, (14a)...Reception timing circuit, (15a)...Transmission timing circuit, (16a)...Relay shift register, ( 20a)
, (20b)...each node device. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] In a transmission system in which a plurality of node devices are connected in cascade to each other via a loop-shaped transmission path and data is transferred between the plurality of node devices, a start field including frame synchronization information made up of a first predetermined number of bits, and a data field including data to be transmitted made up of a second predetermined number of bits;
means for organizing a transmission frame of a predetermined length of time by an idle field that is made up of empty fields and serves as a margin corresponding to a change in bit period; provided in each node device of the plurality of node devices; a reception timing circuit that detects a reception clock pulse for the reception signal from a reception signal to be received; a relay shift register to which the reception signal is input and shifted by the reception clock pulse; and a signal shifted out from the relay shift register is sequentially input. a transmission timing circuit that generates a transmission clock pulse that determines the bit period of the signal sent from the node device to the loop-shaped transmission path; A transmission system characterized by comprising means for reading out and transmitting it to the loop-shaped transmission path.