JPH03181243A - Signal synchronizing system - Google Patents

Abstract

PURPOSE:To prevent the signal errors due to the difference of delay time between the working and spare systems at the switch of both systems by storing the initial frame phase of the working system, comparing this stored frame phase with the frame phase of a received signal, and setting the delay value of the delay circuit. CONSTITUTION:The frame synchronizing circuits 1 and 5 of systems 0 and 1 receive the signals having different frame phases due to the difference of transmission delay between both transmission lines and then secure the frame synchronization to detect the frame phases respectively. The frame phase comparators 2 and 6 of systems 0 and 1 compare the frame phase signals of its own systems outputted from both circuits 1 and 5 with the phase outputted from a frame phase storage circuit 9 storing the delay value of the working system at start of a system. These comparison results are sent to the control circuits 4 and 8 respectively. At the same time, the delay circuits 3 and 7 that can vary the delay values of both systems 0 and 1 set their own delay values via the circuits 4 and 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal synchronization system in a frame synchronization signal system with duplex transmission paths.

[Conventional technology]

Generally, in a frame synchronization signal system with duplex transmission paths, the propagation delay time differs for each transmission path (working system and protection system), so the frame phase of the received signal differs. Therefore, when switching from the working system to the protection system, a signal error may occur due to this delay time difference when the time division multiplexed signal receiving device or the like is pressed.

In order to prevent signal errors at the time of switching, a configuration as shown in FIG. 2 has conventionally been adopted. That is, the duplicated O system and 1
Each receiving section of the system includes frame synchronization circuits 10 and 14, frame phase comparison circuits 11 and 15 that compare frame phases of the own system and other systems, and delay circuits 12 and 16 that delay and output data signals. , frame phase comparison circuit 1
control circuits 13 and 17 for controlling the delay amount of delay circuits 12 and 16 according to signals a and b indicating whether the outputs of 1 and 15 or the own system is 0 system or 1 system; Ru.

Here, the 0-system and 1-system receiving circuits each receive data signals with different delay amounts, and the frame synchronization circuits 10 and 14 perform frame synchronization to detect the frame phase. Further, the frame phase comparison circuits 11 and 15 compare the frame phases of the own system and the other system to detect the delay time difference between the two systems, and the difference in the amount of delay between the delay circuits 12 and 16 of the 0 system and 1 system is detected.

The control circuits 13 and 17 control the delay amount so that it becomes equal to the detected delay time difference between the two systems. That is,
The frame phase of system 1 is 0.2 compared to the frame phase of system O.
If b is delayed by the frame length, it is determined that the propagation delay time of the transmission path of the 1st system is larger than that of the O system by 0.2 frame length.

By controlling the delay amount of the 1-system delay circuit 16 to be smaller than the delay amount of the 0-system delay circuit 12 by 0.2 frame length, the phase of the output data from the delay circuits 12 and 16 of both systems is controlled. be equal.

Here, the O system is the active system at system startup.

When the 1st system is used as a standby system, the delay amount of the O system is generally set at the center of the delay circuit 12 in order to equalize the range of absorption of delay time differences.

As described above, the delay amount of the 1st system is set to be equal to the frame phase difference with the O system, and is added or subtracted by b from the center position of the delay circuit.

[Problem that the invention seeks to solve]

In the conventional signal synchronization method described above, the delay amount of the 0 system is fixed and the delay amount of the 1 system is changed to absorb the delay time difference, and signal errors at the time of switching do not occur in the following cases.

This is switching from the 0 system to the 1 system, or switching back from the 1 system to the O system without changing the delay amount of the O system line. For example, when switching from the O system to the 1 system due to a line failure in the O system, and then switching back from the 1 system to the O system due to line recovery of the O system,
In addition, due to a failure in the receiving circuit of the O system, switching from the O system to the 1 system, and subsequent replacement of the receiving circuit of the 0 system caused the switching from the l system to the O system.
This is the case when disconnecting and returning to the system.

However, in cases where the delay amount of the O system line is changed,
In other words, due to a line failure in the O system, when switching from the 1 system to the 0 system when the 0 system line is changed, a signal error occurs at the time of switching, which makes it impossible to absorb the delay time difference due to the line change. There is a problem.

By the way, in the configuration shown in FIG. 2, a frame phase generation circuit (not shown) that generates an arbitrary frame phase is added, and the delay amount is controlled to match the phase from the frame phase generation circuit. If done, the received frame phase and
Since the internal frame phase relationships are independent, when the propagation delay amount changes due to two line changes, the delay may shift by one frame length depending on the two phase relationships.

An example of this case is shown in FIG.

Here, the amount of delay in the transmission path is shown by a broken line, and the amount of total delay in the delay circuit is shown by a solid line. Also, the arrow indicates the internally generated frame phase, z-,6, and the total delay is the sum of the delay amount of the difference between the frame phase of the received signal and the internally generated frame phase, to the delay amount of the transmission path. amount.

Here, the duplicated signal receiving circuits are referred to as 0 system and 1 system, respectively. The relationship between the received frame phase of the O system, which is the active system at the time of system startup, and the internally generated frame phase is the third
As shown in Figure (1), when the received frame phase is slightly delayed from the internally generated frame phase, the total delay amount of the 0 system is approximately equal to the delay amount of the transmission path, and the delay circuit It all adds up.

Let us now consider the case where a fault occurs in the O-system transmission line and one line is switched over to restore the system. In this case, when the amount of delay on the transmission path becomes slightly smaller than the amount of delay on the previous transmission path, and when the received frame phase advances slightly like the internally generated frame phase, the total amount of delay on the transmission path becomes This is one frame length less than the previous total delay amount, which is equal to the delay amount of .

A difference occurs from the amount of delay in the l system. Therefore, a failure occurs in the 1st system and an error occurs when switching to the O system.

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal synchronization system that does not cause signal errors when switching between the active system and the standby system.

(Means for Solving the Problems) According to the present invention, the frame phase memory is used for a frame synchronization signal system in which the transmission line is duplicated into a working system and a protection system, and stores the initial frame phase of the working system. a frame synchronization circuit for detecting a frame phase in each of the signal receiving sections of the active system and the protection system; a phase comparison circuit that compares the output of the frame phase storage circuit with the frame phase of the own system; A signal synchronization method is obtained, which includes a delay circuit whose delay amount is variable and which delays and outputs a signal, and a control circuit which sets the delay amount of the delay circuit based on the output of the phase comparison circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

An embodiment of the present invention is shown in FIG. Here, the duplicated signal receiving circuits are referred to as a self system and a first system, respectively.

1 and 5 are frame synchronization circuits for the 0 system and 1 system, respectively.They receive signals with different frame phases due to the difference in propagation delay of the respective transmission paths, and synchronize the frames. Detect frame phase.

2 and 6 are frame phase comparison circuits for the 0 system and 1 system, respectively, which compare the frame phase signals of their own system output from the frame synchronization circuits 1 and 5 with the phase output from the frame phase storage circuit 9, and calculate the comparison results. are sent to control circuits 4 and 8, respectively. Housings 3 and 7 are delay circuits with variable delay amounts for the 0 and 1 systems, respectively, and control circuits 4 and 8 set the delay amounts.

The frame phase storage circuit 9 stores the delay amount of the active system at the time of system start-up, and stores and stores a value obtained by adding the delay amount of the active system transmission line to the delay amount of the delay circuit.

The delay time difference absorption at this time is schematically shown in FIG. Here, as in the case of FIG. 3, the amount of delay in the transmission path is shown by a broken line, and the amount of total delay in the delay circuit is shown by a solid line.

FIG. 4 (1) shows the state at the time of system startup, where the active system is the 0 system, and the delay amount of the delay circuit is set to be m, which is the center of the delay circuit.

The phase at this time is stored in the frame phase storage circuit 9. At this time, the delay amount of the first system, which is a standby system, is set in accordance with the output of the frame phase storage circuit 9, so that the delay amount is made to match that of the own system, which is the active system.

Further, FIG. 4 (2) shows a case where a failure subsequently occurs in the own system, which is the active system, and the first system is switched to the active system.

The delay setting at this time is as shown in Figure 4 (1).
Hold.

FIG. 4(3) shows a case where the own line is changed on the subsequent page and the delay amount of the transmission line is slightly reduced and the recovery is restored, similar to the case shown in FIG. Here, since the total delay amount of the 0 system is matched with the phase from the frame phase storage circuit 9, it becomes equal to the total delay amount in the case of FIG. 4(1).

Figure 4 (4) shows the case where a failure subsequently occurs in system 1 and the own system switches back to the active system, but the amount of delay for system 0 is (
The state of 3) is maintained, and no errors occur during switching because the delay is equal to the delay of system 1 before the failure occurred).

In order to absorb the above delay time difference, it is necessary to make the delay amount of the delay circuit sufficiently large to compensate for the difference in delay time of the transmission line when changing the line when a failure occurs. Generally speaking, this is not a major problem, except in special cases such as when switching between a satellite communication line and a satellite communication line.

〔Effect of the invention〕

As explained above, in the present invention, the initial frame phase of the working system is stored, this is compared with the frame phase of the received signal, and the delay amount of the delay circuit is set based on this. Even if the delay time of the transmission line changes due to switching between the two lines, the overall delay time can be kept the same as the initial delay time by absorbing the delay time difference between the first system and the backup system. Also during switching, there is the effect of suppressing the occurrence of signal errors caused by the delay time difference between the two systems.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. Fig. 2 is a block diagram showing the configuration of the conventional method, Fig. 3 is a schematic diagram showing the state of delay time setting when a signal error occurs in the conventional method, and Fig. 4 is a diagram showing the delay time difference absorption in the present invention. It is a schematic diagram showing the situation. In FIG. 1, 1 and 5...7 frame synchronization circuits, 2 and 6...phase comparison circuits, 3 and 7...delay circuits, 4 and 8...control circuits, 9...frame phase storage circuit. Click on the buttons 10 and 14 in Figure 2...frame synchronization circuit, 11 and 15...
...Frame phase comparison circuit, 12 and 16...Delay circuit, 13 and 17...Control circuit. Figure 1 Series Italy - Ikkake --- Shizu - Misakiri'' Figure 2 Figure 3

Claims (1)

[Claims] 1. Used in a frame synchronization signal system in which the transmission path is duplicated into a working system and a protection system, and having a frame phase storage circuit for storing the initial frame phase of the working system, and a signal receiving unit for the working system and the protection system. a frame synchronization circuit that detects each frame phase, and a phase comparison circuit that compares the output of the frame phase storage circuit with the frame phase of its own system;
A signal synchronization method comprising: a variable delay circuit that delays and outputs a received signal; and a control circuit that sets the delay amount of the delay circuit based on the output of the phase comparison circuit.