JPS62204641A - Peripheral equipment for communication - Google Patents

Abstract

PURPOSE:To relieve a load on a host processor by using a control signal from an external communication circuit network to set the standby mode. CONSTITUTION:When a data reception carrier detection signal line 16 from an RS 232C interface circuit 12 controlling the reception of a CMOS communication controller 9 is inactivated, the output of a NOT circuit 6 is activated and the output of a 2-input NOR circuit 2 is inactivated and a system clock supply signal line 4 is inactivated. Thus, no system clock signal is supplied into the controller 9 to set the mode into the standby mode. On the other hand, the standby mode is released by using a command from the host processor 11 to activate the standby mode release signal line 7, to activate an output of a 2-input NOR circuit 3 and to activate an output of the 2-input NOR circuit 2, thereby supplying the system clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication peripheral device, and in particular has a mode that temporarily suppresses the supply of a clock signal supplied from the outside to the inside and stops the internal operation. , relates to a communication peripheral device using 0MO8 manufacturing technology.

[Conventional technology]

Among communication peripheral devices, those manufactured using OMO8 manufacturing technology are characterized by low power consumption.

In addition, in order to keep power consumption low, products made using 0MO8 manufacturing technology internally stop the clock signal supplied from the outside during the period when the operation is stopped, and this state is called standby mode. being called.

Conventionally, although communication peripheral devices using 0MO8 manufacturing technology have a standby mode, the control method for setting it is mainly based on commands from the host processor and does not depend on factors from the external communication circuit network. It was insufficient. As a prior art, a control method has been proposed in which the system standby mode is canceled using a control signal from an external communication network.

[Problems that the invention attempts to solve]

In order to set the conventional CMUS communication controller, which is one of the communication peripheral devices, to standby mode after a series of reception operations are completed until the next reception operation is started, the host The processor needs to issue a command to set the standby mode to the CM (18 communication controller) and also needs to detect the completion of the reception operation. In other words, in the conventional technology, the host processor has to perform extra processing. First, it has the disadvantage of placing a burden on the host process, and the disadvantage of consuming power due to the delay in setting standby mode due to extra processing.

[Means for solving problems]

The communication peripheral device of the present invention is placed between a host processor and an external communication circuit network, and has a mode for temporarily suppressing the supply of an externally supplied clock signal to the inside and stopping internal operations. a circuit for detecting a control signal from the external communication circuit; and a circuit for temporarily suppressing internal supply of the clock signal from the outside and stopping the internal circuit according to the state of the control signal. have.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a detailed diagram showing the control circuit section 8, in which 1 is a two-man powered ANI) circuit, 2 and 3 are two-man powered NOR circuits, and 4 is inactive during the standby mode setting period.
System clock supply signal line to which the system clock signal is applied when mode is released; 5 is system clock generator 1
System clock signal line from 0, 6 is NOT circuit, 1
6 is a data reception carrier detection signal line from the R8232C interface circuit 12 that controls the reception operation of the CMO8 communication controller 9; 7 is a standby mode release line that is activated only when the standby mode is released by a command from the host processor 11; Signal line, 8 is host processor 1
This is a control circuit section that performs a control operation for canceling and setting a standby mode in response to a command from the CMU8 communication controller 9 to supply a system clock signal to the communication controller 9.

FIG. 2 is an example of a general system configuration for data communication using the present invention, where 9 is a 0M08 communication controller, l
O is a clock generator, 11 is a host process, 1-2
is a well-known R8232C interface circuit, 13 is an interface node between the host processor 11 and the 0M08 communication controller 9, 14 is a receive data line from the R,5232C interface circuit 12, and 15 is a BIS
This is a transmission data line to the H.232C interface circuit 12. FIG. 3 is a time chart showing the operation of FIG. 1.

In FIG. 2, the CMO8 communication controller 9 n,
When a command from the R8232C interface circuit 12 is received on the data reception carrier detection signal line 6, a standby mode is set. Further, the standby mode is canceled by receiving a command from the host processor 11 via the interface bus 13 (9).

The above operation will be described in detail with reference to FIG.

R that controls the reception operation of the CMUS communication controller 9
When the data reception carrier detection signal line 16 from the 8232C interface circuit 12 becomes inactive, the output of NOT1gl path 6 (1 active, 2 human-powered NO8 circuit 2 output inactive, 2 human-powered ANI) circuit 1 The output of the system
Clock supply signal line 4 becomes inactive. Shitakatsude, c
The system clock (M
No signal is supplied and standby mode is set.

On the other hand, standby mode can be canceled by host processor 1.
With the command from 1, the standby mode 194 elimination signal line 7 becomes active, the output of the 2-man power NOR circuit 3 becomes inactive, and the system clock signal is supplied by the 2-man power NOf(, the output of the circuit 2 becomes active). It has been done and it has been done.

Although the above embodiment describes the case of love, the data reception carrier detection signal line 1 that controls the reception operation
The standby mode can be set even in times of superstition by replacing the transmit enable icon that controls the transmit operation.

〔Effect of the invention〕

As described above, since the standby mode is set by the control signal from the external communication network, the host processor does not need to perform processes such as detecting the completion of the reception operation and setting the standby mode. It can lighten the burden.

Furthermore, compared to the host processor performing extra processing, the present invention allows standby mode to be set earlier, thereby further reducing power consumption.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a control circuit according to the present invention, FIG. 2 is a general system configuration diagram for data JP1 communication using the present invention, and FIG. 3 is a timing chart. 1...2 Human power to NL) circuit, 2...2
Human power N O) 1° circuit, 3...2 Human power N (J
1 (, circuit, 4... system clock supply signal line, 5... system clock signal line, 6
・・・・・・NOT circuit, 7・・・Standby・
Mode release signal edge, 8...-ft1lJ control circuit section, 9...0M08 communication controller, 1o.
- Clock generator, 11... Host processor, 12... 5232C interface circuit, 13... Interface bus, 14...
. . . Reception data line, 15 . . . Transmission data line, 16 . . . Data reception carrier detection signal line. Agent: Susumu Uchihara, patent attorney. 3rd stroke plow V mode setup

Claims (1)

[Claims] In a communication peripheral device that is placed between a host processor and an external communication circuit and has a mode that temporarily suppresses the supply of an externally supplied clock signal to the inside and stops internal operations, the external communication circuit A communication device characterized by having a circuit that detects a control signal from a network, and a circuit that temporarily suppresses internal supply of the clock signal from the outside and stops internal operation depending on the state of the control signal. Peripheral equipment.