JP2000293206A - Duplex pulse width output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a duplex pulse width output device which can output pulse width in spite of the timing of the switch of control right while reliability is maintained. SOLUTION: In a device, a duplex pulse width output device outputting pulse width is improved. A control side pulse width output part counting pulse width, outputting the start and the end of the pulse width based on control right and outputting the completion notice of pulse width and a waiting side pulse width output part counting the pulse width and outputting the start and the end of the pulse width based on the control right and the completion notice of the control side pulse width output part are installed. The pulse width is outputted by the start and the end of pulse width.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual pulse width output device for outputting a pulse width, and more particularly to a dual pulse width output device capable of outputting a pulse width irrespective of a control right switching timing while maintaining reliability. It is about.

[0002]

2. Description of the Related Art In a process control device or the like, a pulse width output of two contacts is performed to control an operation direction (opening / closing of a valve) and an operation amount of an electric valve or the like. Such a dual pulse width output device is shown in FIG. 10 and will be described below.

In the figure, reference numerals 1 and 2 denote a host processor,
Reference numerals 3 and 4 denote I / O bus interfaces, and reference numeral 5 denotes an I / O card. The host processor 1 is connected to the I / O bus interface 3, and the I / O bus interface 3
/ O card 5 The host processor 2 is an I / O
The I / O bus interface 4 is connected to an I / O card 5. The I / O card outputs a contact to a motor-operated valve or the like (not shown).

[0004] The operation of such a device will be described below.
11 and 12 are timing charts showing the operation of the device shown in FIG. FIG. 11 shows a case where the host processor 2 on the standby side does not count the pulse width.
Is a case where the host processor 2 on the standby side counts the pulse width.

The host processors 1, 2 and the I / O bus interfaces 3, 4 are duplicated and operate. Then, the host processor 1 on the control side counts the pulse width, controls the contact output circuit of the I / O card 5 via the I / O bus interface 3 by the start and end of the pulse width, A desired pulse width is output.

First, a case where the host processor 2 on the standby side does not count the pulse width will be described. FIG.
As shown in FIG. 1 (a), the counting of the pulse width is started at t1, and since the host processor 2 on the standby side does not count the pulse width, the control right is switched during the output of the pulse width at t2. The pulse width ends at t2, and the pulse width output cannot be continued until t4, which is the true end point.

Further, as shown in FIG.
After the counting is started at 1 and the control right is switched at t2, the host processor 2 which has newly become the control side
When the pulse width counting is executed again, the pulse width becomes t5.
Counting, and the output pulse width becomes long.

Therefore, as shown in FIG. 12, when the standby host processor 2 starts counting the pulse width at the same time as the control host processor 1 at t1,
Because there is an error in the operation clock on the control side and standby side,
When the operation clock of the host processor 2 on the standby side is fast, as shown in FIG. 12C, the counting of the pulse width ends at t2 before the control right is switched. For this reason, as shown in FIGS. 12A and 12B, since the operation for lowering the pulse output cannot be executed after the switching of the control right after t2, the pulse width end time t is reached.
In No. 3, there was a problem that the pulse output could not be reduced.

Therefore, an apparatus for providing a pulse width counting function from the host processor to the I / O card and outputting a pulse width is shown in FIG. 13 and will be described below.

In the figure, 6 and 7 are host processors,
Reference numeral 8 denotes an I / O card. The host processor 6 is an I / O
The host processor 7 connects to the I / O card 8. The I / O card 8 outputs a contact to a motor-operated valve or the like (not shown).

The operation of such an apparatus will be described below.
The host processors 6 and 7 are duplicated. Then, the host processor 6 on the control side gives a pulse width output command to the I / O card 8. The I / O card 8 receiving the command counts the pulse width based on the pulse width output command, and outputs the pulse width.

However, the pulse width output function part I /
The O-card 8 has a single configuration, and has a problem that reliability is deteriorated.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to provide a dual pulse width output device capable of outputting a pulse width irrespective of the timing of switching the control right while maintaining reliability. .

[0014]

According to the present invention, there is provided a dual pulse width output device for outputting a pulse width, wherein the pulse width is counted, and a start and an end of the pulse width are output based on a control right. A control-side pulse width output unit that outputs a pulse width completion notification, and counts the pulse width, and based on the control right and a completion notification of the control-side pulse width output unit, starts and ends the pulse width. And outputs a pulse width based on the start and end of the pulse width.

According to the present invention, the control-side pulse width output section outputs the start and end of the pulse width based on the control right, and outputs the completion notification of the pulse width. Then, the standby-side pulse width output unit counts the pulse width, and outputs the start and end of the pulse width based on the control right and the completion notification of the control-side pulse width output unit.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of the present invention.

In the figure, host processors 10, 20
Are duplexed and connected to the system bus 30. I / O
The communication interfaces 40 and 50 are duplicated and connected to the system bus 30 and to the I / O communication bus 60. The I / O card 70 is a contact output unit which is connected to the I / O communication bus 60 and outputs a contact to an electric valve (not shown).

The I / O communication interfaces 40 and 50 are pulse width output units, each of which has a control right flag register 4
1, 51, completion notification registers 42 and 52, command registers 43 and 53, pulse width calculation units 44 and 54, and I / O communication bus interfaces 45 and 55.

The control right flag registers 41 and 51 are control right notifying means connected to the system bus 30 and hold control right flags.

Completion notification registers 42 and 52 are completion notification means which are connected to the system bus 30, hold a completion notification flag, and notify the host processors 10 and 20.

The command registers 43 and 53 are command holding means which are connected to the system bus 30 and hold parameters of the pulse width. The command registers 43 and 53 are configured as shown in FIG. S (start bit) is
1: Command set, 0: Command completion. P
(Busy bit) specifies 1: pulse output, 0: pulse output complete. The amount of pulse width sets the time of the output pulse.

The operation of the start bit and the busy bit is performed as shown in FIG. 3, and the values of the start bit and the busy bit and the pulse output state are as shown in FIG. Here, the host is the host processor 1
0 and 20, and the I / O communication I / F indicates the I / O communication interfaces 40 and 50.

The pulse width calculation units 44 and 54 are respectively provided with control right flag registers 41 and 51 and a completion notification register 4
2, 52, which are connected to the command registers 43, 53, count based on the pulse width amounts of the command registers 43, 53, and output the start and end of the pulse width.

I / O communication bus interfaces 45 and 5
Reference numeral 5 denotes an output unit which is a control right flag register 41, 5 respectively.
1. Connected to the pulse width calculation units 44 and 54,
O communication bus 60, control right flag register 41,
Based on the control right of 51, the outputs of the pulse width calculators 44 and 54 are passed.

The operation of such a device will be described below.
Here, the control side of the host processors 10 and 20 is the host processor 10 and the I / O communication interface 4
The control side of 0, 50 is the I / O communication interface 40
And

FIG. 5 is a flowchart showing the operation of the control host processor 10. FIG. 6 shows the control I / O
5 is a flowchart showing the operation of the O communication interface 40. FIG. 7 is a flowchart showing the operation of the standby-side I / O communication interface 50.

The host processor 10 sets a parameter, that is, a start bit "1", and a pulse width amount in the command register 43 on the control side, and (S11) sets a parameter, that is, a start bit, in the command register 53 on the standby side. 1 ", the pulse width amount is set (S12). Then, the host processor 10 waits for a completion notification interrupt (S13). Note that the host processor 20 on the standby side also
The same operation as that of the host processor 10 is performed, and the control operation is not performed. When the host processor 10 becomes faulty or the like, the host processor 20 operates as the control side and operates, and thus the description is omitted. Further, the host processor 10,
20 is not a characteristic part of the present invention, and the description is omitted.

The pulse width calculation unit 44 controls the start bit “1” of the command register 43 and the control right flag register 4
With the control right flag "1" of 1, the instruction to turn on the contact for outputting the pulse (start of the pulse width) is given to the I / O card 70 via the I / O communication bus interface 45 (S21). Here, the I / O communication bus interface 45 allows the output of the pulse width calculation unit 44 to pass by the control right flag “1”. Then, the pulse width calculator 44 calculates the pulse width based on the pulse width amount of the command register 43, that is, performs the counting (S22, S2).
3). Here, the counting is performed by, for example, addition calculation.

At this time, the pulse width calculation section 54 also calculates the pulse width amount of the command register 53, that is, counts, based on the start bit "1" of the command register 53 (S31, S32). Here, the pulse width calculation unit 5
4 also outputs the start of the pulse width, but the I / O communication bus interface 55 does not allow the output of the pulse width calculation unit 54 to pass due to the control flag “0” of the control flag register 51.

When the counting is completed, the pulse width calculating section 44 issues an instruction to turn off the contact (end of the pulse width) to the I / O
It is given to the I / O card 70 via the O communication bus interface 45 (S23, S24). Then, the pulse width calculator 44 clears the start bit and the busy bit of the command register 43, that is, sets them to “0” and “0” (S25). Further, the pulse width calculation unit 44 sets the completion notification register 42 to “1” and notifies the host processors 10 and 20 via the system bus 30 (S2).
6).

The host processor 10 receives this notification.
Clears the start bit and busy bit of the standby side command register 53, that is, sets them to "0", "0" (S13, S14).

At this time, the pulse width calculator 54 checks whether the start bit and the busy bit of the command register 53 have been cleared by the control right flag "0" of the control right flag register 51 (S33). If cleared, the pulse width calculation unit 54 ends the processing. If not cleared, the pulse width calculation unit 54 sets an internal timer (not shown) (S34).

Again, the pulse width calculator 54 checks whether the start bit and the busy bit of the command register 53 have been cleared (S35). If cleared
The pulse width calculator 54 ends the processing. If not cleared, the pulse width calculation unit 54 checks the control right flag register 51 (S36).

If the control right has been switched, the pulse width calculation unit 54 instructs the I / O card 70 to turn off the contact (end the pulse width) via the I / O communication bus interface 55 (S37). Here, the control right flag register 5
The control right flag of "1" becomes "1", and the I / O communication bus interface 55 passes the output of the pulse width calculation unit 54. Then, since the control right flag is "1", the pulse width calculation unit 54 clears the start bit and the busy bit of the command register 53 (S38). The pulse width calculation unit 54 sets the completion notification register 52 to “
1 ", the completion notification register 52 notifies the host processors 10 and 20 (S39), and ends the processing.

If the control right has not been switched, the pulse calculator 54 checks whether the timer has expired (S40). If the time has not elapsed, the pulse arithmetic unit 54 checks again whether the start bit and the busy bit of the command register 53 have been cleared (S3).
5) Repeat the above operation. If the time is up,
The pulse calculator 54 clears the start bit and the busy bit of the command register 53 (S41), and ends the processing.

By the start and end instructions of the pulse width from the I / O communication interfaces 40 and 50 as described above,
The I / O card 70 performs contact output.

Next, a specific operation will be described below with reference to FIGS. 8 and 9 are timing charts showing the operation of the device shown in FIG. (A) is the control side,
(B) shows a timing chart on the standby side. Note that the timing chart is a conceptual diagram and does not represent an actual signal output.

In FIG. 8, the host processor 10
A start bit, a busy bit, and a pulse width amount are set in the command registers 43 and 53 (S11).

Then, the I / O communication interface 50 on the standby side outputs the start of the pulse width at t1, counts the pulse width, ends the count at t2, and is busy with the start bit of the command register 53. It is confirmed whether the bit has been cleared (S31 to S33). And
The pulse width calculation unit 54 sets the internal timer, and repeatedly checks whether the start bit and the busy bit of the command register 53 are cleared, the control right is switched, or the time is up (S35, S36, S40).

At this time, the control-side I / O communication interface 40 counts the pulse width output from t1, ends the counting, and outputs the end of the pulse width at t3 (S21 to S24). The pulse width calculator 44 clears the start bit and busy bit of the command register 43, sets the completion notification register 42 to "1", and notifies the host processors 10 and 20 of the completion (S25, S2).
6).

Upon completion notification, the host processor 10
Clears the start bit and the busy bit of the command register 53 (S14).

Thus, the pulse width calculator 54 of the I / O communication interface 50 outputs the end of the pulse width at t3.

In FIG. 9, the host processor 1
0 sets a start bit, a busy bit, and a pulse width amount in the command registers 43 and 53 (S11).

Then, the I / O communication interface 50 on the standby side counts the pulse width from t1, and
At 2, the counting is completed, and it is confirmed whether the start bit and the busy bit of the command register 53 have been cleared (S31 to S33). Then, the pulse width calculation unit 54
An internal timer is set, and it is repeatedly checked whether the start bit and the busy bit of the command register 53 have been cleared, the control right has been switched, or the time has expired (S
35, S36, S40).

At this time, the control-side I / O communication interface 40 counts the pulse width output from t1 (S21 to S23). At t3, when the control right is switched, the control right flag register 41 is set to "0",
The control right flag register 51 becomes "1". Here, the switching of the control right is performed by the host processor 10 reading the registers 41 to 43 and, if reading fails, the I / O
Switching is performed by regarding the O communication interface 40 as a failure and setting the control right flag register 41 to "0" and setting the control right flag register 51 of the I / O communication interface 50 to "1".

As a result, at t3, the pulse width calculation unit 54
Ends the pulse width output, clears the start bit and the busy bit, and sets the completion notification register 52 to "1" (S37 to S39).

Upon completion notification, the host processor 10
Clears the start bit and the busy bit of the command register 43 (S14).

As a result, the pulse width calculator 44 of the I / O communication interface 40 on the standby side outputs
The end of the pulse width is output (S31 to S33). In addition,
Since the control right flag register 41 is "0", the I / O
No output is made by the communication bus interface 45.

As described above, the control-side I / O communication interface 40 notifies the completion of the pulse width counting, and, based on this notification, the standby-side I / O communication interface 50.
Ends the pulse width counting, so that even if the processing speeds of the I / O communication interfaces 40 and 50 are shifted, the pulse output can be continuously performed irrespective of the switching timing of the duplexing. Also, since the I / O communication interfaces 40 and 50 are duplicated,
Reliability can be maintained.

The present invention is not limited to this, but may be as follows. The pulse width calculation unit 44,
Although the configuration for controlling the output of 54 has been described, a configuration including a configuration in which the pulse width calculation units 44 and 54 control the output with the control right may be used.

The completion notification of the completion notification registers 42 and 52 is sent to the I / O via the host processors 10 and 20.
Although the configuration for notifying the communication interfaces 50 and 40 has been described, it is possible to directly
The configuration may be such that the I / O communication interfaces 50 and 40 are notified.

Then, in the host processors 10 and 20,
Although a duplicated configuration is shown, the feature of the present invention is that the I / O
Since the O communication interfaces 40 and 50 are used for redundancy, the host processors 10 and 20 may have a single configuration.

[0053]

According to the present invention, the following effects can be obtained. The control-side pulse width output unit notifies the completion of the pulse width counting, and this notification causes the standby-side pulse width output unit to end the pulse width counting. However, the pulse output can be continuously performed irrespective of the switching timing of the duplexing. Further, since the control side and standby side pulse width output units are duplicated, reliability can be maintained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of command registers 43 and 53.

FIG. 3 is a diagram showing an operation correspondence table of command registers 43 and 53;

FIG. 4 is a diagram showing a pulse output state correspondence table of command registers 43 and 53.

FIG. 5 is a flowchart showing the operation of the control-side host processor 10.

FIG. 6 is a flowchart showing the operation of the control-side I / O communication interface 40.

FIG. 7 is a flowchart showing an operation of the standby-side I / O communication interface 50;

FIG. 8 is a timing chart showing the operation of the device shown in FIG.

FIG. 9 is a timing chart showing the operation of the device shown in FIG.

FIG. 10 is a configuration diagram showing a conventional duplex pulse width output device.

11 is a timing chart showing the operation of the device shown in FIG.

12 is a timing chart showing the operation of the device shown in FIG.

FIG. 13 is a configuration diagram showing another conventional duplex pulse width output device.

[Explanation of symbols]

 10, 20 Host processor 30 System bus 40, 50 I / O communication interface 41, 51 Control right flag register 42, 52 Completion notification register 43, 53 Command register 44, 54 Pulse width calculation unit 45, 55 I / O communication bus interface 60 I / O communication bus 70 I / O card

Claims (5)

[Claims] 1. A dual pulse width output device for outputting a pulse width, wherein the pulse width is counted, a start and an end of the pulse width are output based on a control right, and a completion notification of the pulse width is output. A control-side pulse width output unit, a standby-side pulse width output that counts the pulse width, and outputs a start and end of the pulse width based on the control right and a completion notification of the control-side pulse width output unit. Part and
A duplex pulse width output device which outputs a pulse width at the start and end of the pulse width. 2. The control-side and standby-side pulse width output units include: a control right notification unit that notifies a control right; a completion notification unit that notifies a completion notification of a pulse width; and a pulse width amount of the pulse width. A command holding means for counting the pulse width based on the pulse width of the command holding means, and outputting the start and end of the pulse width when the control right is given from the control right notifying means; 2. The duplex pulse according to claim 1, further comprising: a pulse width calculation unit that terminates counting of a pulse width based on a completion notification from the completion notification unit on the control side when there is no control right from the notification unit. Width output device. 3. The control-side and standby-side pulse width output units each have an output unit that outputs an output of the pulse width calculation unit based on a control right from a control right notification unit. A dual pulse width output device as described. 4. The duplex pulse width output device according to claim 1, further comprising a host processor for notifying the standby pulse width output unit of the completion notification of the control side pulse width output unit. 5. The dual pulse output according to claim 1, further comprising a contact output section for performing a contact output based on the start and end of the pulse width of the control-side and standby-side pulse width output sections. apparatus.