JPS54136144A - Shared input/output bus control unit - Google Patents
Shared input/output bus control unitInfo
- Publication number
- JPS54136144A JPS54136144A JP4315878A JP4315878A JPS54136144A JP S54136144 A JPS54136144 A JP S54136144A JP 4315878 A JP4315878 A JP 4315878A JP 4315878 A JP4315878 A JP 4315878A JP S54136144 A JPS54136144 A JP S54136144A
- Authority
- JP
- Japan
- Prior art keywords
- boat
- processor
- input
- signals
- output bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To ensure the monitor or the abnormal switching process for the processor in place of the normal processor by securing the function which monitors the process request given to the processor from the input/output device as well as the time required for the process of the processor.
CONSTITUTION: Boat 11c and 11d to be connected to input/output device 9i and different procesors are connected to shared input/output bus 7d. Shared input/output bus control unit 6d receives various kinds of request signals sent from device 9i as well as the data transfer signals from the processor at reception circuits 12W14, with time monitor circuits 15W17 provided at the rear step of device 9i. As the various kinds of signals are turned on and off with every data word, the fault is decided in case these signals are kept on for a fixed time. The output of circuits 15W17 reach boat 11c and 11d via boat selection setter 18 and boat selection signal sending circuit 19. In this contitution, in case the procesor connected with boat 11d, for example, becomes down, boat selection signal 20a is cut off. And with arrival of the connection command, selection signal 20b is transmitted to start the process through the normal processor.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53043158A JPS6023382B2 (en) | 1978-04-14 | 1978-04-14 | Shared I/O bus controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53043158A JPS6023382B2 (en) | 1978-04-14 | 1978-04-14 | Shared I/O bus controller |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54136144A true JPS54136144A (en) | 1979-10-23 |
JPS6023382B2 JPS6023382B2 (en) | 1985-06-07 |
Family
ID=12656047
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53043158A Expired JPS6023382B2 (en) | 1978-04-14 | 1978-04-14 | Shared I/O bus controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6023382B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5679345A (en) * | 1979-11-30 | 1981-06-29 | Hitachi Ltd | Fault detection system of compound type arithmetic device |
JPS60158360U (en) * | 1984-03-29 | 1985-10-22 | 東芝ライテック株式会社 | transmission device |
JPS60249453A (en) * | 1984-05-25 | 1985-12-10 | Yokogawa Hokushin Electric Corp | Data transmission system |
JPS61173368A (en) * | 1985-01-28 | 1986-08-05 | Oki Electric Ind Co Ltd | Access system for shared memory device |
-
1978
- 1978-04-14 JP JP53043158A patent/JPS6023382B2/en not_active Expired
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5679345A (en) * | 1979-11-30 | 1981-06-29 | Hitachi Ltd | Fault detection system of compound type arithmetic device |
JPS60158360U (en) * | 1984-03-29 | 1985-10-22 | 東芝ライテック株式会社 | transmission device |
JPS60249453A (en) * | 1984-05-25 | 1985-12-10 | Yokogawa Hokushin Electric Corp | Data transmission system |
JPS61173368A (en) * | 1985-01-28 | 1986-08-05 | Oki Electric Ind Co Ltd | Access system for shared memory device |
Also Published As
Publication number | Publication date |
---|---|
JPS6023382B2 (en) | 1985-06-07 |
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