JPS63157238A - Computer - Google Patents

Abstract

PURPOSE:To shorten the processing time of a computer by holding a CPU when an exclusive LSI processes an instruction and releasing the holding state of the CPU to apply an interruption to the CPU if an instruction processing request is given to the CPU from the exclusive LSI. CONSTITUTION:A CPU 11 sends a start command to an exclusive LSI 15 for start of processing of a user program. Thus the LSI 15 sends a holding request to the CPU 11. The CPU 11 receives the holding signal and is set under a holding state. Thus the CPU 11 is cut off from a bus 4 and the LSI 15 that supplied a holding status signal is started by the timing BB. Then the reading of an instruction is started in the first step of the user program.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Application in Business Field) The present invention relates to a computer in which each instruction of a program is shared and processed by an arithmetic processing unit and its peripheral devices.

[Conventional technology]

Generally, as an example of a computer, it exchanges information with an external device, processes the information input from the external device, and
A programmable controller system that outputs the arithmetic processing information to external equipment is being considered. Conventionally, this type of programmable controller system inputs and outputs an arithmetic processing program (hereinafter referred to as a user program) from a program loader to a programmable controller that performs arithmetic processing.

FIG. 4 shows an example of a schematic configuration of a conventional programmable controller.

In Fig. 4, 1 is arithmetic processing (CPU);
The UI executes a user program input by the user from a program loader (not shown). 2 is a system program memory, and the system program 2 includes CPt1l.
Contains system programs necessary for the system to run user programs.

3 is a system work memory, and variables used when CPIJI executes a system program are stored in the system work memory 3. 5 is a dedicated LS such as a DMA (direct memory access) controller, etc.
I (Large Scale Inch Grated Circuit), and the dedicated LSI 5 executes predetermined instructions of a user program executed by the CPU, for example, reading information from the user data memory 7, in place of the CPU I.

6 is a user program memory, and the user program memory 6 stores the program input from the loader. 7 is a user data memory. 9 is a bus switching circuit, and in the bus switching circuit 9, the dedicated LSI 5 is connected to the bus 8.
When using the CPU, bus 4 and bus 8 connected to the CPU are cut off. 10 is an interrupt signal, and the interrupt signal 10 causes the CPt1l to stop and the dedicated LSI 5 to operate.

In such programmable controllers, in order to speed up the processing speed of user programs,
Operation monitoring of the entire programmable controller and highly functional instructions among the user program instructions, such as instructions related to logical operations and numerical operations, and user program auxiliary instructions provided to manage the user's program (for example, extremely long instructions) In a program, the CPU 1 is in charge of processing "page commands" etc. that are stored here and there in order to clearly demarcate the program.

Then, read program commands and data, etc. [:P
When executed by Ul, the processing speed is slow, so a dedicated LSI is used.
5 is in charge of the above-mentioned processing to speed up user program calculations.

However, in the conventional example, while the LSI5 is operating, the CP
[Since Il is inactive, there is a problem in that idle time is wasted for arithmetic processing. This point will be explained in detail.

FIG. 5 shows an example of the contents stored in the program memory 6.

The program input from the loader is stored in the program memory 6 by the CPU in accordance with the system program.

In FIG. 5, program step 1 is an operation code of a user program auxiliary instruction processed by the CPUI. Program step 2.3 stores operands containing numerical values and the like that support the instruction operation code.

The program steps 1 to 3 are system instructions for executing the user program. Program steps 4 to 6 and 10 are bit instructions 1 to 4 processed by the dedicated LSI 5, and are, for example, read addresses.

Program steps 7-9, l! ~13 are each CP
This is the above-mentioned relatively high-performance instruction in the user program that is processed by the UI, and is composed of an operation code and an operand part.

Next, the operation of the conventional example will be explained with reference to FIGS. 6 and 7.

In FIG. 6, in order to start processing the user program, (:PUl first sends a startup command to the dedicated LSI 5 via the system bus 4.8. The reading of the first step instruction is started.

At timing A shown in FIG. 6, the dedicated LSI 5 reads the instruction of program step 1 shown in FIG. 5 and determines whether the instruction should be processed by the dedicated LSI. Since the first step command is negative, the dedicated LSI 5 sends a processing request interrupt to the CPUI.

The old CP that has accepted the interrupt starts executing the instruction processing program shown in FIG. After cput determines the type of interrupt at timing B shown in FIG. 6, it performs interrupt-related processing (step 51), such as countering a predetermined instruction processing program.
After performing this, the contents of the user program counter in the dedicated LSI 5 are read.

Then, it is determined whether the instruction (in this case, word instruction 1 user program auxiliary instruction) that the dedicated LSI 5 has requested to process is in the ρ step of the user program (step S2), and the corresponding instruction is read from the user program memory 6 (step S2). S3), and processes the corresponding command (step S4).

Next, the contents of the user program counter (not shown) in the dedicated LSI 5 are rewritten to the program step where the next instruction (in this case, the instruction of program step 4) after the instruction processed by the CPt1l exists (step 55)1, and then , sends a startup command to the dedicated LSI 5 (step S6
).

When the processing shown in FIG. 7 is executed, the dedicated LSI 5
restarts, and after processing the instructions in program steps 4 and 5.6 shown in FIG. 5 at timing C shown in FIG. An interrupt processing request is output to the CPU again.

At timing D, the CPIII executes the control process shown in FIG. 7 described above and outputs a start command to the dedicated LSI 5 again.

By repeating the above procedure, each instruction of the user program is processed.

(Problem to be Solved by the Invention) In such a conventional user program processing system, a processing request for a CPU IA filling instruction is notified by an interrupt signal IO sent from the LSI 5, so the interrupt-related processing shown in FIG. It is necessary to perform step Sl).Also, when restarting the dedicated LSI 5,
It is also necessary to write the program step value of the instruction whose processing is to be started into the program counter (step S5).

Furthermore, since the user program auxiliary commands, which do not need to be processed when executing the user program, are requested to be processed by Crtll as CPUI processing commands,
The CPUI needs to perform unnecessary processing.

The above-mentioned processing is essentially unnecessary for user program processing, and there is a problem in that it is a major hindrance to solving the user's request to speed up user program processing.

Therefore. The purpose of the present invention is to solve these problems,
An object of the present invention is to provide a computer that can further increase the processing speed of programs.

[Means for solving problems]

To achieve this object, the present invention provides storage means for storing program instructions, address indicating means for indicating the address of the program instruction to be read in the memory means, and a first signal generating means for generating an activation signal. means and
A second generator that generates a hold signal when the activation signal occurs.
a first reading means that starts reading a program instruction from a designated address in response to a signal generating means and a start signal; If the read program instruction is the first instruction as a result of the identification by the identification means, the first instruction is processed and the specified address is transferred to the next instruction. the first processing means instructs the first reading means to read the program instruction by updating it to the address of a third signal generation means for generating a signal; a stop means for rewriting the designated address to the next address after the hold release signal is generated; and a stop means for stopping the reading operation of the first reading means; and an identification means. As a result of the identification, if the read program instruction is the third instruction, the first instruction means rewrites the indicated address to the next address and instructs the first reading means to read the program instruction. and a second reading means for reading the program instruction at the address specified by the address instruction means from the first storage means when the hold release signal is generated; a second processing means that enters a hold state when the second command is processed by the second processing means; and a second instruction that instructs the first signal generation means to generate a start signal when the second command is processed by the second processing means. It is characterized by having the means.

(Operation) According to the present invention, the first instruction in the program stored in the storage means is processed by the first processing means, and the second instruction is processed by the second processing means. When it is determined by the identification means, the first instruction means is set to advance the read address of the program. The second processing means enters a hold state, and the first processing means executes the first command.Furthermore, when the identification means identifies that the program command is the second command, the first processing means stops; The second processing means is activated by the hold release signal generated when the hold release signal is generated. Then, when the second processing means finishes processing the second command, an activation signal is generated, and this activation signal causes the first
Since the first and second processing means are activated, the first and second processing means can perform processing alternately. Therefore, system command processing related to program processing can be deleted.
Program processing time is reduced.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an example of a configuration in an embodiment of the present invention. Note that the same parts as in FIG. 4 are given the same reference numerals.

In FIG. 1, 11 is a CPI as a second processing means.
CPU II is in charge of monitoring the entire controller and processing highly functional commands among the commands of the user program. 15 is a dedicated LSI as a first processing means, and the dedicated LS 115 processes relatively simpler user program instructions than the CPU 11, and detects the operand part of the user program auxiliary instructions and CPU 1 processing instructions. At this time, the user program counter is advanced.

4 is a system bus for exchanging data.

18 is a signal line, and signal line 1B sends a hold request output signal to the dedicated LS 11 when processing a user program.
5 to CPU II. Hold signal is CPU
11, the connection between CPIII and bus 4 is held (temporarily cut off). 19 is a signal line, and a hold status signal, that is, CP
The dedicated LS1151 indicates that t1ll is in the hold state.
．． : A notification signal is transferred from the CPU II to the dedicated LS 115.

The operation of the embodiment of the present invention will be explained with reference to FIGS. 2 and 3.

In FIG. 3A, in order to start processing the user program, the CPU II first sends a startup command to the dedicated LS 115 via the system bus 4 at timing ^A shown in the second diagram. The dedicated LS115 starts cp due to the startup command.
A hold request is output to the unit via the signal line 18 (step 5llNS12).

The CPU II receives this hold signal, enters a hold state, and outputs a hold status signal indicating that the hold signal has been confirmed.

At this stage (: PUll and bus 4 are cut off, and the dedicated LS inputs the hold status signal at timing BB).
115 is activated and starts reading out the instructions of the first step of the user program (steps 313 to S14).
. As a result of reading the instruction of program step 1 shown in FIG. 5, since this instruction is a user program auxiliary instruction, the dedicated LS 115 increments the user program counter by 1 and starts reading the next instruction (program step 2) ( Step S15→518→S17→Sll→
514).

Since the next instruction is the operand part of the user program auxiliary instruction, the user program counter is incremented by 1 and the next instruction (program step 3) is read out in the same manner as the above procedure. Since this is also an operand portion, the dedicated LS 115 further adds 1 to the user program counter, reads the next instruction (program step 4), and executes the necessary processing. Similarly, after executing program step 5.6 shown in FIG.
When the CPU processing command is read out, the dedicated LS 115 drops the hold request that has been sent at timing CC, releases the hold state of CPIII, and stops (step 51B-S19-319').

At this point, the user program counter in dedicated LS 115 is incremented by one and points to program step eight. When the hold is released, the CPU II determines that an instruction processing request has been issued, and starts executing the instruction processing program shown in FIG. 3(B).

Figure 3 (B) km, CPUII is dedicated LS11
The content of the user program counter in FIG. 5 is read, and it is determined in which step of the user program the instruction (word instruction 2 shown in FIG. 5) that the dedicated LS 115 has requested to process is located. (Step 521), the corresponding instruction is read from the user program memory 6 (Step 522), and the corresponding instruction is processed (Step 523). Next, send a start command to the dedicated LS115 (
Step 524) Then, the control procedure of FIG. 3(A) is started.

The dedicated LS 115 restarted after executing the processing of steps S11 to S17 starts reading the instruction of user program step 8 since the program counter points to step 8. The command for program step 8 is step 7
Since this is the operand part of the word instruction, the dedicated LS 115 is
adds 1 to the user program counter and executes the next instruction (
Since this is also an operand portion, the dedicated LSI 15 further adds 1 to the user program counter, reads the next instruction (program step 10), and executes the necessary processing.

By repeating the above steps, each instruction of the user program is processed. This user program processing method reduces interrupt processing time, CPU processing time for user program auxiliary instructions, and processing time for the CPU to write restart program steps to the dedicated LSI when restarting the dedicated LSI. etc., thereby reducing the processing time of the user program.

〔Effect of the invention〕

As described above, according to the present invention, when the dedicated LSI processes an instruction, the CPU is set in a hold state by a hold signal, and when a user program is executed, the dedicated LSI issues an instruction processing request to the CPU. Since the CPU is released from hold by dropping the notification hold request signal, it is possible to eliminate the interrupt processing time required in the conventional system.

Furthermore, when executing a user program on the dedicated LSI, the CPU IA processing of the auxiliary instructions can be eliminated by advancing only the program step of the user program auxiliary instructions that do not originally need to be processed. Furthermore, by advancing the program step when the CPU reads the operand part of the instruction that it is responsible for processing, the restart program step that was necessary when the CPU restarts the dedicated LSI can be written to the dedicated LSI. Processing can be deleted. By deleting each of the above processes, it is possible to obtain the effect that the user program processing time can be significantly shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the main configuration of a programmable controller in an embodiment of the present invention, FIG. 2 is a timing chart showing an example of the operation timing of the embodiment of the present invention, and FIGS. 3(A) and (B) are A flowchart showing an example of a control procedure in an embodiment of the present invention, FIG. 4 is a block diagram showing an example of the main configuration of a conventional programmable controller, and FIG. 5 shows an example of a user program stored in the memory 6 in the conventional example. FIG. 6 is a timing chart showing an example of operation timing in the conventional example, and FIG. 7 is a flowchart showing an example of a control procedure in the conventional example. 1.11...CPt1. 2.3,6. F...Memory, 4.8...Path, 5.15...Dedicated LSI, 9...Switching circuit, 1G, 18.19...Signal line. ,I＞Zeimei tsukatun I row 0 block diagram FIG. 1 Block diagram of A row A block diagram FIG. 4 Block diagram of A row A block diagram 60 years old Grass floor A row 0 flow hand yard Figure 7

Claims (1)

[Scope of Claims] Storage means for storing program instructions; address instruction means for specifying the address of the program instruction to be read in the storage means; first signal generation means for generating an activation signal; second signal generating means for generating a hold signal when generated; first reading means for starting reading of the program instruction from the indicated address in response to the start signal; and the read program instruction. an identification means for identifying whether the read program instruction is a first instruction, a second instruction, or a third instruction; and when the read program instruction is the first instruction as a result of identification by the identification means; a first processing means for processing the first instruction, updating the instructed address to the next address and instructing the first reading means to read the program instruction; and the identification means. as a result of the identification, when the read program instruction is the second instruction, a third signal generating means for generating a hold release signal; and after the hold release signal is generated, the commanded address is stopping means for rewriting to the next address and stopping the reading operation of the first reading means; and when the read program instruction is a third instruction as a result of identification by the identification means, the instruction a first instruction means for instructing the first reading means to rewrite the specified address to the next address and read the program instruction; a second reading means for reading a program instruction at a read address from the first storage means; a second processing means for processing the read second instruction and entering a hold state when the hold signal is generated; and second instruction means for instructing the first signal generation means to generate the activation signal when the second command is processed by the second processing means. Computer.