JP2001265468A - Reset system for substrate and processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently rewrite and execute a program such as firmware on an I/O board without stopping or restarting a host. SOLUTION: When either an I/O bus reset signal 17 of a host computer or a reset signal 18 outputted by a reset circuit 13 on an I/O board is made valid, an I/O processor is reset. The reset circuit 13 outputs the reset signal 18 in a fixed time according to an instruction from the I/O processor. At the time of rewriting firmware, the I/O processor 11 outputs a reset request to the reset circuit 13 after the completion of the rewriting of the firmware, and the reset circuit 13 outputs the reset signal in a certain fixed time. Thus, it is possible to reset the I/O processor 11 without restarting a host, and to execute new firmware after the reset is released by the reset circuit 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a board on which electronic equipment capable of rewriting program data and function setting data in an electrically writable and erasable memory is mounted, and a processor provided on the board. Related to the reset method.

[0002]

2. Description of the Related Art FIG. 4 shows a block diagram of a conventional hardware configuration. An I / O (Input / Output) processor 41 that operates by reading firmware in a nonvolatile memory such as a flash memory 42
When replacing a program such as firmware upgrade in the / O board 45, it is necessary to restart the host after rewriting the firmware even in a system where online writing is possible.

When the power supply of the host is turned on / off or the host is reset, the I / O bus is reset via an I / O bus reset signal 47.
The board is also reset, the I / O processor is reset, and the new firmware can be read and operated. As another method, there is a method in which a restart process is performed by firmware so that the reset is not used and the firmware is operated with rewritten firmware.

[0004]

As described above, in the conventional method, after replacing the firmware, it is necessary to restart the host in order to operate with the new firmware. Also, an I / O processor or other LSI (Large Scale Integral) that has no reset terminal and is reset only by turning on / off the power supply
If there is a ted circuit, the host must be powered off once. To do so, it is necessary to stop all programs such as applications running on the host. Therefore, the firmware could not be rewritten on the I / O board mounted on the system that operates continuously for 24 hours and 365 days.

In addition, even if the system is not a continuous operation system, it is necessary to restart the host after rewriting the firmware, and it takes time and effort to stop and restart the OS (Operating System) and applications, resulting in low efficiency. There was a problem.

On the other hand, in the restart processing by the firmware, internal registers and the like may not be completely initialized because the I / O processor is not reset. In addition, a program for restarting must be incorporated in the firmware, which causes problems such as an increase in program size and an increase in program development effort.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to efficiently rewrite and execute a program such as firmware on an I / O board without stopping and restarting a host. I do.

[0008]

A substrate according to the present invention comprises:
In a board including a processor that executes instructions constituting a program, the processor outputs a reset request signal requesting a reset of the processor itself, and the board inputs a reset request signal output from the processor, And a reset circuit for outputting a processor reset signal for instructing resetting.

The reset circuit outputs a substrate reset signal for instructing a reset of the substrate.

[0010] The substrate further includes a non-volatile memory for storing a program including firmware, and the processor reads the program from the non-volatile memory and executes instructions composing the program.
Outputting the reset request signal when the nonvolatile memory is rewritten.

The board is mounted on a computer, and the processor reset signal instructs a reset of a processor provided on the board without resetting the computer.

[0012] The substrate further includes a power control circuit for controlling power supplied to the processor, the reset circuit outputs a processor reset signal to the power control circuit, and the power control circuit outputs the input processor reset signal. The processor is reset by interrupting power supplied to the processor based on the signal.

[0013] A processor reset method according to the present invention is provided in a board, and is a processor reset method for restarting a processor that executes an instruction composing a program, wherein the processor includes a reset signal for instructing reset of the processor itself. And a reset circuit for receiving a reset signal output from the processor and instructing a reset of the processor.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a hardware block diagram of one embodiment of the present invention. In FIG. 1, an I / O board (substrate) 15 is mounted on an I / O bus 16 of a host. An I / O processor (processor) 11 is provided on the I / O board 15, and the I / O processor 11 reads firmware in the flash memory 12 and executes a program instruction. The I / O processor 11 is reset by a reset signal, and after the reset, starts executing from a certain fixed address in the flash memory.

The host I / O bus reset signal 17 is
The logic circuit 14 is interposed without being directly connected to the I / O processor 11. The logic circuit 14 receives the reset signal 1 from the host I / O bus reset signal or the reset circuit 13.
8 is a logic circuit that outputs a reset when either of them becomes valid. The reset circuit 13 outputs a reset signal 18 for a certain period according to an instruction from the I / O processor. Therefore, the I / O processor 11 sends the I / O
The reset is performed when either the / O bus reset signal 17 or the reset signal from the reset circuit 13 on the I / O board or both become valid.

In this embodiment, the reset circuit 13
Outputs a reset signal to the processor. The reset signal includes a processor reset signal for instructing a reset of the processor and a board reset signal for resetting the entire I / O board (board). In the following description, the processor reset signal and the substrate reset signal will be described as “reset signals” without distinction. As described above, in this embodiment, as an example of the substrate, I
An I / O board is used as an example of a processor using an I / O board.
A description will be given using a processor. Similarly, in the following embodiments, an I / O board and an I / O processor will be described as examples.

Next, the operation at the time of rewriting the firmware will be described. Normally, the I / O processor 11 reads and executes firmware in the flash memory 12. When rewriting the firmware, the host temporarily suspends the use of the I / O board 15. The contents of the flash memory 12 are rewritten online from a host or an external port prepared on the I / O board 15. After rewriting is completed, the I / O processor 11 issues a reset request (reset request signal) to the reset circuit 13. This reset request may be issued by the host instructing the I / O processor 11 to make a request, or the I / O processor 11 itself may determine and request the completion of rewriting of the firmware.

In response to a reset request from the I / O processor 11, the reset circuit 13 outputs a reset signal 18 for a certain period of time, and the I / O processor 11 is reset.
After a certain period of time, when the reset is released (reset completed) by the reset circuit 13, the I / O processor is started up, and the firmware in the flash memory is newly read and executed, whereby the operation is performed with the new firmware.

After the I / O board 15 starts up, the host resumes using the I / O board 15. During the reset of the I / O board 15, the I / O board
The output pin of the processor 11 is set to a high impedance state so as not to affect the I / O bus 16 of the host.

As described above, according to the present invention, 2
I / O mounted on the system for continuous operation for 4 hours 365 days
Even in the case of a board, it is possible to upgrade firmware and the like without stopping the host computer. Since it is not necessary to restart the host even if the system is not a continuous operation system, cost and time can be saved, and the work efficiency of firmware rewriting can be improved. Also, during the development / debugging of the I / O board, rewriting of firmware and the like frequently occurs. However, in the conventional method, it is necessary to re-start the host after rewriting even a small program change, which takes time. Although the efficiency is reduced, the method saves time because the host does not need to be restarted, thereby enabling efficient development.

Further, in the conventional restart processing by the firmware, registers and the like in the I / O processor may not be initialized. However, in this method, since a reset is performed by hardware, the I / O processor also needs to be initialized. It can be completely initialized. In this method, since a restart program is not required, the firmware program can be simplified. Further, since the I / O processor directly controls the reset circuit, a special circuit such as a watchdog circuit other than the reset circuit is not required, and mounting can be performed with a small number of components.

As described above, this I / O board (substrate)
And a method of resetting the processor, wherein the I / O board mounted on the host computer includes a reset circuit as a device that can be reset by an instruction from the I / O processor, and does not affect the host during the reset of the I / O board. The I / O board can be restarted by resetting an instruction from the I / O processor without restarting the host computer after rewriting firmware or the like.

Embodiment 2 FIG. FIG. 2 shows an embodiment in which the I / O processor 21 has no reset terminal and is reset only when the power is turned on. In the figure, an I / O board (substrate) 25 is mounted on an I / O bus 26 of a host. An I / O processor 21 is provided on the I / O board 25, and the I / O processor (processor) 21 reads firmware in the flash memory 22 and operates. The I / O processor 21 is reset when the power is turned on. After the reset, the I / O processor 21 starts executing from a certain fixed address in the flash memory 22. The reset circuit 23 outputs a reset for a certain period according to an instruction from the I / O processor 21. The reset signal 28 of the reset circuit 23 is input to the power supply control circuit 24. The power supply of the I / O processor 21 is not directly connected to the power supply on the board, but to the power output of the power control circuit 24.

Flash memory 22, reset circuit 23
Other than the I / O processor 21, the power supply 27 on the board
Directly connected to The power supply control circuit 24 cuts off the power supply while the reset signal 28 from the reset circuit 23 is valid, and does not supply power to the I / O processor 21. Therefore, during reset by the reset circuit 23 on the I / O board 25, the I / O processor 21 is turned off.

Next, the operation at the time of rewriting the firmware will be described. Normally, the I / O processor 21 reads and executes firmware in the flash memory 22. When rewriting firmware, first, the host temporarily suspends use of this I / O board. The contents of the flash memory 22 are rewritten online from a host or an external port prepared on the I / O board 25.

After rewriting is completed, the I / O processor 21
Issues a reset request to the reset circuit 23. This request may be made by the host instructing the I / O processor 21 to make a request, or the I / O processor 21 itself may make the request after judging that the rewriting of the firmware has been completed. I / O
In response to a reset request from the processor 21, the reset circuit 23 outputs a reset signal for a certain period of time, and the power supply control circuit stops power supply to the I / O processor 21.

After a predetermined time, when the reset is released by the reset circuit 23, the power supply control circuit supplies power to the I / O processor 21 and the I / O processor 21 is activated. The I / O processor 21 operates by using the new firmware by reading and executing the firmware in the flash memory. After the I / O board 25 starts up, the host resumes using the I / O board 25. During the reset of the I / O board 25, the I / O bus 26 of the host is not affected.

As described above, by controlling the power supply of the I / O processor in this manner, it is possible to use the I / O processor which has no reset terminal and is reset only when the power supply is turned on. No cost and time savings.

As described above, in the board and processor reset method of this embodiment, the I / O board 25 includes the power supply control circuit 24 for controlling the power supplied to the processor (I / O processor 21). The reset circuit 23
A reset signal is output to the power supply control circuit 24, and the power supply control circuit 24 resets the processor by interrupting power supplied to the processor 21 based on the input reset signal.

Embodiment 3 FIG. 3 shows an FPGA (field programmable gate array) that performs configuration using program data in a flash memory.
This is an embodiment in which the present invention is applied to an I / O board equipped with a. In the figure, an I / O board 35 is mounted on an I / O bus 36 of a host. The FPGA 39 is on the I / O board 35. The FPGA 39 reads data from the flash memory 32 when the power is turned on and performs configuration.

Further, an I / O processor 31 is provided on the I / O board 35. The reset circuit 33 outputs a reset for a certain period according to an instruction from the I / O processor 31. The reset signal 38 of the reset circuit is input to the power supply control circuit 34.

The power supply of the FPGA 39 is not directly connected to the power supply 37 on the board, but to the power supply output of the power supply control circuit 34. The I / O processor 31, the flash memory 32, the reset circuit 33, and the like are directly connected to a power supply on the board. The power control circuit 34 shuts off the power while the reset signal 38 from the reset circuit 33 is valid,
The power is not supplied to the GA 39. Therefore, I /
During reset by the reset circuit 33 on the O board 35,
The FPGA 39 is turned off.

Next, the operation of the FPGA 39 when rewriting the program data will be described. Normally, FPGA39
Reads the program data in the flash memory 32 when the power is turned on and performs the configuration. FPG
When rewriting the program data of A39, first, the host temporarily suspends use of the I / O board 35. The contents of the flash memory 32 are rewritten online from a host or an external port prepared on the I / O board 35.

After rewriting, the I / O processor 31
Issues a reset request to the reset circuit 33. This request may be made by the host instructing and requesting the I / O processor 31, or the I / O processor 31 itself may determine and request the completion of rewriting of the program data. The reset circuit 33 outputs a reset signal for a certain period of time, and the power supply control circuit 34 stops supplying power to the FPGA 39.

After a predetermined period of time, when the reset is released by the reset circuit 33, the power supply control circuit 34 supplies power to the FPGA, the FPGA 39 is started, and the program data in the flash memory 32 is read to perform the configuration. , Operation with new program data. After the I / O board 35 starts up, the host resumes using the I / O board 35. Note that I
While the I / O board 35 is being reset, the host I / O bus 3
6 is not affected.

As described above, by controlling the power supply of the FPGA in this manner, it can be used even when the configuration of the FPGA is redone, and it is not necessary to restart the host, so that cost and time can be saved.

[0038]

According to the board and processor reset method of the present invention, firmware or the like can be upgraded without stopping the host computer on which the board is mounted.

Further, according to the present invention, there is no reset terminal, and the present invention can be used for reconfiguring a processor or an FPGA which is reset only when the power is turned on. Can be saved.

According to the present invention, since the processor or the board is reset as hardware, the inside of the processor can be completely initialized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a configuration of an I / O board according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a configuration of an I / O board according to a second embodiment of the present invention.

FIG. 3 is a block diagram illustrating an example of a configuration of an I / O board according to a third embodiment of the present invention.

FIG. 4 is a block diagram illustrating an example of a configuration of a conventional I / O board.

[Explanation of symbols]

11, 21, 31, 41 I / O processor (processor), 12, 22, 32, 42 flash memory, 1
3, 23, 33 reset circuit, 14 logic circuit, 1
5, 25, 35, 45 I / O board (substrate), 16,
26, 36, 46 host I / O bus (excluding reset signal), 17, 47 I / O bus reset signal, 18, 2
8, 38 reset signal, 24, 34 power control circuit,
27, 37 power supplies, 39 FPGAs.

Claims (6)

[Claims] 1. A board provided with a processor for executing a command constituting a program, wherein the processor outputs a reset request signal requesting reset of the processor itself, and the board outputs a reset request signal output from the processor. And a reset circuit for outputting a processor reset signal for instructing a reset of the processor. 2. The substrate according to claim 1, wherein said reset circuit outputs a substrate reset signal for instructing a reset of the substrate. 3. The substrate further includes a non-volatile memory for storing a program including firmware, wherein the processor reads a program from the non-volatile memory to execute an instruction forming the program, and executes the non-volatile memory. 2. The substrate according to claim 1, wherein the reset request signal is output when the memory is rewritten. 4. The board according to claim 1, wherein the board is mounted on a computer, and the processor reset signal indicates a reset of a processor provided on the board without resetting the computer. substrate. 5. The power supply control circuit for controlling power supplied to a processor, the reset circuit outputs a processor reset signal to the power supply control circuit, and the power supply control circuit receives the input signal. The substrate according to claim 1, wherein the processor is reset by interrupting power supplied to the processor based on the processor reset signal. 6. A reset method of a processor provided on a substrate and restarting a processor executing instructions constituting a program, wherein the processor outputs a reset signal instructing reset of the processor itself, and outputs the reset signal from the processor. Input the reset signal
A processor reset method comprising a reset circuit for instructing a reset of the processor.