JP2000347772A - Power consumption reduction control method for processor to be used for portable information equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain the reduction of power consumption while preventing required interruption responsiveness from being damaged by preventing a power source from being turned off even in the standstill state of a processor when the interruption responsiveness is set high. SOLUTION: Inside a processor 10, a setting register 15 is provided for setting a value when requesting high interruption responsiveness. When the start of the standstill (or stop) state of portable information equipment is judged, it is judged whether the value of high interruption responsiveness is set to the setting register 15 or not. When the value of high interruption responsiveness is set to the setting register 15, in the standstill state, the power source of the processor 10 is prevented from being turned off. Thus, when turning the processor 10 into standstill state, it is controlled based on the state of equipment at that time or application software to be used whether or not the power source is to be turned off and power consumption can be reduced while preventing required interruption responsiveness from being damaged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for controlling low power consumption of a processor having low power consumption control means used for portable information equipment.

[0002]

2. Description of the Related Art Processors used in portable information devices such as mobile and handheld PCs have an execution state (RU).
N), idle state (IDLE), stop state (SUSPEN)
D). In the following description,
The execution state is a state where the program is being executed.
The hibernate state is a state in which the power is turned on and the system is started but there is no program being executed, or a state in which the user is looking at the screen and there is no input. The stopped state is a state in which the power is turned off. However, in the case of portable information devices, the power is not actually turned off.
It is assumed that data in the M memory is held.

[0003] In a portable information device incorporating a processor having the above-mentioned state, various devices have been devised in order to extend the life of the battery.

[0004] For example, a method of turning off the power when the processor is not used has already been performed as a device for reducing power consumption when the portable information device enters a suspend state (suspend). However, when entering the sleep state (idle), only the input clock of the processor is stopped.

[0005] This is because the power consumption of the portable information device is sufficiently reduced only by stopping the clock of the processor. However, with the progress of semiconductor process technology, the power consumed only by turning on the power has increased, and the power consumption in the idle state cannot be ignored.

The reason why the power is turned off when the processor is not used in the stop state is as follows.
Usually, this is to reduce the power consumed while carrying the portable information device (not using the portable device).

[0007]

It is certain that power consumption can be reduced by turning off the processor when the processor of the portable information device goes into a hibernation state, but this poses a problem at this time. Is the response of the interrupt. As a portable information device, a certain level of interrupt response (about several tens of microseconds) is required if it is in use, and a normal interrupt frequency is assumed to be about several milliseconds.

According to the present invention, when the processor enters a hibernation state, whether the power of the processor is turned off is controlled by the state of the device at that time and the application software to be used, so that the necessary interrupt responsiveness is not impaired. It is an object of the present invention to provide a power consumption control method that realizes reduction of power consumption, which is an original object.

[0009]

In order to achieve the above object, a low power consumption control method according to the present invention is a low power consumption control method for a processor having a low power consumption control means used in a portable information device. When the user sets the interrupt responsiveness of the portable information device high,
Thereafter, even if the processor of the portable information device enters a hibernation state, the power of the processor is not turned off.

In order to achieve the above object, a low power consumption control method according to the present invention is a low power consumption control method for a processor having low power consumption control means used in a portable information device. When a specific application mounted on the portable information device requests interrupt responsiveness, the power of the processor is not turned off even when the processor is in a halt state during the execution of the application. Features.

In order to achieve the above object, a low power consumption control method according to the present invention is a low power consumption control method for a processor having a low power consumption control means used in a portable information device, The portable information device is equipped with an operating system of a type that loads driver software such as a modem or a mobile phone for the first time when the device is used. When it is determined that the information is loaded on the information device, the power of the processor is not turned off even if the processor is in a halt state while the driver software is being loaded. .

Further, in order to achieve the above object, a low power consumption control method of the present invention is a low power consumption control method for a processor having a low power consumption control means used in a portable information device, The operating system mounted on the portable information device determines whether or not an interrupt with high real-time property is enabled. If the interrupt is enabled, even if the processor is in a halt state, the processor of the processor is disabled. It is characterized by not turning off the power.

According to another aspect of the present invention, there is provided a method for controlling low power consumption of a processor having low power consumption control means used in a portable information device. The operating system installed in the portable information device examines the activated processes, and determines whether any of the processes waiting for I / O requires high interrupt responsiveness, When there is a process that requires high interrupt responsiveness, the power of the processor is not turned off even when the processor is in a halt state.

[0014]

FIG. 1 is a block diagram showing a configuration of a low power consumption control device applied to a portable information device according to the present invention.

In FIG. 1, a low power consumption control device includes a processor 10, a power supply control device 20, and an interrupt control device 3.
0. The power control device 20 has a control register 25. The interrupt control device 30 also has a control register 35. A setting register 15 in which a value is set when a high interrupt response is required is provided inside the processor 10. The setting register 15 is not limited to this, and may use a specific address, a flip-prop, or the like in the memory area.

Between the processor 10 and the power supply control device 20, a power supply line 12 for supplying power from the power supply control device 20 to the processor 10, and read / write control information from the processor 10 to a control register 25 of the power supply control device 20. And a read / write line 14 for performing the operations.

The processor and the interrupt controller 30
The write line 16 for writing control information from the processor 10 to the control register 35 of the interrupt control device 30 and an external interrupt from the external interrupt line 40 are received by the interrupt control device 30, and the interrupt terminal of the processor 10 Alternatively, they are connected by an interrupt line 18 input to a reset terminal and a reset line 19.

The interrupt control device 30 and the power control device 20 are connected by a signal line 50 for outputting a control signal from the interrupt control device 30 to the power control device 20.

FIG. 2 is a flowchart showing the operation of the low power consumption control device described above.

When the operating system OS executed in the processor 10 determines that the portable information device enters a hibernation state (or a halt state), the operating system OS determines whether a high interrupt responsiveness value is set in the setting register 15 or not. (Step S10). If the setting register 15
If a high interrupt responsiveness value is set in step S11, the power of the processor 10 is not cut off in the sleep state (step S11). The setting operation to the setting register 15 will be described later.

On the other hand, if the value of the high interrupt response is not set in the setting register 15, the OS sends the control register 3 of the interrupt control device 30 through the write line 16.
Rewrite the setting of 5. In response, the interrupt control device 30 switches the interrupt signal from the external interrupt line 40 to the reset line 19 (Step S12).
The normal state is connected to the interrupt line 18 of the processor 10.

Subsequently, the OS writes control information to the control register 25 of the power supply control device 20 via the read / write line 14, and recognizes the control information.
Stops the power supply to the power supply line 12 and shuts off the power supply to the processor 10 (step S13).

At this time, since the power of hardware other than the processor is not cut off, information set in the control registers is not lost. It is also assumed that the memory (not shown) is designed so that its contents are not lost by using the self-refresh mode of the DRAM memory.

Thereafter, when an external interrupt signal is generated and input from the external interrupt line 40, an instruction for supplying power to the processor 10 from the interrupt control device 30 to the power control device 20 via the signal line 50 is issued. A signal is sent. Further, the processor 10 is reset by the reset line 19 (step S1).
4).

The processor 10 whose power supply has been resumed,
Similar to a normal power-on reset, the reset sequence (OS program) starts to be executed.
Reads the contents of the control register 25 of the power supply control device 20 and determines whether to return from the normal power-on reset or to return from the sleep state (or the stop state) (step S15). Then, in the case of the return from the power-on reset, the power-on reset return sequence is executed as it is (step S16), and in the case of the return from the sleep state (or the stop state), the necessary hardware initialization is performed. Is performed, and the program being executed is restarted (step S17).

Here, the transition from the execution state of the processor to the halt state (or halt state) will be described.

The process scheduler of the OS is started by a timer interrupt every predetermined time (on the order of several milliseconds) and searches for a process that can be executed at that time. Runs any processes that are enabled and returns to hibernation when complete.

For example, when a text editor or a word processing function is being executed, most of the time is in an I / O wait state such as a keyboard input wait state, so that the process becomes executable. Often not. In this case, the time in the execution state can be expected to be about several percent of the whole.

Also, for example, even during data communication such as modem control, an I / O
In many cases, it is waiting for O, and even in this case,
The processor is in the running state for several tens of percent of the time
Can be expected.

However, during communication or the like, after receiving an external interrupt indicating that data has arrived,
There may be a limit on the time until the data is actually processed. For example, in soft modem communication, if an acknowledgment for data transmission is not received within a certain time, an error occurs due to data loss. Also, TC
In the P / IP communication, if an acknowledgment for data transmission is not received within a certain period of time, re-execution or the like frequently occurs and performance is significantly reduced.

In this case, the time required for the processor to change from the sleep state to the execution state and process data is determined by the above-described step S14, steps S15-S16, and S15-S17.
And the time from when the communication process is executed after steps S16 and S17 are completed until the data processing is actually completed.

When the power is turned off after the processor enters the hibernation state, the time for resetting the processor by hardware and the time for restoring the internal state of the processor are compared with the case where the power is not turned off. It is well known that extra time such as time is required. This can be expected to be several tens of microseconds in total.

This waiting time is not a problem for a user who is a user of the device or for an application program which does not require high interrupt responsiveness. For example, when the user looks at the screen and performs an input operation from the keyboard,
Even if the response is slowed down by about several tens of microseconds as compared with the conventional device, there is no problem. However, there may be a case where a particular application program or the device is used for a particular purpose. For example, a case where the above-described certain data communication is performed may be considered.

According to the present invention, only when a high interrupt response is set in the setting register 15, the power is maintained without turning off the power of the processor when entering the sleep state. In other cases, the power is turned off by the above-described method or the like, thereby reducing the power consumption while maintaining the required interrupt responsiveness.

In the following, various embodiments for setting the high interrupt response to the setting register 15 will be described.

(First Embodiment) FIG. 3 is a flowchart showing the operation of the first embodiment.

If the user instructs the application to give a high interrupt response before executing the application (Yes in step S20), the setting register 15 is stored in the setting register 15 by software means. Set the value (Step S2
1) Otherwise, set a normal value (step S)
22). When the OS shifts from the execution state to the sleep state, in step S10 of FIG.
When high interrupt responsiveness is set, the power supply of the processor is not cut off in the sleep state.

When the interrupt responsiveness of the portable information device is set high by the user as in the present invention, the power of the processor is not turned off even if the processor of the portable information device goes into a halt state thereafter. The power consumption can be reduced while maintaining the required interrupt responsiveness.

(Second Embodiment) FIG. 4 is a flowchart showing the operation of the second embodiment.

When the application software requires high interrupt responsiveness as attribute information of each application, such as when installing the application software (Yes in step S30), the value is set in the setting register 15 by software means. (Step S31) Otherwise, a normal value is set (Step S32). When the OS transitions from the execution state to the sleep state, the OS reads the setting information of the setting register 15 in step S10 of FIG. 2 and, if high interrupt responsiveness is set, shuts down the power of the processor in the sleep state. Do not do anything.

When the interrupt responsiveness of a specific application installed in the system is set high as in the present invention, the power of the processor is not turned off even if the processor is in a halt state during the execution of the application. The power consumption can be reduced while maintaining the required interrupt responsiveness.

(Third Embodiment) FIG. 5 is a flowchart showing the operation of the third embodiment.

As the types of the OS, there are a type loaded when a device driver is used, and a type preinstalled in a kernel. When the OS is the former, when the OS shifts from the execution state to the hibernation state, a list of loaded device drivers and a high interrupt responsiveness set in advance (for example, when the OS or the device driver is installed) are required. By comparing and referring to a list of devices (step S40), if there is an entry that matches both, the power supply of the processor is not cut off in the hibernate state (step S41). If they do not match, the operation is the same as that described with reference to FIG. 2, and a description thereof will be omitted.

As in the present invention, when it is determined by the operating system that driver software such as a modem or a mobile phone is loaded on the portable information device, the processor operates while the driver software is loaded. By setting the power of the processor not to be turned off even in the hibernation state, it is possible to reduce power consumption while maintaining necessary interrupt responsiveness.

(Fourth Embodiment) FIG. 6 is a flowchart showing the operation of the fourth embodiment.

When shifting from the execution state to the sleep state, the OS checks whether or not all interrupts are enabled (step S50), and interrupts requiring high interrupt responsiveness are enabled. In this case, the power of the processor is not shut off in the sleep state (step S51). If it is not enabled, the operation is the same as that described with reference to FIG. 2, and a description thereof will be omitted.

According to the present invention, it is determined by the operating system whether or not an interrupt having high real-time property is enabled. By setting the power supply not to be turned off, it is possible to reduce power consumption while maintaining necessary interrupt responsiveness.

(Fifth Embodiment) FIG. 7 is a flowchart showing the operation of the fifth embodiment.

When the OS shifts from the execution state to the sleep state, the OS checks the state of all processes, and among the processes in the I / O waiting state, there is a process requiring high interrupt responsiveness. It is confirmed whether or not (step S60). If there is a process that requires high interrupt responsiveness, the power of the processor is not cut off in the sleep state (step S61). If there is no process, the operation is the same as that described with reference to FIG. 2, and a description thereof will be omitted.

According to the present invention, the operating system checks the activated processes to determine whether any of the processes waiting for I / O requires a high interrupt responsiveness. However, if there is a process that requires high interrupt responsiveness, by setting the processor not to be turned off even if the processor goes into a halt state, it is possible to maintain the necessary interrupt responsiveness. Power consumption can be reduced.

[0051]

According to the present invention, when the processor enters the hibernation state, whether or not the power is turned off is controlled by the state of the device at that time and the application software to be used, so that the necessary interrupt responsiveness is not impaired. However, it is possible to reduce the power consumption, which is the original purpose.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a low power consumption control device applied to a portable information device of the present invention.

FIG. 2 is a flowchart showing an operation of the low power consumption control device applied to the portable information device of the present invention.

FIG. 3 is a flowchart showing the operation of the first embodiment of the low power consumption control method of the present invention.

FIG. 4 is a flowchart showing the operation of the second embodiment of the low power consumption control method of the present invention.

FIG. 5 is a flowchart showing the operation of the third embodiment of the low power consumption control method of the present invention.

FIG. 6 is a flowchart showing the operation of the fourth embodiment of the low power consumption control method of the present invention.

FIG. 7 is a flowchart showing the operation of the fifth embodiment of the low power consumption control method of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Processor, 20 ... Power supply control device, 30 ... Interrupt control device 15, 25, 35 ... Control register 12 ... Power supply line, 14 ... Read / write line, 16 ... Write line 18 ... Interrupt line, 19 ... Reset line 40 ... External interrupt Line, 50 ... signal line

Claims (5)

[Claims] 1. A method for controlling low power consumption of a processor having low power consumption control means used in a portable information device, the method comprising the steps of: A method of controlling power consumption of a processor used in a portable information device, wherein the power of the processor is not turned off even if the processor of the portable information device is in a halt state thereafter. 2. A method for controlling low power consumption of a processor having low power consumption control means used in a portable information device, wherein a specific application mounted on the portable information device requests an interrupt response. In such a case, the power of the processor is not turned off even when the processor is in a halt state during the execution of the application. 3. A method for controlling low power consumption of a processor having a low power consumption control means used for a portable information device, wherein the portable information device is provided with driver software such as a modem or a mobile phone. When an operating system of a type that is loaded for the first time when used is installed, and the operating system determines that the driver software such as the modem or the mobile phone is loaded on the portable information device, the driver A low power consumption control method for a processor used in a portable information device, wherein the processor is not turned off even when the processor is in a halt state while software is loaded. 4. A method for controlling low power consumption of a processor having low power consumption control means used for a portable information device, wherein an interrupt with high real-time property is enabled by an operating system mounted on the portable information device. It is determined whether or not the processor is turned off, and if the processor is enabled, the processor is not turned off even when the processor is in a hibernation state. Low power consumption control method for processors. 5. A method for controlling low power consumption of a processor having low power consumption control means used in a portable information device, wherein a process activated by an operating system mounted on the portable information device is checked. It is determined whether there is a process requiring high interrupt responsiveness among the processes waiting for I / O, and if there is a process requiring high interrupt responsiveness, the processor A low power consumption control method for a processor used in a portable information device, wherein the power of the processor is not turned off even in a hibernation state.