CN105824650A - Computer system, adaptive dormancy control module and control method for same - Google Patents
Computer system, adaptive dormancy control module and control method for same Download PDFInfo
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Abstract
The invention provides a computer system, an adaptive dormancy control module and a control method for the same. The computer system comprises a central processor, an auxiliary processor and a JTAG connection port connecting the central processor and the auxiliary processor; when the auxiliary processor receives a dormancy trigger signal, a dormancy program is executed, so a current state of the computer system can be backed up and the computer system is closed; and when a wake-up trigger signal is received, a wake-up program is executed according to wake-up data corresponding to the central processor, so the computer system can restores to a state before the dormancy program execution. The central processor is replaced by the auxiliary processor to execute the dormancy program and the wake-up program, so the computer system can be quickly powered on; and a quick-power on function can be adaptive to central processors of various types without modification of operation systems or program start.
Description
Technical field
It is relevant that this utility model relates to a kind of computer system, control module and control method, has the adaptive dormancy control computer system of function, adaptive dormancy control module and adaptive dormancy control method particularly to a kind of.
Background technology
Existing advanced configuration and power interface (AdvancedConfigurationandPowerInterface, ACPI) standard are current modal power management specifications.By this ACPI standard, make research staff more easily computer system can be carried out power management.
In ACPI standard, the sleep state (SleepingStates, S-States) of computer system includes six kinds of patterns of S0, S1, S2, S3, S4 or S5.It is introduced only for more conventional S0, S3 and S4 Three models in this.
Under S0 pattern, computer system is the state of normal boot-strap running.
S3 pattern is also called standby (Standby) pattern or is suspended to memory main body (SuspendtoRAM, STR) pattern, under standby mode, a computer system only provides electrical power to a memory main body, and stops power supply to other devices to save electric power.When computer system leaves standby mode, owing to this memory main body still storing all status datas before this computer system enters standby mode, this computer system is not necessary to heavily loaded various software (such as driver or operating system) or re-starts initialization and can directly operate, and can realize quick turn-on function and recover to entering the state before standby mode.
In more detail, owing to this memory main body is volatile memory (volatilememory), therefore this computer system must enter after standby mode continued power to this memory main body.Once this memory main body is de-energized, the all data (including the status data of this computer system) being stored in this memory main body will be caused to disappear, so this computer system will be made cannot to realize quick turn-on function and the state recovered to entrance standby mode after leaving standby mode.
S4 pattern is also called dormancy (Hibernate) pattern or is suspended to hard disk (SuspendtoDisk, STD) pattern.Referring to the first schematic diagram that Figure 1A and Figure 1B, Figure 1A are existing park mode, Figure 1B is the second schematic diagram of existing park mode, in order to illustrate that existing computer system enters park mode and leaves the function mode of park mode.
As shown in Figure 1A, existing computer system 1 includes central processing unit 10, memory main body 12 and a hard disk 14.This memory main body 12 store to should a status data 120 of existing computer system 1 current state.
This hard disk 14 stores a dormancy program 140.This dormancy program 140 is to be exclusively used in this central processing unit 10 specific.Specifically, this dormancy program 140 is operating system (Operatingsystem, OS) or a part for boot program (bootloader) for this existing computer system 1.
When this central processing unit 10 receives a dormancy triggering signal, this dormancy program 140 can be performed so that this existing computer system 10 enters park mode.Specifically, this central processing unit 10 is after performing this dormancy program 140, this status data 120 can back up to this hard disk 14 using as Status of Backups data 120 ', and all devices (including this memory main body 12) stopped power supply to this existing computer system 1 are to save electric power.
When this central processing unit 10 having been enter into park mode receives a wake up trigger signal, this dormancy program 140 can be performed to leave park mode.Specifically, after this central processing unit 10 is waken up and performs this dormancy program 140, these Status of Backups data 120 ' can be loaded into this memory main body 12 using as this status data 120 (as shown in Figure 1B) from this hard disk 14, and reopen other devices.
Thereby, this existing computer system 1 can realize quick turn-on function, and can be by these Status of Backups data 120 ', and after being waken up, fast quick-recovery current state is the state before entering park mode.Further, owing to all devices are stopped power supply under park mode by this existing computer system 1, the pattern of power saving during therefore park mode is sleep state.
But, owing to this dormancy program 140 is to be exclusively used in this central processing unit 10 specific.New central processing unit is used (i.e. when the manufacturer of this existing computer system 1 is intended to release, another central processing unit different types of with this central processing unit 10) this existing computer system 1 time, this dormancy program 140 must significantly be revised by the research staff of system manufacturer, so that this dormancy program 140 is applicable to this new central processing unit.Further, owing to this dormancy program 140 is a part for operating system or boot program, difficulty and the complexity of aforementioned modifications are more added.
So, existing park mode carries into execution a plan and there is the problem that above-mentioned adaptive is too low, and urgently more effectively solution is suggested.
Summary of the invention
The main object of the present invention, is to be to provide a kind of computer system, adaptive dormancy control module and adaptive dormancy control method, is applicable to different types of central processing unit.
For reaching above-mentioned purpose, the present invention is to provide a kind of computer system, the central processing unit including a JTAG connectivity port, being electrically connected with this JTAG connectivity port and the secondary processor connecting this JTAG connectivity port.This secondary processor have to should central processing unit one wake up data up.Wherein, this secondary processor sends a dormant control signal to this central processing unit in time receiving a dormancy and trigger signal, performing a dormancy program by the control of this central processing unit, this dormancy program includes backing up the current status data of this computer system and closing this computer system；And, this secondary processor sends one in time receiving a wake up trigger signal and wakes up up and control signal to this central processing unit, performing a wake up procedure by according to this up control of this central processing unit is waken up data, this wake up procedure includes making this computer system to recover to performing the state before this dormancy program.
From the above, wherein further include: a memory main body, be electrically connected with this central processing unit, store this status data；And a non-volatility memory, it is electrically connected with this central processing unit；This secondary processor backs up this status data to this non-volatility memory using as Status of Backups data in time performing this dormancy program, and in time performing this wake up procedure, wake up data up according to this and read this Status of Backups data from this non-volatility memory, and be loaded into this memory main body using as this status data.
From the above, wherein this wakeup packet include to should a scratch memory data address of central processing unit, an an access data address and mapping address of this non-volatility memory of this memory main body, wherein this mapping address is corresponding to this access data address.
From the above, wherein this secondary processor is in time performing this wake up procedure, this central processing unit is made to operate according to this scratch memory data address and start this computer system, and read this Status of Backups data from this mapping address of this non-volatility memory, and it is loaded into this access data address of this memory main body.
From the above, wherein this wakes up data up is a text file or one or two meta files；This wakes up data up and is stored in a memory body of this secondary processor, this non-volatility memory or connects an external memory of this central processing unit.
From the above, wherein this JTAG connectivity port connects one end of a JTAG connecting element, and this secondary processor connects the other end of this JTAG connecting element；Joint test work group technology supported by this central processing unit.
From the above, wherein further including a trigger element, connect this central processing unit or this secondary processor, this trigger element produces this dormancy in time accepting peripheral operation and triggers signal or this wake up trigger signal.
The present invention further provides a kind of adaptive dormancy control module, assist connectivity port including the one of the JTAG connectivity port connecting a computer system via a JTAG connecting element and be electrically connected with a secondary processor of this auxiliary connectivity port.This secondary processor have to should central processing unit one wake up data up.Wherein this JTAG connectivity port is electrically connected with a central processing unit of this computer system.Wherein, this secondary processor sends a dormant control signal to this central processing unit in time receiving a dormancy and trigger signal, performing a dormancy program by the control of this central processing unit, this dormancy program includes the current state backing up this computer system and closes this computer system；And, this secondary processor sends one in time receiving a wake up trigger signal and wakes up up and control signal to this central processing unit, performing a wake up procedure by according to this up control of this central processing unit is waken up data, this wake up procedure includes making computer system to recover to performing the state before this dormancy program.
The present invention further provides a kind of adaptive dormancy control method, comprise the following steps: that an a) secondary processor sends a central processing unit of a dormant control signal a to computer system in time receiving a dormancy and trigger signal, perform a dormancy program by the control of this central processing unit；B) this central processing unit backs up the current state of this computer system according to this dormant control signal and cuts out this computer system；C) this secondary processor obtain in time receiving a wake up trigger signal to should computer system a central processing unit one wake up data up；D) send one and wake up control signal up and this wakes up data up to this central processing unit, perform a wake up procedure by the control of this central processing unit is waken up up data according to this；And e) this central processing unit wakes up control signal up according to this and makes this computer system recover to performing the state before this dormancy program.
From the above, wherein this step b comprises the following steps: b1) receive this dormant control signal；B2) status data a to non-volatility memory of this computer system it is stored according to the backup of this dormant control signal, using as Status of Backups data；And b3) close this computer system according to this dormant control signal.
From the above, wherein this step e comprises the following steps: e1) receive this and wake up control signal up and this wakes up data up；E2) wake up control signal up according to this and this wakes up data up and starts this computer system；And e3) wake up control signal up according to this and this wakes up data up and reads this Status of Backups data from this non-volatility memory, and it is loaded into a memory main body of this computer system, using as this status data.
From the above, wherein this wakeup packet includes should a scratch memory data address of central processing unit；This step e2 is to make this central processing unit operate according to this scratch memory data address and start this computer system.
From the above, wherein this wakeup packet includes access data address and a mapping address of this non-volatility memory of this memory main body, and wherein this mapping address is to accessing data address；This step e3 is that this mapping address from this non-volatility memory reads this Status of Backups data, and is loaded into this access data address of this memory main body.
From the above, wherein this wakes up data up is a text file or one or two meta files.
The present invention performs dormancy program and wake up procedure via with secondary processor replacement central processing unit, can be under the operating system that need not revise computer system or the situation starting program, order uses the computer system of different types of central processing unit all can realize quick turn-on function.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Accompanying drawing explanation
Figure 1A is the first schematic diagram of existing park mode；
Figure 1B is the second schematic diagram of existing park mode；
Fig. 2 is the computer system architecture figure of the present invention the first specific embodiment；
Fig. 3 is the computer system schematic appearance of the present invention the first specific embodiment；
Fig. 4 is the adaptive dormancy control module Organization Chart of the present invention the first specific embodiment；
Fig. 5 is the adaptive dormancy control module schematic appearance of the present invention the first specific embodiment；
Fig. 6 is the adaptive dormancy control method flow chart of the present invention the first specific embodiment；
Fig. 7 is the adaptive dormancy control method flow chart of the present invention the second specific embodiment.
Wherein, reference
1 ... existing computer system
10,22 ... central processing unit
12,26 ... memory main body
120,260 ... status data
120 ', 260 ' ... Status of Backups data
14 ... hard disk
140 ... dormancy program
2 ... computer system
20 ... JTAG connectivity port
24,40 ... secondary processor
240,400 ... wake up data up
28 ... non-volatility memory
30 ... trigger element
32 ... printed circuit board (PCB)
34 ... read module
36 ... external memory
4 ... adaptive dormancy control module
42 ... auxiliary connectivity port
44 ... auxiliary printing circuit board
A1, a2 ... JTAG connecting element
S600-S612 ... the first rate-determining steps
S700-S720 ... the second rate-determining steps
Detailed description of the invention
Hereby with regard to a preferred embodiment of the present invention, coordinate accompanying drawing, after describing in detail such as.
Head refers to Fig. 2, for the computer system architecture figure of the present invention the first specific embodiment.As in figure 2 it is shown, the computer system 2 (hereinafter referred to as computer system 2) that the tool adaptive dormancy of the present invention controls function mainly includes JTAG connectivity port 20, central processing unit 22 and a secondary processor 24.
This JTAG connectivity port 20 is used for transmitting instruction or data.Specifically, this JTAG connectivity port 20 is the connectivity port supporting joint test work group (JointTestActionGroup, JTAG) interfacing.
It is noted that jtag interface technology is the technology developed based on IEEE-1149.1 boundary scan architecture (IEEE-1149.1BoundaryScanArchitecture).In application aspect, jtag interface is that one is specifically designed to burning or the interface of test one printed circuit board (PCB) (PrintedCircuitBoard, PCB) (printed circuit board (PCB) 32 as shown in Figure 3).
For example, in development, when research staff wants each function of this computer system 2 carries out error detection or removes wrong (debug), a circuit simulator (In CircuitEmulator, ICE) can be connected to this JTAG connectivity port 20 of this computer system 2.Then, this research staff this circuit simulator operable sends specific one and controls signal to this computer system 2, and observes this computer system 2 when operating according to this control signal, if make a mistake and whether mistake is got rid of.In sum, this research staff can control signal to this computer system 2 via jtag interface technology various this of input easily, to simulate various situation and to carry out error detection or except mistake.
It is preferred that this control signal includes an address field and an instruction field.Why the corresponding hardware location to the device to be controlled of this address field, indicate device that this central processing unit 22 to be controlled.This instruction field controls the content (as interrupted electric power, providing electric power, reading data or write data) of operation in order to indicate.
Due to above-mentioned advantage, computer system can arrange this JTAG connectivity port 20 in development, to facilitate research staff to carry out error detection or except mistake.
This central processing unit 22 is electrically connected with this JTAG connectivity port 20, and can control each element running (such as power on/off or mouse enable/forbidden energy) of this computer system 2.Further, this central processing unit 22 can receive this control signal via this JTAG connectivity port 20, and performs should the operation of control signal.It is preferred that JTAG technology supported by this central processing unit 22.
For example, if this control signal is a pass machine control signal, then this central processing unit 22 is after receiving this pass machine control signal, can close all devices (including this central processing unit 22) of this computer system 2, so that this computer system 2 enters off-mode.
This secondary processor 24 connects this JTAG connectivity port 20.Specifically, this secondary processor 24 connects this JTAG connectivity port 20 via JTAG connecting element a1.This JTAG connectivity port 20 connects one end of this JTAG connecting element a1, and this secondary processor connects the other end of this JTAG connecting element a1.It is preferred that this JTAG connecting element a1 is bus (bus) or the conducting wire being printed in this printed circuit board (PCB) 32, but it is not limited.
This secondary processor 24 can send this via this JTAG connecting element a1 and this JTAG connectivity port 20 and control signal to this central processing unit 22 to control this central processing unit 22, and controls this computer system 2 by this central processing unit 22.
Then illustrate how this secondary processor 24 of the present invention controls this computer system 2 and enter a park mode (Hibernatemode).This secondary processor 24, in time receiving a dormancy and trigger signal, can send dormancy triggering a dormant control signal of signal to this central processing unit 22 to control this central processing unit 22.In the present embodiment, this secondary processor 24 is to perform a dormancy program via this dormant control signal of transmission.This dormancy program includes by this central processing unit 22 of control to back up the action of the current state of this computer system 2, and closes this computer system 2, so that this computer system 2 enters the action of this park mode.
Specifically, this computer system 2 further includes a memory main body 26 (such as random access memory (RandomAccessMemory,) and a non-volatility memory 28 (non-volatilememory RAM), such as disk hard disk (HardDiskDrive, HDD), fast flash memory bank (flashmemory) or solid state hard disc (SolidStateDrive, SSD)).This memory main body 26 is electrically connected with this central processing unit 22, is configured to temporarily store a status data 260.Wherein, aforesaid state data 260 are the current states (such as current application program, form or the current system default parameter opened) representing this computer system 2, and are stored in an access data address of this memory main body 26.
When this secondary processor 24 performs this dormancy program, being to control this central processing unit 22 so that this status data 260 to back up to a mapping address of this non-volatility memory 28 from this access data address, wherein this mapping address is corresponding to this access data address.Thereby, this non-volatility memory 28 can store Status of Backups data 260 ', and can avoid losing this status data 260 because this memory main body 26 is de-energized.Further, this computer system 2 can completely close, without providing electrical power to this memory main body 26 after entering this park mode (that is, this secondary processor 24 performs this dormancy program success).
Then illustrate how this secondary processor 24 controls this computer system 2 and leave this park mode.When this secondary processor 24 receive one wake up up (wakeup) trigger signal time, can first obtain to should central processing unit 22 one wake up data 240 up, and wake up data 240 up according to this and send one and wake up up and control signal to this central processing unit 22 to control this central processing unit 22.In the present embodiment, this secondary processor 24 is to wake up control signal up and perform a wake up procedure via sending this.This wake up procedure is to include starting the action of this computer system 2 by controlling this central processing unit 22, and makes this computer system 2 recover to the action performing the state before this dormancy program.
Specifically, this wakes up data 240 up and can be stored in a memory body of this secondary processor 24, this non-volatility memory 28 or connect an external memory of this central processing unit 22.If this wakes up data 240 up is designed to be stored in the memory body of this secondary processor 24, owing to this research staff can be not necessary between consideration different file (filesystem) (i.e., this non-volatility memory 28 may use different file system standard from this secondary processor 24) access issues, and can effectively shorten the research and development time.In the present embodiment, this wakes up data 240 up and mainly includes should a scratch memory data address of central processing unit 22, this access data address and this mapping address.Preferably, this scratch memory data address is to be preset according to the type of this central processing unit 22 by this research staff, this access data address this memory main body 26 acquired in time performing this dormancy program that is this secondary processor 24 stores the memory body address of this status data 250, this mapping address be this research staff in advance prior to the memory body address in order to store these Status of Backups data 260 ' of institute's programming in this non-volatility memory 28, but do not limit with this.
This secondary processor 24 obtains after this wakes up data 240 up, wakes up data 240 up according to this and sends this and wake up up and control signal to this central processing unit 22, to perform this wake up procedure.By the execution of this wake up procedure, this secondary processor 24 can transmit this scratch memory data address to this central processing unit 22, so that this central processing unit 22 operates according to this scratch memory data address.
In more detail, this central processing unit 22 includes multiple buffer.Further, respectively this buffer is respectively corresponding to one group of this scratch memory data address.This central processing unit 22 is based on this scratch memory data address multiple and the plurality of buffer is carried out access control, to perform various computing or program.
Therefore, in the present invention, when this central processing unit 22 receives after this wakes up control signal and this scratch memory data address up, and this central processing unit 22 can be enabled.Further, this central processing unit 22 can carry out access control according to this scratch memory data address to the plurality of buffer, and can wake up control signal up according to this and perform correspondence and control (resuming operation as controlled other devices of this computer system 2).
After this central processing unit 22 wakes up control signal and the recovery normal operation of this scratch memory data address up according to this, control signal, this access data address and this mapping address can be waken up up according further to this and read this Status of Backups data 260 ', and be loaded into the access data address of this memory main body 26 to recover this status data 260.Thereby, this secondary processor 24 wakes up data 240 up via this can make this fast quick-recovery normal operation of central processing unit 22, and makes this computer system 2 can realize quick turn-on function and dormancy control function.
For example, when this central processing unit 22 (such as the first central processing unit) of this computer system 2 is replaced with another central processing unit different types of (such as the second central processing unit) by manufacturer, using during as new product, this research staff of this manufacturer only need to revise this wake up up data (as by should this scratch memory data address of the first central processing unit replace with should this scratch memory data address of the second central processing unit), by this secondary processor 24, the computer system being configured with this second central processing unit can be made to realize quick turn-on function and dormancy controls function, and be not necessary to additionally operating system or the startup program of this computer system 2 be modified.In sum, the present invention can effectively shorten the research and development time of computer system in fact.
It is preferred that this wakes up data 240 up is a text file (such as a script file (scriptfile)) or one or two meta files (binaryfile).When this wakes up data 240 up for this text file, it is this two meta file that this text file first can be changed (as compiling (compiler) or group translate (assembler)) by this secondary processor 24, then performs this wake up procedure according to the content of this two meta file.
In another embodiment of the present invention, this computer system 2 further includes a trigger element 30 (such as power button).This trigger element 30 connects this central processing unit 22, and produces this dormancy triggering signal or this wake up trigger signal in time accepting peripheral operation, and is sent to this secondary processor 24 via this central processing unit 22.In the present embodiment, this trigger element 30 is to connect this central processing unit 22, but is not limited.In another embodiment, this trigger element 30 also can be directly connected to this secondary processor 24, and directly transmits this dormancy triggering signal or this wake up trigger signal to this secondary processor 24.
Refer to Fig. 3, for the computer system schematic appearance of the present invention the first specific embodiment, in order to the set-up mode of each element of this computer system 2 to be described.
As it is shown on figure 3, in this example, this JTAG connectivity port 20, this central processing unit 22, this secondary processor 24, this memory main body 26 and this non-volatility memory 28 are all arranged on this identical printed circuit board (PCB) 32.
This computer system 2 further includes a read module 34.This read module 34 is arranged on this printed circuit board (PCB) 32, and is electrically connected with this central processing unit 22 by this printed circuit board (PCB) 32.In the present embodiment, (this external memory 36 can for example, safety digit (SecureDigital in order to read an external memory 36 for this read module 34, SD), this read module 34 can for example, card reader), wherein this wakes up data 240 up and is stored in this external memory 36.
Preferably, multiple this of corresponding different types of central processing unit can be waken up up data 240 and store to the most different this external memory 36 (i.e., respectively this stored by this external memory 36 wake up data 240 up be in harmony corresponding to a type of central processing unit) respectively by this research staff.When this central processing unit 22 of this computer system 2 is replaced, this research staff only needs to be inserted into this read module 34 by storing corresponding this this external memory 36 waking up data 240 up to the central processing unit being replaced, this secondary processor 24 can be made to obtain this of correspondence and to wake up data 240 up, and realize quick turn-on function and dormancy controls function.
Refer to the adaptive dormancy control module Organization Chart that Fig. 2 and Fig. 4, Fig. 4 are the present invention the first specific embodiment.As shown in Figure 4, this adaptive dormancy control module 4, including secondary processor 40 and an auxiliary connectivity port 42.This auxiliary connectivity port 42 is via this JTAG connectivity port 20 of JTAG connecting element a2 this computer system 2 external.One memory body (figure does not indicates) of this secondary processor 40 stores one and wakes up data 400 up.Wherein, this secondary processor 40 not necessarily combines with this computer system 2, thereby further increases the bullet arranged.
Refer to Fig. 5, for the adaptive dormancy control module schematic appearance of the present invention the first specific embodiment.As it is shown in figure 5, this secondary processor 40 and this auxiliary connectivity port 42 are arranged on an identical auxiliary printing circuit board 44.This JTAG connectivity port 20, this central processing unit 22, this memory main body 26 and this non-volatility memory 28 are all arranged on this identical printed circuit board (PCB) 32.Further, this auxiliary connectivity port 42 connects one end of this JTAG connecting element a2, and this JTAG connectivity port 20 connects the other end of this JTAG connecting element a2.
Thereby, this research staff under the original design of printed circuit board (PCB) 32 not changing this computer system 2, can realize quick turn-on function and the dormancy control function of this computer system 2 via this adaptive dormancy control module 4 external.
Referring to Fig. 2, Fig. 4 and Fig. 6, Fig. 6 is the adaptive dormancy control method flow chart of the present invention the first specific embodiment.The inventive method comprises the steps of
Step S600: detect whether that receiving this dormancy triggers signal.Specifically, this secondary processor 24 detects whether that receiving this dormancy from this trigger element 30 triggers signal.If this secondary processor 24 receives this dormancy and triggers signal, then perform step S602, otherwise repeat this step S600 persistently to detect.
Step S602: send this dormant control signal to this central processing unit 2.Specifically, this secondary processor 24 sends this dormant control signal to this central processing unit 22 of this computer system 2 via this JTAG connecting element a1 and this JTAG connectivity port 20, to perform this dormancy program via to the control of this central processing unit 22.
Step S604: back up the current state of this computer system 2 and close this computer system 2.Specifically, this central processing unit 22 backs up the current state of this computer system 2 according to this dormant control signal, and closes this computer system 2 so that this computer system 2 enters this park mode.
Step S606: detect whether to receive this wake up trigger signal.Specifically, this secondary processor 24 detects whether to receive this wake up trigger signal from this trigger element 30.If this secondary processor 24 receives this wake up trigger signal, then execution step S608 is so that this computer system 2 leaves this park mode, otherwise repeats this step S606 persistently to detect.
Step S608: obtain this and wake up data 240 up.
Step S610: send this and wake up control signal up and this wakes up data 240 up to this central processing unit 22.Specifically, this secondary processor 24 sends this via this JTAG connecting element a1 and this JTAG connectivity port 20 and wakes up control signal up and this wakes up data 240 up to this central processing unit 22 of this computer system 2, to perform this wake up procedure via to the control of this central processing unit 22.
Step S612: make this computer system 2 recover to performing the state before this dormancy program.Specifically, this central processing unit 22 wakes up control signal up according to this and this wakes up data up and makes this computer system 2 recover to the state of (before i.e. performing this step S602) before performing this dormancy program.So far, this computer system 2 can be left this park mode and reach quick turn-on function.
Referring to Fig. 2, Fig. 4 and Fig. 7, Fig. 7 is the adaptive dormancy control method flow chart of the present invention the second specific embodiment.The inventive method comprises the steps of
Step S700: detect whether that receiving this dormancy triggers signal.If this secondary processor 24 receives this dormancy and triggers signal, then perform step S702, otherwise repeat this step S700 persistently to detect.
Step S702: send this dormant control signal to this central processing unit 22.
Step S704: this central processing unit 22 receives this dormant control signal.
Step S706: back up this status data 206 to this non-volatility memory 28.Specifically, this central processing unit 22 according to this secondary processor 24 control (i.e., content according to this dormant control signal), this status data 206 being stored in this access data address of this memory main body 26 is backed up to this mapping position of this non-volatility memory 28, using as these Status of Backups data 260 '.
Step S708: close this computer system 2.Specifically, this central processing unit 22 is shut down computer system 2 according to this dormant control signal, so that this computer system 2 enters this park mode.
Step S710: detect whether to receive this wake up trigger signal.If this secondary processor 24 receives this wake up trigger signal, then perform step S712, otherwise repeat this step S710 persistently to detect.
Step S712: obtain this and wake up data 240 up.
Step S714: send this and wake up control signal up and this wakes up data 240 up to this central processing unit 22.
Step S716: this central processing unit 22 receives this and wakes up control signal up and this wakes up data 240 up.
Step S718: start this computer system 2.Specifically, this wakes up data 240 up and includes should this scratch memory data address of central processing unit 22.This central processing unit 22 wakes up control signal and this scratch memory data address up according to this and recovers normal operation, and wakes up control signal up according to this and make other devices of this computer system 2 resume operation.
Step S720: read this Status of Backups data 260 ', and be loaded into this memory main body 26.Specifically, this wakes up data 240 up and also includes this access data address and this mapping address of this non-volatility memory 28 of this memory main body 26.This central processing unit 22 wakes up control signal up according to this and this wakes up data 240 up, this Status of Backups data 260 ' are read from this mapping address of this non-volatility memory 28, and it is loaded into these Status of Backups data 260 ' to this access data address of this memory main body 26, using as this status data 260.So far, this computer system 2 can be left this park mode and realize quick turn-on function.
The present invention performs dormancy program and wake up procedure via the central processing unit replaced in computer system with secondary processor, computer system can be made to realize quick turn-on function, and quick turn-on function can be made to be applicable to different types of central processing unit under the situation not revising operating system or startup program.
In other words, the present invention is not necessary to, according to the type of central processing unit, operating system or startup program are customized amendment, both the computer system of different types of central processing unit can be used all to realize quick turn-on function by secondary processor order, and then effectively shorten the system research and development time.
Certainly; the present invention also can have other various embodiments; in the case of without departing substantially from present invention spirit and essence thereof; those of ordinary skill in the art are when making various corresponding change and deformation according to the present invention, but these change accordingly and deform the protection domain that all should belong to appended claims of the invention.
Claims (14)
1. a computer system, it is characterised in that this computer system includes:
One JTAG connectivity port；
One central processing unit, is electrically connected with this JTAG connectivity port；And
One secondary processor, connects this JTAG connectivity port, have to should central processing unit one wake up data up；
Wherein, this secondary processor sends a dormant control signal to this central processing unit in time receiving a dormancy and trigger signal, a dormancy program is performed by the control of this central processing unit, this dormancy program includes backing up the current status data of this computer system and closing this computer system, and this secondary processor in receive a wake up trigger signal send one wake up up control signal and this wake up data up to this central processing unit time, a wake up procedure is performed by the control of this central processing unit is waken up up data according to this, this wake up procedure includes making this computer system to recover to performing the state before this dormancy program.
2. computer system as claimed in claim 1, it is characterised in that further include:
One memory main body, is electrically connected with this central processing unit, stores this status data；And
One non-volatility memory, is electrically connected with this central processing unit；This secondary processor backs up this status data to this non-volatility memory using as Status of Backups data in time performing this dormancy program, and in time performing this wake up procedure, wake up data up according to this and read this Status of Backups data from this non-volatility memory, and be loaded into this memory main body using as this status data.
3. computer system as claimed in claim 2, it is characterized in that, this wakeup packet include to should a scratch memory data address of central processing unit, an an access data address and mapping address of this non-volatility memory of this memory main body, wherein this mapping address is corresponding to this access data address.
4. computer system as claimed in claim 3, it is characterized in that, this secondary processor is in time performing this wake up procedure, this central processing unit is made to operate according to this scratch memory data address and start this computer system, and read this Status of Backups data from this mapping address of this non-volatility memory, and it is loaded into this access data address of this memory main body.
5. computer system as claimed in claim 3, it is characterised in that this wakes up data up is a text file or one or two meta files；This wakes up data up and is stored in a memory body of this secondary processor, this non-volatility memory or connects an external memory of this central processing unit.
6. computer system as claimed in claim 1, it is characterised in that this JTAG connectivity port connects one end of a JTAG connecting element, and this secondary processor connects the other end of this JTAG connecting element；Joint test work group technology supported by this central processing unit.
7. computer system as claimed in claim 1, it is characterised in that further including a trigger element, connect this central processing unit or this secondary processor, this trigger element produces this dormancy in time accepting peripheral operation and triggers signal or this wake up trigger signal.
8. an adaptive dormancy control module, it is characterised in that this adaptive dormancy control module includes:
One auxiliary connectivity port, connects a JTAG connectivity port of a computer system via a JTAG connecting element, and wherein this JTAG connectivity port is electrically connected with a central processing unit of this computer system；And
One secondary processor, is electrically connected with this auxiliary connectivity port, have to should central processing unit one wake up data up；
Wherein, this secondary processor transmits a dormant control signal to this central processing unit in time receiving a dormancy and trigger signal, a dormancy program is performed by the control of this central processing unit, this dormancy program includes the current state backing up this computer system and closes this computer system, and this secondary processor transmits one in time receiving a wake up trigger signal and wakes up control signal up and this wakes up data up to this central processing unit, a wake up procedure is performed by the control of this central processing unit is waken up up data according to this, this wake up procedure includes making computer system to recover to performing the state before this dormancy program.
9. an adaptive dormancy control method, it is characterised in that this adaptive dormancy control method comprises the following steps:
A) secondary processor sends a central processing unit of a dormant control signal a to computer system in time receiving a dormancy and trigger signal and comes, and performs a dormancy program by the control of this central processing unit；
B) this central processing unit backs up the current state of this computer system according to this dormant control signal and cuts out this computer system；
C) this secondary processor obtain in time receiving a wake up trigger signal to should computer system a central processing unit one wake up data up；
D) send one and wake up control signal up and this wakes up data up to this central processing unit, perform a wake up procedure by the control of this central processing unit is waken up up data according to this；And
E) this central processing unit wakes up control signal up according to this and this wakes up data up and makes this computer system recover to performing the state before this dormancy program.
10. adaptive dormancy control method as claimed in claim 9, it is characterised in that this step b comprises the following steps:
B1) this dormant control signal is received；
B2) status data a to non-volatility memory of this computer system it is stored according to the backup of this dormant control signal, using as Status of Backups data；And
B3) this computer system is closed according to this dormant control signal.
11. adaptive dormancy control methods as claimed in claim 10, it is characterised in that this step e comprises the following steps:
E1) receive this and wake up control signal up and this wakes up data up；
E2) wake up control signal up according to this and this wakes up data up and starts this computer system；And
E3) wake up control signal up according to this and this wakes up data up and reads this Status of Backups data from this non-volatility memory, and be loaded into a memory main body of this computer system, using as this status data.
12. adaptive dormancy control methods as claimed in claim 11, it is characterised in that this wakeup packet includes should a scratch memory data address of central processing unit；This step e2 is to make this central processing unit operate according to this scratch memory data address and start this computer system.
13. adaptive dormancy control methods as claimed in claim 11, it is characterised in that this wakeup packet includes access data address and a mapping address of this non-volatility memory of this memory main body, and wherein this mapping address is to accessing data address；This step e3 is that this mapping address from this non-volatility memory reads this Status of Backups data, and is loaded into this access data address of this memory main body.
14. adaptive dormancy control methods as claimed in claim 9, it is characterised in that this wakes up data up is a text file or one or two meta files.
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| CN113127087A (en) * | 2020-07-27 | 2021-07-16 | 虹光精密工业（苏州）有限公司 | Affair machine with intelligent dormancy awakening function and control method thereof |
| US20220413047A1 (en) * | 2021-06-28 | 2022-12-29 | Silicon Motion, Inc. | Method and apparatus and non-transitory computer-readable storage medium for debugging solid-state disk (ssd) device |
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| US20080016374A1 (en) * | 2006-07-13 | 2008-01-17 | International Business Machines Corporation | Systems and Methods for Asymmetrical Performance Multi-Processors |
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