JPH08101788A - Method and device for memory operation management - Google Patents

Abstract

PURPOSE: To provide the method and device for memory operation management which manage the erase operation in a flash memory to shorten the end time of the erase operation. CONSTITUTION: A CPU 2 executes various program processings corresponding to various application programs and executes a flash memory write request processing program for the purpose of outputting a data write request command to a flash memory driver 3 at need in the middle of execution of various program processings and makes the flash memory driver 3 start the erase operation of the flash memory 4 and returns the processing right to a higher-order application program by issue of an erase command to advance the higher-order application program processing to the next step.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory operation management method and a memory operation management device for speeding up an erase operation of a flash memory.

[0002]

2. Description of the Related Art Conventionally, a disk system such as a hard disk device has been generally used as an auxiliary storage device of a main storage device. However, since it takes a long operation time to access, there is a demand for an auxiliary storage device that operates at a higher speed. It is rising. To meet this demand, DRAM (Dyna
mic Random Accesses Memory), SRAM (Static Ra
A semiconductor disk device using a semiconductor memory such as an n-dom access memory or a flash memory has been put into practical use.

In particular, a flash memory does not require a battery backup for holding data like a DRAM and can be highly integrated as compared with a DRAM, so that a large capacity can be realized and a hard disk or a floppy disk can be replaced. It is possible.

When a data write request to this flash memory occurs, if there is a free area (area in which data is not written), the write operation can be executed immediately in a predetermined block unit. When data has been written and is to be overwritten, the area where the data has been written is once erased in block units, and then the write operation is performed.

[0005]

However, in such a conventional flash memory as a semiconductor disk device, when a data write request occurs and data has already been written and is overwritten, Since the write operation was performed after performing the erase operation on the area where data was written in block units, if the area to erase data is large, it takes time to complete the erase operation. There is a problem in that the interruption time of the upper program processing that has generated the data write request is prolonged and the processing speed of the upper program is reduced.

An object of the present invention is to provide a memory operation management method and a memory operation management device for managing the erase operation in a flash memory and shortening the end time of the erase operation.

[0007]

According to the first aspect of the present invention,
In a memory operation management method for managing a progress state of an erase operation in a memory that requires an erase operation in units of a predetermined storage area in response to a data write request, data management information for managing a data expansion state for each storage area is provided. Set,
When a data write request is generated by the upper program processing, the data management information is referred to, the storage area that requires the erase operation is determined and the erase operation is started, and when the erase operation is started, the upper program processing is performed. The processing authority is returned to, the erase operation is executed in parallel, and after the information is issued, the progress status of the erase operation is regularly monitored to set and update the erase operation management information.
It is characterized in that the progress state of the erase operation in the memory is managed.

According to a second aspect of the present invention, there is provided a memory operation management method for managing a progress state of an erase operation in a memory which requires an erase operation in units of a predetermined storage area in response to a data write request. When the data management information that manages the data expansion state is set and a data write request is generated by a higher-order program process, the data management information is referenced to determine the storage area that requires the erase operation, and the erase operation is performed. When the erase operation is started, the processing authority is returned to the upper program processing at the same time as the start of the erase operation, the erase operation is executed in parallel, and the operation state after the start of the erase operation is periodically performed as an interrupt process of the upper program processing. To monitor and set the update operation management information and manage the progress of the erase operation in the memory. It is a symptom.

According to a third aspect of the present invention, in a memory operation management device for managing a progress state of an erase operation in a memory that requires an erase operation in units of a predetermined storage area in response to a data write request, each memory area is managed. A data management information storage unit that stores data management information that manages a data expansion state, an operation management information storage unit that stores the erase operation management information that manages the erase operation, and a data write request by a higher-order program process. Then, by referring to the data management information, the memory area requiring the erase operation is determined and the erase operation is started, and at the same time, the processing authority is returned to the higher-order program processing to execute the erase operation in parallel. , Periodically monitoring the operation state after the start of the erase operation, and setting and updating the erase operation management information in the operation management information storage means. It is characterized by comprising a memory operation management means.

Further, in this case, as described in claim 4, the memory operation management means executes periodical monitoring of an operation state after the start of the erase operation as an interrupt processing of the upper program processing. Is effective.

[0011]

According to the first aspect of the present invention, in the memory operation management method for managing the progress state of an erase operation in a memory which requires an erase operation in units of a predetermined storage area in response to a data write request, the storage area Data management information for managing the expansion state of data is set for each, and when a data write request is generated by a higher-level program processing, the data management information is referred to determine the storage area that requires an erase operation and the data is erased. The operation is started, the processing authority is returned to the higher-order program processing at the start of the erase operation, the erase operation is executed in parallel, and after the issuance of the information, the progress status of the erase operation is periodically performed. The erase operation management information is monitored and set and updated to manage the progress of the erase operation in the memory.

Therefore, it is possible to shorten the waiting time until the completion of the erasing operation in the memory during the execution of the upper program processing, and it is possible to speed up the upper program processing.

According to a second aspect of the present invention, in the memory operation management method for managing the progress state of the erase operation in a memory that requires an erase operation in units of a predetermined storage area in response to a data write request, the storage area Data management information for managing the expansion state of data is set for each, and when a data write request is generated by a higher-level program processing, the data management information is referred to determine the storage area that requires an erase operation and the data is erased. When the erase operation is started, the operation authority is returned to the upper program processing at the same time as the start of the erase operation, the erase operation is executed in parallel, and the operation state after the erase operation is started as an interrupt processing of the upper program processing. Is regularly monitored to set and update the erase operation management information and manage the progress of the erase operation in the memory.

Therefore, it is possible to shorten the waiting time until the completion of the erasing operation in the memory during execution of the upper program processing, and to surely grasp the progress state of the erasing operation in the memory by the upper program side, so that the upper program processing The speed can be increased.

According to a third aspect of the present invention, in the memory operation management device for managing the progress state of the erase operation in the memory which requires the erase operation in units of a predetermined storage area in response to the data write request, the storage area Data management information for managing the expansion state of data for each is stored in the data management information storage means, erasing operation management information for managing the erasing operation is stored in the operation management information storage means, and a data write request is made by a higher-order program process. When an error occurs, the memory operation management unit refers to the data management information to determine the storage area that needs the erase operation, starts the erase operation, and returns the processing authority to the higher-order program processing, The erasing operation is executed in parallel, the operating state after the erasing operation is started is regularly monitored, and the erasing operation is stored in the operation management information storage means. To set up and update the management information.

Therefore, it is possible to shorten the waiting time until the completion of the erase operation in the memory during the execution of the upper program processing, and it is possible to provide the memory operation management device which accelerates the upper program processing.

According to the fourth aspect of the present invention, the memory operation management means executes the periodical monitoring of the operation state after the start of the erase operation as the interrupt processing of the upper program processing. The progress state of the erasing operation can be surely grasped by the upper program side.

[0018]

EXAMPLES Examples will be described in detail below with reference to FIGS. 1 to 17 are diagrams showing an embodiment in which the present invention is applied to a computer system using a flash memory by a DOS system. First, the configuration will be described. FIG. 1 is a diagram showing a block configuration of a computer system 1. In this figure, a computer system 1 is composed of a CPU 2, a flash memory driver 3, a flash memory 4, a flash memory management memory 5, a flash memory power supply 6 and an interval timer 7.

CPU (Central Processing Unit) 2
Executes various program processes according to various application programs operating based on a DOS (Disk Operating System) system, and issues a data write request command to the flash memory driver 3 as necessary during execution of the various program processes. In order to output, the flash memory write request processing program to be described later is executed, the flash memory driver 3 starts the erase operation for the flash memory 4, and the erase command is issued to give the processing authority to the upper application program. Then, the process of the upper application program is advanced to the next step.

After starting the erase operation, the CPU 2 activates the interval timer 7 and executes a timer interrupt process, which will be described later, in response to an interrupt request input at a predetermined interval each time the interval timer 7 times up. Then, the progress state of the erase operation in the flash memory 4 is checked by the flash memory driver 3.

The flash memory driver 3 has a CPU 2
When a data write request command generated by various higher-order application program processes executed in step S6 is input, a dirty sector cleanup process, which will be described later, is set in the flash memory management memory 5, and free sector management information and a block erase process described later are performed. Execute using information.

That is, in the cleanup process, the flash memory driver 3 manages whether the flash memory 4 is a block-based empty area (unused area) or dirty area (overwriting impossible and processed unnecessary data storage area). By setting and updating sector management information (data management information) and block erase information in the flash memory management memory 5, an erase operation for reconfiguring an empty area in which data is written in the flash memory 4 is executed. Then, after this erase operation is completed, the flash memory driver 3 refers to the allocation table information stored in the flash memory management memory 5 described later for the data write operation to the sector in the flash memory 4 for which the write request is made. Then run.

The flash memory driver 3 also transfers the timer start command input by the CPU 2 in the flash memory write request process to the interval timer 7 to start the interval timer 7. When the CPU 2 executes the timer interrupt process, it outputs a command for checking the progress of the erase operation to the flash memory 4, and stores it in the flash memory management memory 5 according to the status information returned from the flash memory 4. Change the setting of the erase management information in the block erase information to be set.

Further, the flash memory driver 3 is
When a data read request is input from the CPU 2 during execution of the erase operation, a flash memory read request process described below is executed, the erase operation is interrupted, and the read process of the data requested to be read is performed. Restart the erase operation.

As shown in FIG. 2, the flash memory 4 includes, for example, a bank No. having a storage capacity of 64 kbytes as one unit. The data storage area into which data is actually written, divided by (bank 00 to bank 31), and the data content written in this data storage area are stored in the bank number.
A management information storage area that stores block management information that is managed for each is formed. This management information storage area corresponds to each bank No. of the data storage area. Corresponding to the logical block ID No. (ID00 to ID31) are set and divided, and information for managing the entire management area and data area in the flash memory 4 is stored in the area "ID00".

In FIG. 2, "ID01 to ID29" in the management information storage area designates a bank N for designating an empty area when writing data in the data storage area in units of banks.
o. To form a data area for storing the ID No. of each data area, as indicated by an arrow in the figure. Bank No. Are dynamically assigned. Further, a "DOS management area" for storing management information (for example, directory information or FAT information) necessary for the DOS system is formed in "ID30" of the management information storage area, and a bank of the data storage area is formed in "ID31". When forming a vacant area in each sector, the data of the required sector is saved and an erasing area for reconfiguring a new data storage area including the vacant sector is formed, and the storage capacity for one block is increased. Have.

The flash memory management memory 5 is shown in FIG.
Block erase information is stored as shown in FIG. The block erase information is management information for managing the erase operation in the flash memory 4, and has a 5-byte length.
Erase management information is stored in the first 1-byte portion, and block ID information (block ID shown in FIG. 2 is stored in the next 2-byte portion.
No. ) Is stored and the bank number. Information (bank No. position information shown in FIG. 2) is stored. In the erase management information, each bit of the 8-bit configuration is set as shown in the figure. For example, bit 0 is for high speed erase execution request setting, bit 1 is for high speed erase execution wait setting, and bit 2 is high speed. For setting during erase execution, bit 3 for setting high speed erase execution interrupt request, bit 4 for setting high speed erase ID write request, bit 5 not set, bit 6 for normal erase execution request setting, bit 7
Is for setting the format erase execution request. When each bit is set to "1", it indicates that each operation and request is in progress.

Therefore, the flash memory driver 3 changes the block erase information in accordance with the progress of the erase operation, thereby managing the progress of the erase operation.

The flash memory management memory 5 also stores empty sector management information, as shown in FIG. The free sector management information is management information used when the flash memory driver 3 executes the cleanup processing, and each free sector management information is stored in the flash memory 4. Corresponding to the ID No. Control information (ID00-
ID 32) is stored. Each IDN
o. As shown in the figure, the control information has a 5-byte length, and the first 1-byte portion has a bank number. The next 2
Free area count information is linked to the byte portion and dirty area count information is linked and stored to the next two bytes.

Here, the empty area count information means the bank number. Is information indicating how many empty sectors are in the area, and the dirty area count information is the bank number. This is information indicating how many dirty sectors are in the area.

Further, the flash memory management memory 5
In the table, allocation table information is stored as shown in FIG. This allocation table information is management information for managing the data expansion state of the entire flash memory 4, and forms an information storage area divided by logical sectors 0 to n (n: last sector), and is stored in each information storage area. Is
Area pointer No. for managing the sector position where the data in the flash memory 4 is written. And the block ID including the sector position is linked and stored. Specifically, the area pointer table (link pointer N that is actually stored in the flash memory 4 shown in FIG.
o. And block ID) and information obtained by copying the information (Next link pointer and block ID) indicating the link relationship of the data expanded in the data area are stored.

The flash memory power supply 6 is a power supply for supplying the drive voltage Vpp necessary for the erasing operation of the flash memory 4, and the drive voltage Vpp is supplied or stopped by the power ON / OFF signal input from the flash memory driver 3. Controlled.

The interval timer 7 is a timer that sets a timing for outputting an interrupt request for causing the CPU 2 to execute a timer interrupt process, and is activated by a timer activation command input from the flash memory driver 3.

Next, the operation will be described. First, the CPU
The flash memory write request processing executed by No. 2 will be described based on the flowchart of FIG. CP
In U2, when a write request to the flash memory 4 is generated during application program processing, the flash memory write request processing is started and it is determined whether or not there is a free sector in the flash memory 4 via the flash memory driver 3. Judging from the free sector management information stored in the management memory 5 (step S1), if there is a free sector, a data write command to the designated sector is output to the flash memory driver 3 and the flash memory 4 The write operation to is started (step S2).

Then, at the time of writing data in the designated sector, whether or not the data in the designated sector needs to be erased is referred to by the erase management information set in the block erase information stored in the flash memory management memory 5. (Step S3). If erasing is not necessary, this process is terminated, and if erasing is necessary, a power ON command is output to the flash memory power supply 6 via the flash memory driver 3 to output the erasing drive voltage Vpp to the flash memory 4. Then, the erase operation is started (step S4).

Then, an erase command is issued (step S5), a timer start command is output to the interval timer 7 via the flash memory driver 3, and the interval timer 7 is started (step S6).
This process ends.

If it is determined in step S1 that there are no free sectors, the flash memory driver 3 executes a clean-up process for dirty sectors (step S7).

Now, the dirty sector cleanup processing executed by the flash memory driver 3 will be described with reference to FIGS. First, before performing the cleanup processing, the block ID No. Of the corresponding block ID No. stored in the flash memory management memory 5. The empty sector management information of, for example, the empty sector management information shown in FIG. The free sector management information in FIG. 7 is
The management information of the block IDl is the bank N of the data storage area.
o. Corresponding to m, the empty area count information is "0" (indicating that there is no empty sector) and the dirty area count information is "n" (n dirty areas).

FIG. 8 shows a concrete data development state in the block ID1 before the cleanup process. In FIG. 8, an area pointer table indicating the data expansion state of the entire block IDl is stored in the head sector. In this area pointer table, the start pointer of the data stored in sector A and the area stored in sector B are stored. A start pointer of data to be stored and a start pointer of data to be stored from the sector C are stored.

The shaded area in the drawing indicates a dirty sector (a storage area for unprocessed unnecessary data that cannot be overwritten). At the beginning of each dirty sector, there are a sector A, a sector B, and a sector C including a start pointer. The link pointers of the sectors to be linked are stored. In the figure, the data linked to the sector A is shown by a solid line, the data linked to the sector B is shown by a chain line, and the data linked to the sector C is shown by a dotted line. Of the data linked to each sector A, B, and C, the data of the last sector shown in the figure is the data that has been finally processed in the process using each sector data, and therefore the data to be erased, that is, , Does not become a dirty sector.

When the cleanup process is executed for such a block IDl, as shown in FIG. 9, the erase area of the block ID31 in the management information storage area of the flash memory 4 shown in FIG. The necessary data of the last sectors A, B, and C shown in FIG. 2 are saved in a packed state, and each start pointer data of the saved sectors is stored in the first sector as an area pointer table to reconstruct the contents of the block IDl. As a result, as shown in the figure, an empty area for n sectors corresponding to the bank O is formed, and the cleanup process is completed.

As described above, the flash memory driver 3
When the clean-up process by the process is finished, the process returns to step S8 of FIG. 6 again, and as shown in FIG.
The free sector management information of D31 is set, the data write request command for the free area of the reconfigured designated sector is output to the flash memory driver 3, and the write operation to the flash memory 4 is started (step S
9). Then, the processes in and after step S3 are executed.

Next, the timer interrupt processing executed by the CPU 2 each time the interrupt request command generated by the interval timer 7 at the set time interval is output to the CPU 2 by the activation of the interval timer 7 in step S6. This will be described based on the flowchart shown in FIG.

When an interrupt request command is input from the interval timer 7, timer interrupt processing is started, and it is confirmed via the flash memory driver 3 whether or not the flash memory 4 is in the erase operation (step S1).
1). If the erasing operation is not in progress, this processing is immediately terminated, and if the erasing operation is in progress, a status read command is output to the flash memory driver 4 to confirm the operating state of the flash memory 4 (step S12), and the flash memory The status returned by the driver 4 determines whether or not the erase operation is completed (step S
13). If the erase operation has not been completed, this processing is terminated, and if the erase operation has been completed, the flash memory power supply 6 is powered on via the flash memory driver 3.
The FF signal is output to stop the supply of the erasing drive voltage Vpp to the flash memory 4 (step S14).

Then, a timer stop command is output to the interval timer 7 via the flash memory driver 3 to stop the interval timer 7 (step S15), and is stored in the flash memory management memory 5 of the block for which erasing has been completed. The erased block information is cleared (step S16), and this processing ends. The processing time of the timer interrupt processing described above is performed in a very short time of the order of μsec compared to the main application processing time, and therefore the application processing time in the CPU 2 is not prolonged.

The relationship between the operations of the CPU 2 and the flash memory driver 3 with respect to the flash memory 4 by the above flash memory write request processing and timer interrupt processing is as shown in FIG. 12, and the application processing of the CPU 2 and the flash memory driver by the generation of the erase command. The erase operation executed under the control of No. 3 is performed in parallel. Therefore, the CPU 2 can reduce the time to wait for the completion of the erase operation of the flash memory 4 after the write request command is generated, and reduce the processing time by the upper application program. As a result, higher-speed application program processing executed by the CPU 2 can be speeded up.

Next, a data writing process performed on the empty sector reconstructed in FIG. 9 after the above cleanup process is completed will be described with reference to FIGS. 13 to 16. FIG. 13 shows a case where data is written as data to be linked to the sector A in the empty sector reconfigured in the block ID1 (bank O) of FIG.

As a result of this writing, in FIG. 13, the portion which was the final data of the sector A before writing is made a dirty sector (hatched portion in the drawing), and the link pointer is set at the head of the dirty sector. Then, the free sector management information stored in the flash memory management memory 5 corresponding to this block IDl is changed as shown in FIG. That is, the free area count is "n"
To "n-1" and the dirty area count is changed from "0" to "1".

After this data writing is completed, the block ID 3 which is the erasing area in the cleanup process.
In order to erase the contents expanded to 1, the block erase information stored in the flash memory management memory 5 is set as shown in FIG. In this case, the high speed erase execution request is set as the erase management information (bit 0 shown in FIG. 3 is set to "1"), and the block ID1 and the bank number. By setting m, the data erasing process based on the erasing operation is executed, and the block ID 31
Delete the contents expanded to.

When the erase operation for the block ID 31 is completed, the free sector management information of the block ID 31 is changed to the setting shown in FIG. That is, the bank number. Is changed to "m", the empty area count is changed to "0", and the dirty area count is changed to "0".

Next, after issuing the erase command, if a data read request to the flash memory 4 is issued from a higher-order application program process while the erase operation is continuing in the flash memory 4, it is executed in the flash memory driver 3. The flash memory read request process will be described based on the flowchart shown in FIG.

After the erase command is issued, when the data read request command to the flash memory 4 from the upper application program processing of the CPU 2 is input to the flash memory driver 3 while the erase operation is continuing in the flash memory 4, the flash memory read is performed. The request process is started, and it is determined whether or not erasing is in progress by referring to the block erasing information stored in the flash memory management memory 5 (step P1). If not erasing, step P
If it is in the process of erasing, the erase suspending command is issued to the flash memory 4 (step P2) to suspend the erase operation.

Then, in step P3, the data read processing is executed, the read command for reading the data of the designated sector from the flash memory 4 is output to the flash memory 4, and the data of the designated sector responded from the flash memory 4 is transferred to the CPU 2. To do. Then, when the data reading is completed, a command for reading the status of the flash memory 4 is output to the flash memory 4, and it is judged from the status returned from the flash memory 4 whether or not the erase operation is stopped (step P4). If the erase operation is not stopped, this processing is terminated. If the erase operation is stopped, an erase operation restart command is issued (step P5) to restart the erase operation in the flash memory 4 and execute the main operation. The process ends.

By performing the flash memory read request process in the flash memory driver 3 as described above, even when the application program process after the erase command is issued and the erase operation are performed in parallel,
It becomes possible to suspend and continue the erase operation in response to the read request of the application program processing.

Further, in the above embodiment, the monitoring of the erase operation in the flash memory 4 after issuing the erase command is performed by CP.
Since it is executed as the U2 timer interrupt process, the CPU 2 can surely grasp the progress state of the erase operation in the flash memory 4 even when the CPU 2 is executing the upper application program process.

[0056]

According to the first aspect of the present invention, it is possible to shorten the waiting time until the completion of the erase operation in the memory during the execution of the upper program processing, and it is possible to speed up the upper program processing.

According to the second aspect of the present invention, the waiting time until the completion of the erase operation in the memory during the execution of the upper program processing can be shortened, and the progress of the erase operation in the memory can be surely performed on the upper program side. By grasping the information, it is possible to speed up the upper-level program processing.

According to the third aspect of the present invention, there is provided a memory operation management device capable of shortening the waiting time until the completion of the erase operation in the memory during the execution of the upper program processing and accelerating the upper program processing. be able to.

According to the fourth aspect of the invention, the upper program side can surely grasp the progress state of the erase operation in the memory.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of a computer system to which the present invention is applied.

FIG. 2 is a diagram showing a configuration in the flash memory of FIG.

3 is a diagram showing a data structure of block erase information stored in a flash memory management memory shown in FIG. 1;

FIG. 4 is a diagram showing a data structure of free sector management information stored in a flash memory management memory shown in FIG. 1;

5 is a diagram showing a data structure of allocation table information stored in the flash memory management memory shown in FIG. 1;

FIG. 6 is a flowchart of flash memory write request processing executed by the CPU of FIG.

7 is a diagram showing an example of free sector management information set by the cleanup process of FIG. 6;

8 is a diagram showing an example of a data expansion state of a block unit in a flash memory corresponding to the free sector management information of FIG.

9 is a diagram showing a state in which the data of FIG. 8 is reconfigured in the erase area of FIG. 2 by the cleanup processing of FIG. 6 to form empty sectors.

10 is a diagram showing a configuration of free sector management information corresponding to the data of FIG.

11 is a flowchart of timer interrupt processing executed by the CPU of FIG.

12 is a diagram showing an operational relationship between a flash memory write request process and a cleanup process executed by the CPU and the flash memory driver of FIG.

13 is a diagram showing a state in which data is written in an empty sector of the memory shown in FIG. 9.

14 is a diagram showing a configuration of free sector management information corresponding to the data of FIG.

15 is a diagram showing the configuration of block erase information when erasing the data expanded in the erase area of FIG.

16 is a diagram showing a configuration of free sector management information corresponding to an erase area after data is erased by the block erase information of FIG.

17 is a flowchart of a flash memory read request process executed by the flash memory driver of FIG.

[Explanation of symbols]

 1 Computer System 2 CPU 3 Flash Memory Driver 4 Flash Memory 5 Flash Memory Management Driver 6 Flash Memory Power Supply 7 Interval Timer

Claims (4)

[Claims] 1. A memory operation management method for managing a progress status of an erase operation in a memory that requires an erase operation in units of a predetermined storage area in response to a data write request, wherein a developed state of data is managed for each storage area. When the data write request is generated by the higher-order program processing, the data management information is set, the memory area requiring the erase operation is determined, the erase operation is started, and the erase operation is performed. With the start of the operation, the processing authority is returned to the higher-order program processing, the erase operation is executed in parallel, and after the information is issued, the progress status of the erase operation is regularly monitored to display the erase operation management information. A memory operation management method, characterized in that setting and updating are performed to manage a progress state of an erase operation in the memory. 2. A memory operation management method for managing a progress status of an erase operation in a memory that requires an erase operation in units of a predetermined storage area in response to a data write request, wherein a developed state of data is managed for each storage area. When the data write request is generated by the higher-order program processing, the data management information is set, the memory area requiring the erase operation is determined, the erase operation is started, and the erase operation is performed. The processing authority is returned to the upper program processing at the same time as the start of the erase operation, the erase operation is executed in parallel, and the operation state after the start of the erase operation is periodically monitored as the interrupt processing of the upper program processing and erased. The operation management information is set and updated, and the progress of the erase operation in the memory is managed. Memory operation management method. 3. A memory operation management device for managing a progress status of an erase operation in a memory which requires an erase operation in units of a predetermined storage area in response to a data write request, wherein a developed state of data is managed for each storage area. Data management information storage means for storing data management information, operation management information storage means for storing erase operation management information for managing the erase operation, and the data management information when a data write request is generated by a higher-order program process. The erasing operation is started by determining the storage area that requires the erasing operation with reference to, and the processing authority is returned to the upper program processing,
Memory operation management means for executing the erase operation in parallel, periodically monitoring the operation state after the start of the erase operation, and setting and updating the erase operation management information in the operation management information storage means. And a memory operation management device. 4. The memory operation management unit according to claim 3, wherein the memory operation management unit executes periodical monitoring of an operation state after the start of the erase operation as an interrupt process of the upper program process. apparatus.