JPS6019821B2 - Serial data reception method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a serial data receiving system in a system in which a local address and data are serially transmitted from a terminal device to a central processing unit.

When a plurality of terminal devices are connected to a central processing unit, a configuration is usually adopted in which one terminal device is connected to each terminal of an input port of the central processing unit.

In such a system, since the terminal device can be identified by the input terminal, there is no need to transmit an address from the terminal device, and only data is transmitted serially. In this case, the central processing unit CPU has a first
It has a receive buffer as shown in the figure.
In FIG. 1, the received serial data is stored in a buffer B4 and converted into parallel data. Converted data is transferred to thief buffer B3, B2, B
The interrupt signal INT is generated when the data is sequentially sent to the receiver buffer BI and stored in the receiver buffer BI. Receipt B
The next data received until the stored data is input to the CPU is stored in 82. When the CPU inputs data from the receiver buffer BI, the data from B2 is sent to BI, and an interrupt signal mT is generated again. In this way, the reception of serial data and the input to the CPU are performed asynchronously, and the data waiting to be input is sequentially stored in the sheep buffers BI to B4. On the other hand, as the number of terminal devices increases, a system configuration is adopted in which a plurality of terminal devices are connected to one common transmission path extending from the CPU. In such a system, a terminal device attaches its own address to data and transmits the data to the CPU for terminal identification. Let us consider that serial data having this terminal identification address is received by the serial data receiving circuit shown in FIG.
First, when an address is stored in the receiver buffer BI, an interrupt signal T is generated. At this time, if the CPU accepts the interrupt and performs an immediate input, the BI becomes empty, and this state continues until the data being received is completed. After the data reception is finished and the data is sent from B4 to BI, the I
NT is generated and BI data is input. In this way, when data with a terminal identification address added is received by the circuit shown in Figure 1, an interrupt occurs each time the address and data are received, and interrupt processing must be performed each time, so the CPU Program processing is frequently interrupted by interrupt processing, resulting in poor efficiency. Also, since addresses and data are normally sent continuously, an interrupt will occur again within a short period of time, and once the CPU finishes the address reception interrupt processing and returns to the original program, the interrupt will occur again. Interrupt processing for data reception will be started, and essentially the same thing as one interrupt processing will be performed twice. As mentioned above, if the receive buffer of the central processing unit is shared for addresses and data, an interrupt always occurs when receiving an address and when receiving data, and interrupt processing must be performed when receiving an address and receiving data respectively. . At the time when an address is received, no data has been received yet, so no data processing can be performed, so the interrupt processing at the time of address reception is simply to save the received address. This saved address is processed together with the data only when an interrupt occurs later due to data reception, so it is only necessary to input it after data reception.
If the receive buffer is shared, an interrupt cannot be generated only for data reception. SUMMARY OF THE INVENTION An object of the present invention is to provide a reception method that enables efficient processing of serial data in which an address is added to the data.

In order to achieve the above object, the present invention is characterized in that addresses and data received by the CPU are stored in separate buffers, and an interrupt is generated when data is received.

FIG. 2 shows a serial data receiving circuit which is an embodiment of the present invention.

In this case, there are two completely identical sheep buffers ABI ~ 4.
and DBI~4~ address buffer ABI~AB
It is assumed that addresses are stored in 4 and data are stored in data buffers DBI to DB4, respectively. Serial data sent from the terminal device is sent to gates GI and G2.
input into the address buffer or data buffer. Gates GI and G2 are controlled by an address/data discrimination flip-flop 11. This flip-flop 11 determines whether it is currently receiving serial data, address, or data. At power-on and reset, this flip-flop is reset, and the gate G
I is open. Therefore, the first address sent is stored in address buffer AB4. When the reception of the address is completed, the flip-flop 11 is set,
Gate G2 opens. Therefore, the next data sent is stored in the data buffer DB4. The contents of AB4 are A
The contents of DB4 are sequentially transferred from B3 to AB2 to ABI, and the contents of DB4 are also sequentially transferred from DB3 to DB2 to DBI. When the address is stored in ABI and data in DBI in this way, an interrupt signal NT is generated through the data buffer side. do. On the other hand, the address buffer that stores the address does not have an interrupt signal generating means, or the interrupt signal is masked in advance so that the interrupt signal is not output even if the address is stored in the ABI. Therefore, due to the interrupt by the melon T on the data buffer side, the CP
U can input addresses from ABI and data from DBI. FIG. 3 shows the format of serial data consisting of addresses and data. Although the circuit of the present invention handles serial data in this format, it is not limited to this format as long as the address field and data field can be distinguished. FIG. 3 shows the case of 1-byte data transfer, where the address field and the data field are continuous with 1 stop bit. At least 2 stop bits are placed between the data field and the next address field.
It doesn't matter if it's more than a bit away. FIG. 4 shows an embodiment of a circuit that drives the address/data discrimination flip-flop 11 of FIG. 2 when the format of FIG. 3 is received.

Si, RXC correspond to FIG. 2, 12 is a counter circuit that counts the bit string of received data, 13 is a flip-flop circuit that is set during reception, 14 is a flip-flop circuit that is set at the end of data section reception, and 15 is a flip-flop circuit that is set at the end of receiving data. Inverter G3 is a two-input AND gate. Figure 5 is the 4th
The time chart shown in the figure describes the case where the format shown in FIG. 3 is received.

4. A is an inverted signal of the data in FIG. 3, and represents the data applied to the receive data input in FIG. b is the fourth
The output signals of the flip-flop circuit 13 in the figure, c and d are the output signals of the flip-flop circuit 14, and e and f are the output signals of the flip-flop circuit 11. First, when the start bit of the address section is given to a, the flip-flop circuit 13 is set in synchronization with CLOCK. b is “H”
When it becomes igH, gate G3 opens and RXC is sent out,
Thereafter, the data given to a is input to the buffer. The counter circuit 12 starts operating at the same time as the flip-flop circuit 13, counts the input data bits, and outputs d immediately before the end of the stop bit of the address section. d
As a result, the flip-flop 11 is set, the address section instruction is switched to the data section instruction, and the outputs e and f are inverted. The counter circuit 12 continues counting, and at the center of the bit position next to the stop bit, the sampling signal h
Output. In this case, the start bit of the data section is received after the stop bit, so a is “High.”
”, the output of the inverter 15 becomes “mountain w” and the flip-flop circuit 14 is not set.Counter circuit 1
2 is composed of a double counter, and while counting the bit following the stop bit, data counting is restarted from the start bit. Therefore, when counting again up to the stop bit of the data section, d is output, and furthermore, h is output at the center of the next bit after the stop bit. At this time, the stop bit state is maintained after the stop bit, and "mountain w'' is given to a. Therefore, the output of the inverter 5 becomes "High", and the flip-flop circuit 14 is set.Flip-flop circuit 14 is set, the flip-flop circuit 13
and flip-flop 11 is reset, and the next one to be received points to the address section. The flip-flop circuit 14 is reset by the reset signal g, and all the circuits return to their initial states. As described above, in the case of the format shown in FIG. 3, two consecutive characters of data can be stored in the first received address buffer AB' and the second received character in the data buffer DB.

As explained above, according to the present invention, ``Two sets of receive buffers are provided on the CPU side, only one of the receive buffers is provided with an interrupt generation function, and the address field and data field that arrive serially are separated. By storing it in the reception buffer, it sends an interrupt signal to the CPU when receiving data,
This allows the CPU to input data and an address already stored in another buffer at the same time.
Enables efficient processing.

[Brief explanation of drawings]

Fig. 2 is a block diagram showing a conventional example, and Fig. 2 is a block diagram showing a conventional example.
FIG. 3 is a block diagram showing a serial data receiving circuit according to an embodiment. FIG. 4 is a block diagram showing an example of a circuit that drives the flip-flop 11 in FIG. It is a time chart explaining Fig. 4. ABI~AB4...address buffer, DBI~DB
4...Data buffer! 1...Flip-flop, 12.
...Counter circuit, 13 and 14...Flip-flop circuit, 15...Inverter. Figure 3 Figure 2 Figure 4 Figure 5

Claims (1)

[Claims] 1. When multiple terminal devices are connected to a common transmission path extending from the central processing unit and data is transmitted from the terminal device to the central processing unit, the address of the own station is added to the beginning of the data, and the data is transmitted via the transmission path. In a system in which data is serially transmitted to a central processing unit, and each time an address or data is available in a reception buffer on the central processing unit side, an interrupt is generated and the address or data is taken in, two sets of reception buffers are provided on the central processing unit side. Then, only one of the receiving buffers is provided with an interrupt generation function, and among the addresses and data that arrive serially from the terminal device side via the common transmission path, the address is sent to the first receiving buffer, and the data is sent to the first receiving buffer. When the data is stored in the second receive buffer, an interrupt is generated, and the interrupt causes the data stored in the second receive buffer to be stored in the first receive buffer. A serial data reception method characterized by simultaneously capturing addresses already stored in the .