JPH0565894B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology for spatially dividing and using a microprocessor according to two or more modes.
For example, it is suitable for a device such as an in-circuit emulator having a system mode and an emulation mode.

[Background technology]

When developing software for a microcomputer system developed by a user, a device such as the one shown in FIG. 1 is sometimes used in a loose manner. That is, an MPU identical to the MPU of the system 1 is connected via a connector 3 to an IC socket 2 for a microprocessor (hereinafter referred to as MPU) provided on a board 1a that constitutes a microcomputer system (user system) 1. A built-in adaptive system evaluator (hereinafter referred to as ASE) 4 is connected. This ASE 4 is connected via a cable to a system development device 7 equipped with a CRT display 5, floppy disk devices 6a, 6b, and the like.

A source program written in a language such as an assembler or compiler that is entered from the keyboard of the CRT display 5 is first inputted from the floppy disk 6.
written to a, the MPU in the system development device 7
The program is translated into machine language and written to the floppy disk 6b in the form of an object program. The program written on the floppy disk 6b is transferred by the MPU in the ASE 4 to a RAM (random access memory) 8 or the like in the user system 1 and written therein.

The user program written to RAM8 etc.
When the connector 3 is pulled out from the IC socket 2 and the system's MPU 9 is inserted, normally the MPU 9 executes the operation, but in the device shown in Figure 1, the MPU in the ASE 4 (same type as the MPU 9) ), it is now possible to debug a user program while performing emulation.

In this case, data obtained by controlling the CRT display 5, floppy disk devices 6a, 6b, etc., translating assembler or compiler language into machine language, and executing user programs by the MPU in ASE4 Edit
An MPU for displaying on the CRT display 5 is provided in the system development device 7, but the in-circuit emulator is used to convert data obtained as a result of emulation into a format that is easy for the MPU in the system development device 7 to edit. for processing
MPU is required. Therefore, in order to make this MPU also serve as an MPU for user program emulation, it is necessary to spatially divide the MPU in ASE4 into emulation mode and system mode.

Normally, when such space division is performed, a halt request (stop command) from the user system is prevented from entering the MPU except during execution of emulation. However, this does not allow the user to e.g.
If you create a system in which the bus is released and dynamic memory can be refreshed only after a halt request is made to the MPU, the memory in the user system will not be refreshed except during emulation, and the memory There was an inconvenience in that the data inside was destroyed, or the user had to provide a countermeasure circuit.

[Purpose of the invention]

This invention was made against the above background, and for example, even when emulation is not being executed,
It can respond to requests from the user system without stopping the microprocessor.
As a result, it is an object of the present invention to provide an emulator that facilitates the user's system design and that can be applied to a wider range of subjects.

The above and other objects and novel features of the present invention will become apparent from the description of the present invention and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the present invention includes a state setting means that can be set in advance by a program, and a signal that can form a predetermined control signal based on an external input signal (halt signal) according to the setting state of the state setting means. The above object is achieved by providing a forming means and making it possible to output a desired control signal without stopping the microprocessor even if a halt signal is received.

The present invention will be explained below using the drawings.

〔Example〕

FIG. 2 shows an embodiment of the main part of the in-circuit emulator according to the present invention. A circuit portion surrounded by a chain line in the figure is an ASE (adaptive system evaluator) 4, and an MPU 10 of the same type as an MPU 9 constituting the user system is provided within this ASE 4. And this
installed in ASE4 and system development equipment 7.
ASE controller 11 and trace buffer 1
2 and the break circuit 13 constitute an in-circuit emulator.

A trace buffer 12 has a memory for chronologically capturing input/output signals appearing on the bus while the MPU 10 is executing a user program. The break circuit 13 sets conditions for the end (breakpoint) of a series of programs to be divided and executed during debugging.
Compared to the address signal on the bus in terms of hardware
A stop signal for execution of the user program by the MPU 10 is formed.

Further, the ASE controller 11 is connected to an MPU 20 as a host processor that controls the system development device 7 via a bus 14.
When a command such as executing a user program comes in from the CRT display keyboard,
It is determined whether the command is directed to the ASE 4 or not, and the command is supplied to the MPU 10. MPU1
When 0 receives this command, it outputs an appropriate address signal and performs space switching, that is, switching from system mode to emulation mode in which a user program is executed.

15 is a decoder for decoding the address signal output from the MPU 10, 16a and 16b are registers set by the output signal from the decoder 11, and 17a and 17b are input/output buffers of the ASE 4, respectively. When the MPU 10 receives a user program execution command input from the keyboard and outputs a predetermined address signal, the decoder 15 decodes this address signal and sets the register 16a at an appropriate timing. When the register 16a is set by the decoder 15, it outputs a high level control signal _C1 . This control signal C ₁ is supplied to one input terminal of AND gates G ₁ and G ₂ . Then,
AND gates G ₁ and G ₂ are opened and input buffer 17
Halt signal from the user system side via a
HALT is enabled to be input to MPU10, and
Output signal from MPU10 (photo recognition signal BA)
is made possible to be supplied to the user system side from the output buffer 17b via the OR gate _G3 .

In other words, when a command to execute a user program is input from the keyboard, the space is switched, and the MPU 10 enters a state in which the user program is executed (emulation mode), the register 16a is set and the user system A halt signal HALT from the side can be received at all times. Therefore, the halt signal
When HALT is input, the execution of the program by MPU 10 is temporarily stopped, and the output buffer 17b
Holt recognition signal BA to the user system side via
is output and the bus is released. As a result, the freed bus can be used, for example, to refresh the dynamic memory (RAM8) used in the system.

When the condition for stopping the execution of the user program is satisfied in the break circuit 13, the MPU 10 is switched from the emulation mode to the system mode, and the register 16a is reset.

Then, the MPU 10 uses the ASE controller 11
The MPU 20 in the system development device 7 operates the ASE controller 11, trace buffer 12, break circuit 13, etc. according to the program stored in the ROM in the system development device 7, and the MPU 20 in the system development device 7 receives the data obtained as a result of executing the user program. Process in a format that is easy to edit. As a result, the system development device 7
The MPU 20 displays on the CRT display how the user program is executed in an easy-to-understand manner. Furthermore, when the register 16a is reset, the output signal of the register 16a changes to low level, AND gates _G1 and _G2 are closed, and the halt signal HALT from the user system side is reset.
is no longer supplied to the MPU 10. Therefore,
The hole recognition signal BA is no longer output from the MPU 10. However, at this time, register 16b
is set, the AND gate _G4 is opened by the output signal _C2 of the register 16b, so when the halt signal HALT comes in, the AND gate _G4 is opened.
The output becomes high level, a halt recognition signal BA is output from the output buffer 17b to the user system side via the OR gate _G3 , and the bus is released.

Note that the register 16b can be set to an arbitrary set state or reset state by causing the MPU 10 to execute a system program on the ASE 4 side in advance.

In this way, in the in-circuit emulator of the above embodiment, the bus is released in response to a halt request from the user system side even in a mode other than the emulation mode in which the MPU 10 in the ASE 4 executes the user program. CRT
MPU1 that processes data for display
It is possible to refresh the dynamics on the user system side without stopping the operation of 0.

On the other hand, if it is not desired to output the halt recognition signal BA in response to a halt request from the user system side, the register 16b need not be set in advance.

The present invention is not limited to the above-mentioned embodiment. For example, even when a tri-state type is used as the output buffer 17b in the ASE4, the gate circuit section consisting of the logic gates _G1 to _G4 can be appropriately assembled. By changing this, it is possible to output the halt recognition signal BA in the same manner as in the above embodiment even when emulation is not being executed.

〔effect〕

As explained above, the present invention is equipped with the same microprocessor as the microprocessor of the system to be emulated, and is operated in a spatially divided manner between the emulation mode and the system mode. In the emulator, first and second state setting means (registers) that can be set in advance and an operation low usage request signal (halt signal) from the emulation target system according to the setting state of the first state setting means are provided. A first logic circuit (AND gate) for supplying or cutting off the signal to the microprocessor, and a response signal formed in response to an operation stop request signal from the emulation target system according to the setting state of the second state setting means. A second logic circuit (AND gate) is provided to output an output, and when the microprocessor is in the system mode, the supply of the operation stop request signal is cut off and the microprocessor is not put into the emulation mode. Response signal to operation stop request signal (halt recognition signal)
Since the microprocessor is configured to be able to respond to the emulation target system, even if a halt request is received, the desired control signal can be output without stopping the microprocessor. Therefore, an in-circuit emulator to which this is applied can respond to a halt request from the user system side even when emulation is not being executed. As a result, the dynamic memory can be refreshed without stopping the microprocessor. Moreover, this has the effect of making it easier for the user to design the system and widening the scope of application.

Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.

[Application field]

In the above explanation, the invention made by the present inventor was mainly explained with respect to the in-circuit emulator, which is the field of application that forms the background of the invention.
The present invention is not limited to this, and can be applied, for example, to a case where two microprocessors connected to a common bus line share one RAM.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing the configuration of a software development device as an example of a system to which the present invention is applied, and FIG.
1 is a block configuration diagram showing one embodiment of an emulator. FIG. 10...Microprocessor (MPU), 16
a, 16b...Status setting means (register), G ₁ ~
G ₄ ...Signal forming means (logic gate), HALT...
Halt signal, BA...control signal (halt recognition signal).

Claims (1)

[Scope of Claims] 1. The microprocessor is equipped with the same microprocessor as the microprocessor of the system to be emulated, and the microprocessor is capable of processing data obtained as a result of emulation during an emulation mode in which a user program is executed, and in an emulation mode in which a user program is executed. In an emulator that is operated in a spatially divided manner between a system mode and a system mode in which the host processor processes the
a first logic circuit that supplies or cuts off an operation stop request signal from the emulation target system to the microprocessor according to the setting state of the first state setting means; and a second logic circuit that receives an operation stop request signal from the emulation target system according to the setting state of the setting means, forms and outputs a response signal, and when the microprocessor is in the system mode, the microprocessor stops operating. It is characterized by comprising a functional circuit configured to be able to cut off the supply of the stop request signal and send a response signal to the system to be emulated without causing the microprocessor to enter the emulation mode. An emulator that does this. 2 The first logic circuit is an AND gate that takes the output signal of the first state setting means as one input signal and the operation stop request signal from the emulation target system as the other input signal, and The logic circuit is an AND gate that takes the output signal of the second state setting means as one input signal and takes the operation stop request signal from the emulation target system as the other input signal. The emulator described in item 1.