JPH04114241A - Debugging device - Google Patents

Abstract

PURPOSE:To enable emulation control to a sub processor as well as a main processor by providing a temporary stop means to temporarily stop the operation of the sub processor and to restart the operation in addition to the function of interruption to the main processor. CONSTITUTION:The first microcomputer is a microcomputer equipped with a sub processor 2 as well as a main processor 1 in the same chip. The first microcomputer is equipped with the temporary stop means to temporarily stop the operation of the sub processor 2 and to restart the operation. Then, the main processor 1 and the sub processor 2 can simultaneously control the operations. Therefore, in the microcomputer building-in the sub processor 2 as well as the main processor 1, the operations of the main processor 1 and the sub processor 2 are easily controlled. Thus, when applying this device to an emulator, the emulation similar to the emulation to the conventional main processor is realized to the sub processor 2 and further, combined debugging is enabled as well.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a technique effective for realizing a program debugging function in a development support device for a microcomputer having a plurality of processors, and particularly to a technique effective for use in an emulator. .

[Prior Art] In the development of microcomputer application equipment, emulators are used to debug the application system and perform detailed revisions of the system. The emulator has a target microcomputer or a microcomputer with the same functions as the target microcomputer, and enables hardware and software debugging by controlling the user system while executing and stopping the user program using the microcomputer.

In general, emulators have functions for executing programs from arbitrary addresses, setting breakpoints, displaying and changing register contents, and tracing execution results in order to debug user programs. In addition, an emulator memory is provided that is lent out when the application equipment (user system) does not have memory available.The user can allocate the required capacity to any address location of the user's choice, load the user program, and execute the user program ( 1989 61
(Refer to pages 78 to 94 of ``All About F Microcomputer Development,'' published by Dempa Shimbun on the 120th).

Furthermore, the emulation support target of conventional emulators has generally been a CPU inside a microcomputer.

[Problem to be solved by the invention] As microcomputers become more highly integrated, systems on a chip are being developed. The development of a one-chip microcomputer equipped with a sub-processor that operates and mainly controls peripheral devices is underway.

On the other hand, as an emulator for such a microcomputer, it is necessary to provide a debugging function for the sub-processor as well as a debugging function for the main processor. However, since the sub-processor operates by executing a program in the built-in PROMJ, it has become difficult to control its operation from the outside, and it is currently impossible to debug the sub-processor.

An object of the present invention is to enable emulation control for sub-processors in addition to the main processor.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

"Means for Solving the Problems" An overview of typical inventions disclosed in this application is as follows.

That is, in addition to the ability to interrupt the main processor,
A temporary stop means for temporarily stopping and restarting the operation of the sub-processor is provided, thereby making it possible to control the operation of both the main processor and the sub-processor simultaneously.

[Operation] According to the above-mentioned means, in a microcomputer that has a built-in sub-processor in addition to the main processor, operation control of the main processor and the sub-processor becomes easy, and when this is applied to an emulator, it is superior to the conventional main processor. Similar emulation can be achieved for sub-processors, and combination debugging is also possible.

[Embodiment] An embodiment in which the present invention is applied to an emulator will be described below with reference to the drawings.

First, the overall configuration of an emulator to which the present invention is applied will be explained with reference to the block diagram shown in FIG.

That is, the emulator of this embodiment has a sub-processor 2 in addition to the main processor 1 inside the chip, a microcomputer 11 that performs the functions of the target microcomputer, and an emulation control unit that executes emulation and various debugging functions. 12. A break control unit 13 that sets program execution and trace stop conditions and stops the program or trace when the conditions are met; a trace memory 14 that sequentially stores signals on the bus during emulation; and application equipment ( An emulation RAM 15 that is lent out when memory is not available in the user system), a serial interface J6 for data communication with the parent computer console 3o, a system memory 17 that stores programs for the entire system, and various debugging functions. A system microprocessor 18 that manages control to achieve
Consists of etc.

In the emulator, the tip of a cable extended from the main body of the emulator is connected to a microprocessor socket provided in an application device, so that the microcomputer 11 acts as a target microprocessor. When the microcomputer 11 performs proxy control (emulation) of the user's actual machine, the microcomputer 11 is separated from the control of the system microprocessor 18;
When the control operating state reaches a predetermined state and is broken, it is placed under the control of the mask microprocessor. Such switching of control states is performed by the emulation control section 12.

Note that, although not particularly limited, the emulation control unit 1
2. The break control unit 13, trace memory 14, and emulation RAM 15 are connected to the microcomputer 11 via the emulation bus 19 used during emulation execution, and to the system microcomputer 11 via the system bus 20 used to control the entire emulator. The processor 18 is connected to the processor 18 . Each function is executed using the console 3 on the parent computer side connected to the emulator main body.
Controlled by 0.

Further, a cable 22 is extended from the microcomputer 11 via a user interface circuit 21, and a plug provided at the end of this cable is connected to a microcomputer socket 23 on the user's actual machine as a microcomputer application device. , the microcomputer 11 performs proxy control of the user's actual machine.

FIG. 1 shows an embodiment of a microcomputer for emulation of a debugging device according to the present invention.

The emulation microcomputer 11 of this embodiment has a sub-processor 2 in addition to the main processor 1 on the same chip.
Although the functions of sub-processor 2 and sub-processor 2 are not particularly limited, for example, main processor 1 performs system control using a bus, and sub-processor 2 realizes peripheral device control functions via an I10 port.

In FIG. 1, inside the microcomputer 11,
Main processor! , subprocessor 2, RAM, RO
RAM consisting of M and peripheral I10.

It has a ROM and an I10 function 3, which are connected to each other via an internal bus 4. Furthermore, the internal bus 4 can access external memory via an external interface 5. The microcomputer 11 is provided with a non-maskable interrupt BRK terminal 6 to which the BRK interrupt 31 from the break control section 12 is input, and an F (ALT terminal 7) to which the halt input 32 is input. It has an input from the non-maskable interrupt BRK terminal 6 to the processor 1 and an exception handling return instruction for the main processor 1, and has a halt function for temporarily halting the operation of the sub-processor 2, which will be described later, as a function exclusive to the emulator. In the example, sub-processor 2 executes one instruction in 1 clocks, which is faster than the main processor 1, which executes 1 instruction in at least 2 clocks.

In this embodiment, the causes of a halt include an input from the HALT terminal 7, a write to the halt register 8 by the main processor 1, and an instruction whose HALT bit 2a added to the instruction executed by the sub-processor 2 is II II II. The execution consists of three parts. The HALT bit 2a of the sub-processor 2 consists of 1 bit and is prepared for the instruction address capacity. Each of the above-mentioned halt factors performs halt control via the sub-processor halt control circuit 9. In addition, input from HAL T terminal 7 and H
The ALT bit 2a generates a non-maskable interrupt 33 to the main processor l. Above BRK terminal 6
The input from the main processor 1 and the non-maskable interrupt 33 are input to the main processor 1 via an OR gate 1o. Further, the halt state is released by the main processor 1's return instruction execution signal 34 from exception processing.

Next, an explanation will be given of an interrupt to the main processor of the microcomputer of the above embodiment, and the operation and termination of the sub-processor.

The main processor 1 of the microcomputer 11 stops emulation by the BRK interrupt 31 from the break control 13 and enters a waiting state. Thereafter, when the system MPU 18 issues an emulation execution instruction via the emulation control unit 12, the exception handling return instruction is executed and the emulation is re-executed. Here, the sub-processor 2 can operate even when the main processor 1 is stopped, and conversely, when the sub-processor 2 is halted, the main processor 1 is always stopped due to an interrupt. The sub-processor 2 receives a halt instruction (that is, a halt command 32 from the break control unit 13 to the HALT terminal 7, a write to the halt register 8 by the main processor 1, or a HALT bit 2a set to II).
The operation is temporarily stopped by execution of an instruction to change to I II), and then the system enters a waiting state until emulation is re-executed by execution of an exception handling return instruction by the system MPU 18.

If at least one of the above three halt factors exists, the halt function can be realized in some way. Each halt factor has the following characteristics.

1) In the case of HALT terminal 7, microcomputer 1
Halt human power 32 is input from outside 1 and the operation is temporarily stopped. Specifically, when the sub-processor halt control circuit 9 checks the address and the address value reaches a certain value specified by the halt input 32 input via the HAL terminal 7, the sub-processor 2 is temporarily disabled. It can be stopped.

1i) If HALT bit 2a, subprocessor 2
HA for a predetermined number of instructions (for example, 512 instructions) that has
There is LT bit 2a, and the bit of H A L T bit 2a corresponding to the instruction to be halted is II l +1
If set to , the corresponding command will be executed and then paused. To release the halt, the sub-processor halt control circuit 9 issues a return-break command exclusively for the emulator to the main processor 1 (main processor 1 at this time is in break mode after receiving the BRK interrupt 31). When the main processor 1 executes the return-break instruction, the sub-processor 2 is also released from the halt state. This HAT
The halt factor caused by the L bit 2a has the following characteristics compared to the halt factor caused by the HALT terminal 7 described above.

In other words, since the sub-processor 2 performs high-speed processing that executes one instruction with one clock, even if the halt power 32 is instructed from the outside via the HALT terminal 7, it will stop a little further than the desired state. Therefore, the desired emulation may not be possible, but if the HALT bit 2a is provided, by setting the corresponding bit to l'', it is possible to execute the corresponding instruction and stop the program reliably. Also, HALT bit 2
When providing a, it is sufficient to secure bits corresponding to the instructions of the sub-processor 2, and there is also an advantage that fewer circuits are required to be added outside the sub-processor 2.

However, in the case where the HALT bit 2a is provided, the corresponding instruction is always stopped after execution, so it is not suitable for executing the instruction by specifying the number of times.

When specifying such a number of times, the halt function may be realized by the halt manual input 32 to the HALT terminal 7.

m) In the case of the halt register 8, when the main processor 1 is in a break state and the sub-processor 2 is running (for example, operating a peripheral device) and you want to stop the sub-processor 2, the main processor 1 uses this register. By setting the halt register 8, the subprocessor 2 is temporarily stopped. Halting using the halt register 8 is very convenient in that it does not place a burden on the hardware, especially when stopping the sub-processor 2 when the main processor 1 is in a break state and the sub-processor 2 is running.

In this embodiment, since the above-mentioned three halt factors are provided, various emulation operation controls as described below are possible.

FIG. 3 shows a state transition diagram of the microcomputer 11 in emulation operation control. Also,
Table 1 shows the operating states of the main processor and sub-processor and their control means in each status shown in FIG.

In FIG. 3 and Table 1, the system MPU 18 that starts the emulator causes the main processor 1 in the microcomputer 11 to break (emulation stopped state) and sub-processor 2 to halt state. In this embodiment, the above-mentioned interrupt to the main processor 1 and the halt function of the sub-processor 2 make it possible to realize the nine states (statuses) 1 to 2 shown in FIG. 3.

Table 1 For example, in Table 1 status ■, 6 represents a state where the main processor 1 and sub processor 2 are stopped and emulation is executed. This state is realized by the main processor l executing an interrupt exception return instruction. Furthermore, the status ■ indicates a state in which the main processor 1 is in operation, with the main processor 1 being stopped but the sub processor 2 being in operation.

In status ■, if both main processor 1 and sub-processor 2 are stopped, only sub-processor 2 is activated, and BRK is activated immediately after executing the interrupt exception return instruction.
A state in which only subprocessor 2 is running can be realized by interrupt input. In status ■, only the main processor l executes l instructions, and one instruction is executed after the interrupt exception return instruction is executed (this l instruction refers to one instruction of the user's program).
Then, the main processor 1 is stopped by the BRK interrupt input. At this time, if the sub-processor 2 is operating, it will be in the status ■. Note that, by designation, when the main processor 1 is stopped, the sub-processor 2 can also be stopped by a halt input.

In status (2), the main processor 1 remains stopped and only the sub-processor 2 is operated.The main processor 1 is stopped by the method of the above-mentioned status (2), and the sub-processor 2 is stopped by a halt input after executing one instruction.

Status ■ represents a state in which the sub-processor 2 is stopped using the halt register 8 when the main processor 1 is in a break state and the sub-processor 2 is running. In status ■, only the main processor 1 is stopped by a BRK input (break instruction) while the main processor 1 and sub-processor 2 are in operation. In this case as well, it is possible to stop the main processor 1 and the sub-processor 2 by inputting a halt, as specified. In status (2), the sub-processor 2 is stopped due to the HALT terminal 7 or the instruction HALT bit 2a, and the main processor 1 is stopped by outputting a non-maskable interrupt 33 from the sub-processor halt control circuit 9.

As described above, by using the exception handling return instruction execution and the BRK interrupt 31, it is possible to execute and stop emulation of the main processor 1 without affecting the state of the sub-processor 2 (■, ■, reference). When executing emulation when the sub-processor 2 is halted, the sub-processor 2 can also start operating at the same time as the main processor 1 (see ■, ■), and depending on the specification, the sub-processor 2 can be stopped by the halt manual power 32. You can also do that. Note that if it is desired to execute emulation of the main processor 1 while the sub-processor 2 is always stopped, this is done by setting registers in the sub-processor 2 by the main processor 1. Conversely, emulation execution of only the subprocessor 2 can be performed by applying the BRK interrupt 31 or HALT input 32 when executing the exception handling return instruction (■,
reference). Furthermore, by writing to the halt register 8 by the main processor 1, only the sub-processor 2 can be forcibly stopped during emulation (see ■). In addition, the break control unit 13 and the BRK interrupt 31. HAL
By using the T and HAL T bits 2a, various break functions can be realized (see ■).

In addition, in the above embodiment, priority is given to HALT, but it is not necessary to give priority to HALT. That is, when the sub-processor 2 enters the halt state, the sub-processor halt control circuit 9 forcibly generates a break in the non-maskable interrupt 32 via the OR gate 10 in the main processor 1, thereby stopping the main processor 1. However, in the above embodiment, the condition for suspending the operation of the sub-processor 2 may not be added as an interrupt factor to the main processor 1.

Furthermore, in the above embodiment, the suspension of the operation of the sub-processor 2 is canceled by a return instruction from the interrupt processing of the main processor 1. Of course, if this is the case, such cancellation may not be performed.

As explained above, in the embodiment 1-1, in addition to the interrupt function for the main processor 1, the HALT terminal 7, HALT bit 2a, and a halt register 8, and it is possible to simultaneously control the operation of both the main processor 1 and the sub-processor 2 using these three halt factors, making it possible to debug the sub-processor 2 at the same time as debugging the main processor 1. Become. This has the effect that emulation similar to the debug function of the main processor can be realized for the sub-processor 2.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the main processor 1 interrupt is generated by the bold of the sub-processor 2, but only the halt of the sub-processor 2 may be used. Further, although the sub-processor 2 is temporarily stopped (halted), any system that can control the operation of the sub-processor 2 may be used.

In the above embodiment, the causes of a halt that temporarily stop the operation of the sub-processor 2 include the halt input 32 from the HA LT terminal 7, the write to the halt register 8 by the main processor 1, and the instruction executed by the sub-processor 2. Three factors are provided for the execution of an instruction with the added HALT bit 2a set to 1, thereby realizing a variety of emulation operation controls as shown in Figure 3 and Table 1. It is not limited to the three above-mentioned halt factors as long as it causes stopping and restarting. Furthermore, it goes without saying that the device does not have to have all three of the above-mentioned actual halt factors, but may have only any one of the three halt factors, or only any two halt factors.

Furthermore, in the above embodiment, the present invention is applied to a multiprocessor emulator that has one subprocessor 2 in addition to the main processor, but it is also applicable to a multiprocessor emulator that has a plurality of processors in the same chip (for example, two subprocessors). The present invention can be similarly applied to certain types of devices. Further, the microcomputer to be emulated may be not only a microprocessor but also a single-chip microcomputer.

The above explanation has mainly been about the application of the invention made by the present inventor to emulators, which is the background field of application. It can be used in simulators, simulators, and other data processing systems with emulation functions.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, in a microcomputer that has a built-in subprocessor in addition to the main processor, it is easy to control the operation of the main processor and subprocessor, and when this is applied to an emulator, the same emulation as the conventional CPU debugging function can be applied to the subprocessor. This makes it possible to implement combined debugging.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the main part of an emulator according to the present invention, FIG. 2 is a block diagram showing an example of a general configuration of the entire emulator to which the present invention is applied, and FIG. FIG. 3 is a state transition diagram of a microcomputer in emulation operation control of an emulator. ■...Main processor, 2...Sub processor, 2a...l (AL T bit (temporary stop means), 6...BRK terminal, 7...HA L T terminal (temporary stop means), 8... Halt register (
(temporary stop means), 9... Sub-processor halt control circuit, 11... Emulation target microcomputer, 12... Emulation control unit, 1
3... Break control unit, 14... Trace memory, 15... Emulation RAM, 17...
System memory, 18...System microprocessor, 19...Emulation bus, 20...
・System bus, 21...User interface,
22...cable, 23...microcomputer socket, 30...main computer console, 31...
...B RK interrupt, 32 ... Halt input, 3
3...Non-maskable interrupt, 34...Return instruction execution signal from exception handling. Figure Figure Emulator 4 Wataru F Mangodan and -dan

Claims (1)

[Scope of Claims] 1. A debugging device having a first microcomputer that performs the functions of a microcomputer of a device to be debugged, and a second microcomputer that controls debugging; A microcomputer is a microcomputer that has a subprocessor in the same chip in addition to a main processor,
A debugging device characterized in that the first microcomputer is provided with a temporary stop means for temporarily stopping the operation of the sub-processor and restarting the operation, so that the operation of the main processor and the sub-processor can be controlled simultaneously. 2. Claim 1, wherein the temporary stopping means is configured to temporarily stop the operation of the subprocessor by inputting a terminal or by executing a special instruction.
Debug equipment as described. 3. The debugging device according to claim 1 or 2, wherein the suspension of operation of the sub-processor is canceled by a return instruction from interrupt processing of the main processor.