JPS61138361A - Parallel processing system - Google Patents

Abstract

PURPOSE:To debug efficiently a program for parallel processing by installing an interrupting circuit, etc., at a control unit and a processor element PE respectively and installing a PE memory change-over circuit at PE. CONSTITUTION:A control unit CU1 is composed of a memory 11, a processor part 12, an interrupting processing part 13, control FF14, 15 and 16 and an OR gate 17. A PE2 is composed a memory 21, a processor part 22, an interrupting processing part 23, a control FF24 and a PE memory change-over circuit 25. In a program debugging, when the breaking is desired to be executed at the optional program point of CU1 and PE2, the processing is executed through processing parts 13 and 23, etc., and when the memory 21 of respective PE2 is viewed, from the CU1, the viewing is executed through the circuit 25. Thus, the CU1 and PE2 can be broken at the same time point as the time point of the breaking and the memory 21 can viewed from the CPU1, and therefore, the debugging of the program for parallel processing can be efficiently executed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a parallel processing system that realizes highly parallel processing by distributing processing by coupling a large number of processor elements into a network. MIMD
Concerning configurations that efficiently support debugging of programs.

[Prior art]

As a method for performing scientific and technical calculations at ultra-high speed.

By combining a large number of processor elements into a network, 1. There is a parallel processing method that distributes processing to each processor element. Figure 4 shows an example of a configuration in which processor elements are connected in a lattice pattern, and 1 is a control element.
Unit (hereinafter referred to as CU), 2 is a processor element (hereinafter referred to as PE). CUI is connected to each PE2 by control line 3 and status line 4, and each PE2
The state of PE 2 is obtained through the status line 4, and each PE 2 is controlled through the control line 3. Each PE2 is connected by an inter-PE interface line 5, and data transfer between PEs is performed.

Looking at this parallel processing method from the processing form, SIMD (
Single In5truction Stream
Multi Data) and MIMD
(Multi In5truction St.
It is divided into two parts: reamMulti Data).

When a program is processed as SIMD on a device in which PEs are connected in a network (hereinafter referred to as a parallel processing device), each PE always executes the same instruction at any given time, so it is as if it were a single processor. It looks like debugging is done with , and program debugging is easy. That is, taking the configuration shown in FIG. 4 as an example, each PE2 has the same program as shown in FIG. 5, although the data is different. Therefore, the debugging point is the same for both software debugging and software debugging.

Moreover, since the execution time is the same, at the time of debugging, you can obtain fixed debugging information that is not affected by other PEs (for example, memory contents at arbitrary addresses, softable information such as program counters, general-purpose registers, segment registers, etc.). It will be done.

On the other hand, when a program is processed as MIMD on a parallel processing device, the execution of each PE is not the same when viewed at the same time. Therefore, by stopping the execution of all PEs at the same time,
It is difficult to view the softable debug information of each PE in the same way as SIMD.

This will be explained in detail below.

Figure 6' shows MTMD (even if the static instructions are the same,
Dynamically, the programs to be executed may be different. For example, when executing a conditional jump instruction, the execution differs depending on the conditions. Here, such cases are interpreted in a broad sense and are referred to as MIMD. ) shows the processing flow.

The CU broadcasts or individually transfers instructions to each PE. Next, the data is transferred to each PE individually, and
When the initial setting of is completed, a start instruction is issued to each PE. The CU then runs its own program to
It waits for the report of the calculation results from E, and edits the calculation results of each PE. On the other hand, the PE starts executing its own program in response to a start instruction from the CU. Let us now assume that the points at which you want to break on the CU side are ■, ■, and the points on the PE side are O2 ■, ■. -For example, if you want to break with ■, use C as debug information.
There may be cases where it is desired to stop the execution of all PEs not only at U but also at the end of the instruction being executed at the same time as the break (hereinafter simply referred to as the same time) and to check the status of each PE. Similarly, P.E.
Set a break point on the side, and at the same time as the break, other P
You may want to stop the execution of E and CU and look at their states. However, with conventional parallel processing devices, it is not possible to stop the execution of other PEs at the same time when a break occurs.
The status of other PEs becomes uncertain, and when dehugging, it is necessary to perform dehugging using only the dehugging information of the own PE, which poses a problem of deteriorating debugging efficiency.

Note that as a debugging method when processing as MIMD on a parallel processing device, there is software debugging using an emulator for software development. This is the total P if the number of PE is small.
E can be emulated at the same time, and various debugs can be performed using the emulator's debugger. However, P.E.
If the number is large, PEs that can be emulated and P that cannot be emulated.
Since E is mixed, there is a problem that the states of PEs that are not emulated at the time of break cannot be seen at the same time. Also,
Setting up an emulator on a parallel processing device after development may be difficult in terms of implementation.

[Object of the invention] The object of the present invention is to solve the above-mentioned conventional problems and to
An object of the present invention is to provide a parallel processing system that enables efficient program debugging.

[Structure of the invention]

The present invention provides control that, when a break is made at an arbitrary program point in a CU and each PE, can break the CU and all PEs or any PE at the same time as the break, and can restart from the next instruction after the break.・CU register and interrupt circuit.

The CU includes a memory control circuit that is provided in each PE and allows the CU to view the memory of each PE.

By providing it in the PE, it is possible to efficiently debug MIMD programs.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the invention. In Figure 1, C
The UI includes memory 11, processor section 12, and interrupt processing section 1.
3. Control flip-flop (control F/F) 14.15.
16 and an OR gate 17. Each PE includes a memory 21, a processor section 22, an interrupt processing section 23, and a control F.
/F24 and a PE memory switching circuit 25.

here.

The PE memory switching circuit 25 serves to switch the appearance of the memory (PE memory) 21 to either the CU side or the PE side. Below, as an example of the operation in Figure 1, a case where a break is made on the CU side (for example, ■, ■ in Figure 6) and a case where the PE
Cases where the break is made on the side (for example, @, ■, ■ in Figure 6)
) will be explained.

First, a case will be described in which a break is caused on the CU side and debugging is proceeded by checking the state of the PE at the same time as the break.

First, the operation on the CU side will be described. From 5TART to the start instruction in Figure 6, the PE side does not execute the C
Since it is visible from U, in this case there is no need to stop the PE side at the same time. ○N control F/F 15 at debug point
” (this is referred to as OUT' F/F 15) is inserted into the program. By executing this debug instruction, the processor unit 12 of the CUl
Turn F15 into 'ON' state and interrupt processing unit 13 on the CU side.
and issues an interrupt to the interrupt processing unit 23 of each PE (this is referred to as interrupt 1). In Figure 1, the configuration is such that interrupt 1 is issued to all PEs, but when sending interrupt 1, it must be sent to each PE individually, or interrupt 1 may be masked before being processed by the PE. It is also possible to apply interrupt 1 to any PE depending on the situation. C.D.I.
can support various types of debugging for this interrupt 1 depending on how the program is constructed. for example,
When debugging with a conversational image, you can view the memory contents of each PE from the terminal (in this case, the CU side waits until the softwareable information necessary for the PH is set).
/ then need to look at the PE's memory).

It can support debugging such as being able to set data. That is, in order to view the contents of the memory 21 of each PE 2, the CU1 controls the memory switching circuit 25 on the PE side with an instruction to turn the control F/F 14 to 0N10FF (output F/F 14). It is possible to read/write the PE memory 21 individually. After reading/writing, the control F/F 14 is reset and the PE memory 21 is returned to the PE side, and the control F/F 1
Debug instruction to turn 6 “ON” (OUT F/F16)
By executing 1. An interrupt is issued to each PE (this is called interrupt 2), and the stopped state is released.

Then execute the next command. When debugging a non-conversational image, each PE waits until the softable information is stored in the fixed memory area, then executes the debug instruction (OUT F/F 16), and moves on to the next instruction.

Next, the operation on the PE side will be described. Processor section 2 of PE2
2 checks whether there is an interrupt 1 after completing the current instruction, and if not, executes the next instruction □.

If so, the interrupt processing unit 23 processes the interrupt.

That is, softable information is saved in a fixed memory area of the memory 21, and then the system is stopped. The stop state is canceled by interrupt 2 issued by the CUI. After the release, the information saved by interrupt 1 is restored and the next instruction is executed.

Next, a case will be described in which a break is caused on the PE side and debugging is proceeded by checking the state of other PEs at the same time as the break.

First, the operation on the PE side that issued the debug command will be described. After setting control F/F24 to 'ON' by debug command, interrupt 1 from CU side (signal from control F/F)
Perform mask processing to ignore.

By setting the control F/F 24 to II Q N #,
The control F/F 15 on the CU side turns "ON" and generates interrupt 1 to the CU and other PEs. Thereafter, the process necessary for debugging, such as moving softable information to a fixed memory area, is performed, and the system is brought to a halt state.

To cancel the stopped state, interrupt 2 (control F/F) issued by CUI
16). After the release, the information saved by interrupt 1 is restored and the next instruction is executed.

The operation on the PE side that does not generate a debug instruction is the same as the operation on the PE side described above in the case of causing a break on the CU side.

The operation on the CU side is as follows. After completing the instruction, C and Ul check whether there is an interrupt 1. If not, execute the next instruction, and if so, perform interrupt processing. This interrupt processing and subsequent operations are the same as the operations on the CU side described above in the case of causing a break on the CU side.

The operational flow on the CU side is shown in FIG. 2, and the operational flow on the PE side is shown in FIG. 3. Blocks 31 and 32 surrounded by broken lines in FIGS. 2 and 3 are interrupt processing routines that should be handled by software, and if the content of debugging is different, this routine will naturally be different. However, breaks necessary for debugging and breaks at the same time are supported by hardware.

Note that the OR gate 17 in FIG. 1 serves to cause each PE to generate an interrupt 1 at an arbitrary point.

Even with this configuration, debug instructions can be inserted at any program point in the CU and each PE, and all PEs or any PE can break at the same time the debug instruction is executed, making it even easier to break. It is possible to perform an interrupt that allows restarting from 1 to 1 from the next instruction issued, and memory switching control that allows the CU to view the memory of the PE.

〔Effect of the invention〕

As explained above, according to the present invention, CU and PE can be broken at the same time as the break time, and
Since the E memory is visible, MIMD program location on the parallel processing device can be efficiently performed.

Further, debugging in trace mode is possible by inserting a debugging instruction at each step of the program.

moreover.

When issuing a debug instruction, either send it to each PE individually when sending interrupt 1, or interrupt 1 on the PE side.
By controlling the mask for PE, it is possible to stop any PE, and debug instructions can be arbitrarily inserted into the CU and each PE, so a wide range of debugging can be supported.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of the CU and PE of one embodiment of the present invention, and Figure 2
The figure shows an example of the processing flow on the CU during debugging.
The figure shows an example of the processing flow on the PE during debugging.
Figure 5 shows an example of the overall configuration of a parallel processing system.
The figure shows an example of the processing flow when debugging SIMD.
The figure is a diagram showing an example of a processing flow when debugging MIMD. 1...Control unit)-(CU), 2...
Processor element (PE), 11.1-2...
・Memory, 12.22... Processor section,
13.23...Interrupt processing unit, 14.15.16.2
4... Control flip-flop 5 17... OR gate. Figure 4 Figure 5 Rollo circle

Claims (1)

[Claims] (1) Multiple processors connected in a network
In a parallel processing system consisting of an element and a control unit that controls each processor element, the control unit has the ability to control all processors when a break is made at an arbitrary program location of the control unit and each processor element.・Means for stopping the element or any processor element, means for instructing the processor element to switch the memory of the processor element to the control unit side, and means for each processor element after the break is released. and a means to restart from the next instruction after the break,
Each processor element has a means for notifying a control unit when a break is caused at an arbitrary program location of the processor element, and a means for notifying a control unit to that effect, and a means for controlling the memory of the processor element according to instructions from the control unit. A parallel processing system characterized by providing switching means on the control unit side.