JPS634348A - Data processor - Google Patents

Abstract

PURPOSE:To supply a specific instruction to a microcomputer at desired timing by providing a signal output circuit which can outputs a signal indicating an instruction fetch instead of a timing signal. CONSTITUTION:When a break signal BRK is held at a low level while a microcomputer MCU 1 for emulation is operated on the basis of the program of an applied equipment side, control signals phig1, phig2, and phig3 are inverted in synchronism with specific timing, only a gate circuit G3 is enabled to output input data and an operation code indicating break processing is supplied from an operation code output circuit OP. Consequently, the microcomputer MCU 1 performs interruption processing based upon the indication of the operation code and the break processing is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device, and relates to a technique that is effective when applied to, for example, an in-circuit emulator.

[Prior art]

In the development of microcomputer application equipment, in-circuit emulators can be used to debug the application system and provide detailed evaluation of the system.

Such an in-circuit emulator is connected between a system development device such as a parent computer for software development and an application device under development, and takes over the functions of a microcomputer (target microcomputer) included in the application device. It is a microcomputer system development tool that also functions as a debugger and supports detailed system debugging.

Conventional in-circuit emulators are, for example,
rLsI Handbook J published by Ohmsha on November 30th
As described in P2S5 to P563, an emulation microcomputer that performs the functions of the target microcomputer is provided, as well as an emulation control unit, breakpoint control unit, and trace memory for realizing emulation and various debugging functions. It has a built-in mask microcomputer, etc. for controlling these parts.

In such an in-circuit emulator, the end of a cable extended from the main body is connected to a target microcomputer socket included in the application equipment, so that the emulation microcomputer takes over the functions of the target microcomputer. It has emulation functions such as Furthermore, there is a real-time trace function that samples various data and status signals in real time during emulation execution and stores them in trace memory, etc., and the emulation microcomputer can virtually control the control operations of applied equipment. It is equipped with various debugging functions such as a break function to stop the program.

The inventors of the present invention have studied the break function and found that by causing the emulation microcomputer to execute a predetermined command, it is possible to stop the emulation operation of the application device.

In that case, the instructions necessary for break processing are transferred to the emulation microcomputer in synchronization with the timing at which the timing signal for instructing the instruction capture cycle in the emulation microcomputer changes to the level that instructs it. It is supplied to the microcomputer for cycling.

[Problem that the invention seeks to solve]

However, according to the above-mentioned study technology, the timing signal for instructing the instruction capture cycle in such an emulation microcomputer can be used in halt, reset, standby states, etc. where instruction capture is not required. is fixed at a level that does not instruct the uptake of Therefore, if you try to transition to break processing in such a state of the timing signal, you have no choice but to reset the entire system, which is undesirable for debugging because the entire system will be initialized. revealed.

An object of the present invention is to provide a microcomputer at a desired timing even when the microcomputer is instructed to an operation mode in which a timing signal for instructing an instruction fetch cycle does not apparently indicate an instruction fetch cycle. An object of the present invention is to provide a data processing device capable of supplying predetermined instructions to a computer.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, when an emulation microcomputer capable of outputting a timing signal for instructing an instruction capture cycle is instructed to an operation mode in which the timing signal does not apparently indicate an instruction capture cycle, the timing A signal output circuit capable of outputting a signal instructing command capture in place of the signal is provided, and emulation operation of the emulation microcomputer applied to the application device is stopped based on the output signal from the signal output circuit. It is possible to supply predetermined instructions for the microcomputer to the microcomputer.

[For production]

According to the above-mentioned means, when the emulation microcomputer is instructed to enter a halt, reset, standby state, etc. that does not require the capture of the instruction, the signal output circuit operates to
The emulation microcomputer can be supplied with a predetermined instruction necessary to stop its emulation operation, thereby enabling transition to break processing at any time without resetting the entire system. be done.

〔Example〕

FIG. 1 is a block diagram showing a schematic configuration of an in-circuit emulator which is an embodiment of a data processing device according to the present invention. The in-circuit emulator shown in the figure is formed by a known semiconductor integrated circuit manufacturing technique, although it is not particularly limited.

The in-circuit emulator shown in FIG. 1 includes a proxy unit 1 that performs the functions of a target microcomputer included in a microcomputer application device (not shown) to control the operation of the application device, and a proxy unit 1 that performs various debugging functions. It consists of a control unit 2 that controls the proxy unit 1 mentioned above.

The proxy unit 1 includes an emulation microcomputer MCUI that performs functions of a target microcomputer (not shown). Such emulation microcomputer MCUI has at least the same function as a target microcomputer (not shown) due to the nature of proxy control, and for example, TTL (
) - transistor transistor logic) circuit. The emulation microcomputer MCUI uses a load signal as a timing signal for instructing an instruction capture cycle, although it is not particularly limited.
Instruction register! LIR is output, and its low level indicates an instruction fetch cycle.

The proxy unit 1 is coupled to a target microcomputer socket (not shown) via an interface NT. Although not particularly limited, the interface NT is supplied with a halt signal HALT, a reset signal RESET, a standby signal 5TBY, etc. output from application equipment (not shown), and input/output of various data is performed.

Here, the above-mentioned halt signal HALT, reset signal RE
Although the SET and standby signals 5TBY are not particularly limited, their low level instructs the emulation microcomputer MCUI to enter the halt, reset, and standby states, respectively. The halt signal HALT, reset signal RESET, and standby signal 5TBY are supplied to the emulation microcomputer MCUI via the gate circuit G1. Microcomputer MCU for emulation
I has the above-mentioned halt signal H at a low level at its input terminal.
When the halt, reset, and standby states are instructed by supplying ALT, the reset signal RESET, and the standby signal 5TBY, the operation is stopped.

At this time, the emulation microcomputer MCU1 does not need to take in an instruction due to the nature of the specified operation mode, so the load instruction register signal LIR goes to a high level, in other words, it instructs to take in an instruction. It will be fixed at a level that does not occur.

Microcomputer MCU1 for the above emulation
The data input/output terminals of the interface INT and the data input/output terminals of the interface INT are connected to each other by an internal bus DBI with a bidirectional gate circuit G2 interposed therebetween.
One data input/output terminal is connected to the control unit 2 by an internal bus DB2 with a bidirectional gate circuit G3 interposed therebetween.

The control unit 2 includes a mask microcomputer MCU2 used exclusively for debugging control, and its data input/output terminals are typically shown in the RAM
The internal data bus DB2 is coupled to the internal data bus DB2 via various data memories DM such as (random access memory), buffer circuits B, and the like. The mask microcomputer MCU2 is operated asynchronously with the emulation microcomputer MCUI. That is, the emulation microcomputer MCUI is operated according to the clock on the application equipment side (not shown), and the master microcomputer M CU 2 is operated according to the clock on the control unit 2 side.

Here, between the microcomputers MCUI and MCU2, which operate asynchronously with each other, the emulation microcomputer MCU1, which operates based on a program on the application equipment side (not shown), stops the emulation operation for the application equipment, and debugs the application equipment. When the program is executed, its operation is stopped under control of the control unit 2.

Next, the configuration for stopping the emulation operation of the above-mentioned emulation microcomputer MCUI for application equipment will be explained, focusing on the break function.

In the control unit 2, BM is a break condition setting memory consisting of a memory such as a RAM in which desired break conditions are written and set in advance. The output terminal of the break condition setting memory BM is coupled to one input terminal of a comparator COM, and the other input terminal of the comparator COM is coupled to the internal data bus DB2. The comparator COM successively compares the data supplied to the internal data bus DB2 and the break condition during the operation of the in-circuit emulator, and outputs the comparison result data to the break signal generation circuit BG. Break signal generation circuit BG outputs break signal BRK, and when the comparison result data match, the break signal BRK is set to low level.

Here, the break function of this embodiment is executed through interrupt processing by software, although it is not particularly limited. For this purpose, an operation code output circuit OP capable of outputting an operation code as a command instructing break processing is provided, and a control unit CON T that controls the operation code output circuit OP and the gate circuits G1 to G3 is controlled. Unit 2 is provided with ALT, reset signal RESET, standby signal 5
TBY, load instruction register signal L
IR, break signal BRK, and clock generation circuit CG
Control signals φg and φ are generated based on these input signals.
g2, φ et al., and φOp are output. The above control signal φg
φg2 and 6g3 are gate circuits G1 to G3, respectively.
This is an @ signal on the operating side of the internal data buses DBI and DB2, and functions as a selection switching signal for the internal data buses DBI and DB2. Also,
The control signal φOP is an output operation control signal of the operation code output circuit OP.

To roughly explain the function of the control unit C0NT, when the emulation microcomputer MCU1 controls the operation of an application device (not shown), the gate circuits G1 and G2 are in principle in a state where data can be input/output. At the same time, the gate circuit G3 is controlled to be in a state where it cannot input or output data. Note that, at this time, the operation code output circuit oP is controlled to be in a state in which no output operation is possible. - way,
Emulation microcomputer M CU 1
is operated based on a program on the application equipment side (not shown), and when the operation matches the break condition and the break signal BRK is set to low level, the control signal φg is activated in synchronization with a predetermined timing. The levels of φg2 and 6g3 are inverted, and only the gate circuit G3 is controlled to be able to output input data, and an operation code instructing break processing is outputted from the operation code output circuit QP via the gate circuit G3. The data is supplied to the microcomputer MCUI for cycling.

Thereby, the emulation microcomputer MCUI performs interrupt processing based on the instruction of the operation code and executes break processing.

In such break processing, data processed by the emulation microcomputer MCUI at the time of transition is first stacked, and then an interrupt processing routine is executed. In that case, the emulation microcomputer MCUI is separated from the program of the application device (not shown), and the emulation operation of the emulation microcomputer MCUI for the application device is thereby stopped. Note that when the emulation microcomputer MCUI should restart the emulation operation for the application device, another operation code is issued to the emulation microcomputer MCUI, although it is not particularly shown.
It can be restarted by being supplied to the CUI. In that case, the data saved in a predetermined register (not shown) is transferred to the emulation microcomputer MC.
After being returned to the UI, a program on the application equipment side (not shown) starts running.

Next, details of the control section C0NT will be explained with reference to FIG. 2.

The emulation microcomputer MCU1 is
As mentioned above, since the master microcomputer MCU2 operates asynchronously with the control unit 2, the emulation microcomputer MCU1 receives the above operation code from the operation code output circuit OP on the control unit 2 side. In principle, the supplied timing must be synchronized with the timing at which the load instruction register signal LIR, which is a timing signal for instructing the instruction fetch cycle in the emulation microcomputer MCU1, is set to low level. −
On the other hand, the above-mentioned halt signal HALT and reset signal RESE
When the emulation microcomputer MCUI is put into the halt, reset, and standby states based on the T and standby signals 5TBY, its operation is stopped, and as a result, the emulation microcomputer MCUI Due to the nature of the specified operation mode, it is not necessary to import instructions, so the above load
The instruction register signal LIR is fixed at a high level, in other words, at a level where the instruction fetch cycle does not appear to be interrupted. O8 shown in FIG. 2 replaces the load instruction register signal LIR even when the load instruction register signal LIR is set to a high level and is fixed in a state that is not apparently an upper instruction fetch cycle. This is a signal output circuit that outputs a signal that enables the fetching of an instruction, in this embodiment, a launch control signal φ1a.

The signal output circuit O8 is a Nant gate circuit NAN to which the level-inverted standby signal 5TBY and the clock signal CLK are input via the inverter circuit IV1.
DI, the output signal of the NAND gate circuit NANDI, and the load instruction register signal L
It is composed of an AND gate circuit AND to which IR is supplied.

Although not shown, the reset signal RESET and the halt signal HALT have the same circuit configuration as the standby signal 5TBY.

In the signal output circuit O8, the standby signal 5TB
During the period in which Y is set to high level, the output of the NAND gate circuit NAND1 is set to high level regardless of the level change of the clock signal CLK. Therefore, the output of the AND gate circuit AND, that is, the latch control signal φ
1a is the load instruction register signal LI
It is set to low level in synchronization with the fall of R. Also,
When the standby signal 5TBY is set to low level, the emulation microcomputer MCU1
When the NAND gate circuit NANDI is placed in a standby state, the output of the NAND gate circuit NANDI is set to a low level in synchronization with the rise of the clock signal CLK. At this time, the load instruction register signal LIR is fixed at a high level in the standby state, so that as a result, the latch control signal φ1a output from the AND gate circuit AND changes to the high level of the clock signal CLK. Synchronized and set to low level.

In this way, the latch control signal φ1a is set to low level in synchronization with the change of the load instruction register signal LIR to low level, and
When the instruction register signal LIR is fixed at a high level, the clock signal CLK
is set to low level in synchronization with the change to high level.

The controller C0NT of this embodiment includes a latch circuit LAT that latches and outputs the playback signal BRK when the signal output circuit O8 and the latch control signal φ1a output from the signal output circuit O8 are set to low level. Consists of etc. According to this embodiment, the output signal φ of the latch circuit LAT is at the same level as the break signal BRK, and the control signals φg and φg are controlled by the output signal φ.
2, φg3, and φop are formed. That is, the control section φ
The control signals φg3 and φOp are set to the inverted level of the output signal φ via the inverter circuit IV2. Furthermore, the control signal φ
Although the operation instruction levels of g, φg3, and φOp are not particularly limited, the control signals φg2 and φg3 respectively instruct gate circuits G2 and G3 to be in an input/output enabled state by their high level, and the control signal φop is at its high level. This instructs the operation code output circuit OP to perform an output operation.

Here, although the gate circuit G1 is not particularly limited,
It is constituted by a NAND gate circuit NAND2 to which a control signal φg and a standby signal 5TBY whose level has been inverted via an inverter circuit IV3 are input. Although not shown, the halt signal HALT and reset signal RESET also have the same circuit configuration as the standby signal 5TBY.

Next, the operation of the control section C0NT will be explained in detail in relation to the standby signal 5TBY typically shown in FIG.

First, the operation in a state where the standby signal 5TBY is set to high level will be explained.

In this state, the output of the NAND gate circuit NAND2 included in the gate circuit G1 is set to a high level regardless of the level of the control signal φg.

Therefore, at this time, the emulation microcomputer MCUI is always in a non-standby state,
The control operation is enabled according to a predetermined command. - On the other hand, the output of the NAND gate circuit NANDI is set to a high level regardless of the level change of the clock signal CLK. Therefore, the output of the AND gate circuit AND,
That is, the latch control signal φ1a is set to a low level in synchronization with the fall of the load instruction register signal LIR. When this latch control signal φ1a is set to low level, if the break signal BRK is set to high level and no break processing instruction is given,
At this time, the output signal φ output from the latch circuit LAT is maintained at a high level. When this output signal φ is set at a high level, other control signals φg, φg3, and φop formed thereby are maintained at a high level. As a result of the action, the gate circuit G2 is placed in a state where data can be input/output, the gate circuit G3 is placed in a state where data cannot be input/output, and,
The operation code output circuit OP is placed in a state in which output operation is disabled. Therefore, in such a state, the emulation microcomputer M CU 1 is enabled to control the application equipment, that is, execute the emulation function, in accordance with the program on the application equipment side.

Break signal BR during execution of emulation function
When a break processing instruction is given to the control unit C0NT by setting K to low level, the timing at which the load instruction register signal LIR is set to low level, in other words, an instruction fetch cycle is instructed in the emulation microcomputer MCUI. When the latch control signal φ18 is set to low level according to the timing of the change, the output signal φ of the latch circuit LAT changes to the break signal B RK in response to the latch control signal φ18.
is inverted to the low level, which is the same level as . Then, each of the control signals φg1, φg, φ31, and φ.

The level of p is inverted. As a result, contrary to the above, the gate circuit G2 is placed in a state in which data cannot be input/output, and the gate circuit G3 is placed in a state in which data can be input/output,
In addition, the operational code output circuit OP is rendered incapable of outputting. Therefore, in such a state, the operation code output from the operation code output circuit ○P is supplied to the emulation microcomputer MCU1 via the gate circuit G3. At this time, even if the control signal φg1 is inverted and set to a low level, the standby signal 5TBY itself is set to a high level, so the output signal level of the gate circuit G1 is maintained at a high level, and as a result, the emulation The microcomputer MCU1 is maintained in a state where it can perform control operations. Therefore, the emulation microcomputer MCUI executes an interrupt for break processing based on the operation code supplied via the gate circuit G3. In this way, in the non-standby state of the emulation microcomputer MCU1, the load instruction register signal LIR
Break processing is performed in synchronization with the change of the signal to the low level.

Next, the operation in a state where the standby signal 5TBY is set to a low level and the control operation of the emulation microcomputer MCUI for the applied equipment is stopped will be described.

In this state, the output level of the NAND gate circuit NAND2 included in the gate circuit G1 is determined in response to the level of the control signal φg□.

Therefore, at this time, even if the emulation microcomputer MCUI is instructed to enter the standby state by the standby signal 5TBY, the control signal φg□
The standby state can be canceled by setting the voltage to low level. First, standby signal 5T
When the emulation microcomputer MCUI is in a standby state by setting BY to low level, the above Nant gate circuit N A N
The output of D1 is set to a low level in synchronization with the rise of the clock signal CLK. At this time, the load instruction register signal LIR is.

Since it is fixed at a high level in standby mode,
As a result, the output of the AND gate circuit AND,
That is, the latch control signal φ1a is set to a low level in synchronization with the rising edge of the clock signal CLK. When the latch control signal φ1a is set to a low level, if the break signal BRK is set to a high level and no break processing instruction is given, the output signal φ output from the latch circuit LAT is maintained at a high level. be done. When this output signal φ is set to high level, the gate circuit G2 is enabled to input and output data, and the gate circuit G3 is disabled to input and output data, and the operation code output circuit OP is placed in a state in which output operation is disabled. At this time, since the control signal φg1 is at a high level, the standby state of the emulation microcomputer MCU1 is maintained.

During the standby state, when the break signal BRK is set to low level and a break processing instruction is given to the control unit C0NT, the latch control signal φ1 is set at the timing when the clock signal CLK is set to high level.
When a is set to a low level, the output signal φ of the latch circuit LAT is inverted to a low level, which is the same level as the break signal BRK at that time.

Then, each of the above control signals φg1, φg2, φg3,
and φop are inverted. As a result, contrary to the above, the gate circuit G2 is placed in a state where data cannot be input/output, the gate circuit G3 is placed in a state where data can be input/output, and the operation code output circuit oP is placed in a state where output operation is possible. be made into Therefore, in such a state, the operation code output from the operation code output circuit OP is supplied to the emulation microcomputer MCU1 via the gate circuit G3. At this time, since the level of the control signal φg1 is inverted to a low level, even if the standby signal 5TBY itself is set to a low level, the output signal level of the gate circuit G1 is inverted to a high level. As a result, the standby state of the emulation microcomputer MCUI is released under the control of the control unit 2, and the emulation microcomputer MCUI is brought into a state in which it can perform control operations. Therefore, the emulation microcomputer MCU1 executes an interrupt for break processing based on the operation code supplied via the gate circuit G3. In this way, the emulation microcomputer M
When the standby state is instructed to the CU 1, break processing is enabled in synchronization with the change of the clock signal CLK to the high level.

According to the above embodiment, the following effects can be obtained.

(1) Microcomputer MCU for emulation
When I is instructed to enter a standby, reset, or halt state that does not normally require the capture of the instruction, the output level of the load instruction register signal LIR is fixed at a high level in response. Even if it is.

By the action of the signal output circuit SO receiving the clock signal CLK, an operation code necessary for break processing is supplied to the emulation microcomputer MCU1, thereby making it possible to execute a predetermined interrupt processing.

(2) From the above effect, even if the emulation microcomputer MCUI is instructed to operate in a mode in which its control operations are stopped, such as standby, reset, or halt, break processing is executed as necessary. be able to.

(3) Due to the above effects, break processing can be executed without resetting the entire system.

(4) In (1) above, when the operation code necessary for break processing is supplied to the emulation microcomputer MC1J1 and a predetermined interrupt processing is executed, the output control operation is performed in response to the control signal φg1. Due to the action of the gate circuit G1, the control terminals of the emulation microcomputer MCU1, that is, the standby signal 5TBY, the reset signal RESET,
Since input terminals such as the halt signal HALT are disconnected from the application equipment (not shown), it is possible to prevent malfunctions during break processing.

Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above-mentioned examples, and can be variously modified without departing from the gist thereof.

For example, in the above embodiment, the timing signal for instructing the instruction capture cycle in the emulation microcomputer is the load instruction register word output from the emulation microcomputer, but the present invention is not limited to this. Instead, it may be a signal formed based on the E clock signal or a signal formed by another special circuit. Further, the logic circuit configurations of the signal output circuit SO and the gate circuit G1 are not limited to those shown in FIG. 2, and can be changed to other appropriate logic configurations.

The above explanation has mainly been about the case where the invention made by the present inventor is applied to an in-circuit emulator, which is the field of application that formed the background of the invention, but it is not limited thereto. It can be applied to tools, microcomputer system development tools, etc. The present invention
The present invention is applicable to data processing apparatuses in which an operation mode in which at least a control operation is stopped can be set.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, if the emulation microcomputer is instructed to enter a halt, reset, or standby state that does not require the import of the instruction, the emulation microcomputer will not be able to perform break processing due to the action of the signal output circuit. Even if a necessary predetermined instruction can be supplied and an operation mode in which the control operation is stopped, such as standby, reset, or halt, is specified, break processing can be performed as necessary. Ru.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an in-circuit emulator that is an embodiment of a data processing device according to the present invention, and FIG. 2 is a block diagram showing the main parts of this embodiment, such as a control section including a signal output circuit. It is a diagram. 1... Acting unit, 2... Control unit, MCUI... Emulation microcomputer, MCU 2... Master microcomputer,
C0NT...Control unit, ○P...Op code output circuit, BG...Break signal generation circuit, SO...Signal output circuit, G1...Gate circuit, LAT...Latch circuit, LIR... Load instruction register signal, CLK...clock signal, BRK...break signal.

Claims (1)

[Scope of Claims] 1. A microcomputer capable of outputting a timing signal for instructing an instruction fetch cycle, and when the microcomputer is instructed to an operation mode in which the timing signal does not instruct an instruction fetch cycle; What is claimed is: 1. A data processing device comprising: a signal output circuit capable of outputting a signal for instructing command capture in place of the timing signal of the data processing device. 2. The above-mentioned microcomputer is a substitute microcomputer included in an in-circuit emulator, and its emulation operation can be stopped based on the control of a control unit that shares an internal data bus with the substitute microcomputer. A data processing device according to claim 1, characterized in that: 3. The emulation operation of the proxy microcomputer is stopped by executing a predetermined instruction supplied from the control unit, as set forth in claim 2. Data processing equipment. 4. The signal output circuit is capable of supplying a predetermined command to the proxy microcomputer to stop the emulation operation of the proxy microcomputer based on the timing signal output thereby. A data processing device according to claim 3, characterized in that: