KR860001785B1 - System program protection circuit of z80 cpu - Google Patents

Abstract

The protective circuit sectionalizes a system mode and a user mode to protect the system program from an illegal user instruction. The circuit comprises a clock generator which receives an external signal of (NMI) and CPU signal of (M1) and (iORQ) and whose output is connected to the clock latches; an I/O controller which receives a CPU signal of (M1, iORQ, RD,WR) and the output signal of the clock latches. When a CPU instruction is being fetched, Z-80 CPU is operated in the system mode because a flip-flop of clock latches is set at a high-level by the inverter of the clock generator and the OR gate of the clock latches.

Description

System program protection circuit of Z 80 CPU

1 is a pin configuration diagram of a typical Z 80 CPU.

2 is a circuit diagram of the present invention.

3 is a timing chart of the input / output instruction execution cycle of the present invention.

4 is a timing chart for the interrupt request / acknowledge cycle of the present invention.

5 is a timing chart for the mode change output command cycle of the present invention.

6 is a timing chart for the change cycle from the system mode to the user mode of the present invention.

7 is a timing chart for a typical instruction OP code fetch cycle.

* Explanation of symbols for main parts of the drawings

1: Clock pulse generator 2: Clock latch unit

3: Input and output control unit N ₃ , N ₆ : End gate

De: Decoder 5: Control signal latch

6: address latch part 7: data latch part

11: latch set part

In the present invention, a computer using a Z 80 CPU, Z, which distinguishes a user mode from a system mode of a computer in order to prevent a system program of a CPU from being destroyed by a user incorrectly executing a clear command or an input / output command. 80 CPU system program protection circuit.

In general, a multi-user computer system using a Z 8000 CPU or an MC 68000CPU includes a system mode and a user mode in hardware. In the user mode, input / output control commands and system programs are used. This write command to the existing memory cannot be executed. Therefore, when the user mode is to execute the above commands, the system mode or the interrupt method must be converted to the system mode, and then the monitor program or the operating system program executes the various commands. I'm trying to.

Therefore, when the user program executes a command to clear the memory area in which the monitor program or the operating system program exists, the system detects an error in the computer having both the user mode and the system mode. Although it is possible to prevent damage, the Z 80 CPU does not distinguish between the user mode and the system mode by hardware. If the user executes a clear instruction or an input / output instruction incorrectly during the execution of a user program, the user program as well as the system program can be prevented. All of them could be damaged until now.

The present invention has been made to solve such a problem, and by adding a circuit for separating the system mode and the user mode in hardware to the computer using the Z 80 CPU, the system is damaged if the program in the user mode is executed incorrectly The purpose is to prevent that.

This will be described in detail below.

신호단자에 낸드게이트(N₁, N₂), 인버터(I₁, I₂), 오어게이트(O₁, O₂), 지연기(Dy)로 구성된 클럭펄스 발생기(1)를 연결하고, 이 클럭발생기(1)의 오어게이트(O₂)의 출력과 외부로부터의 리세트 출력(

)을, D플립플롭((D₁-D₃)으로 구성된 클럭 래치부(2)의 플립플롭(D₁, D₂)을 제어하도록 한 래치세트부(11)의 오어 게이트(O₅)입력 단에 연결하며, 상기 클럭발생기(1)의 인버터(I₁)출력과 오어게이트(O₂)출력은 각기 클럭래치부(2)의 오어게이트(O₅)를 거친 플립플롭(D₃)과 오어게이트(O₄)에 가해지도록 연결하고, 오어게이트(O₄), 앤드게이트(N₃-N₅)로 구성된 입, 출력 제어부(3)에, Z 80의 각 출력단

및 클럭래치부(2)의 플립플롭(D₃)의 출력단(Q)을 연결하며, 모드 변경 출력단 (

)을 2입력 앤드 게이트(N₆, N₇)의 일단을 연결하고, 이들 앤드게이트(N₆, N₇)의 타단에 각기 입, 출력 제어부(3)의 각 앤드게이트(N₄, N₅)의 출력이 가해지도록 연결하며, 상기 앤드게이트(N₆) 출력은 데코더(De)를 거쳐 4비트 단위의 컨트롤 신호래치부(5), 8비트 단위의 어드레스 래치부(6), 데이타 래치부(7)의 래치용 IC (L₁-L₄)의

단자에 연결하고, 상기 콘트롤 신호 래치부(5)에는 Z 80의 리드, 라이트 신호(RD, WR)와 외부로 부터의 넌 마스크 에이블 인터럽트(Non Maskable Interrupt)신호(NMi)와 클럭 래치부(2)의 출력(S)이 입력되게 연결하며, Z 80의 어드레스 출력단에 연결된 어드레스 버스에는 데코더(De)의 어드레스 입력단(A₀, A₁)과 래치용 IC(L₃, L₃)의 각 어드레스 입력단(A₀-A₇, A₈-A₁₅)을 연결하고, 데이타 버스에는 래치용 IC(L₂, L₃, L₄)의 각 데이타 입, 출력단(D₀-D₇)과 래치용 IC(L₁)의 데이타 입, 출력단(D₀-D₃)을 연결하며, 또한 데이타 버스의 데이타(D₀)가 클럭 래치부(2)의 플립플롭(D₁)의 입력단(D)으로 입력되게 연결하여 구성한다.Z 80 CPU has its system and CPU control instructions

Connect a clock pulse generator (1) consisting of NAND gates (N ₁ , N ₂ ), inverters (I ₁ , I ₂ ), or gates (O ₁ , O ₂ ), and delay (Dy) to the signal terminal. The output of the or gate O ₂ of the clock generator 1 and the reset output from the outside (

) Is the or gate (O ₅ ) input of the latch set portion 11 to control the flip-flops D ₁ and D ₂ of the clock latch portion 2 composed of D flip-flops (D ₁ -D ₃ ). And an inverter (I ₁ ) output and an or gate (O ₂ ) output of the clock generator (1) and flip-flops (D ₃ ) passing through the or gate (O ₅ ) of the clock latch unit (2), respectively. each output end of the OR connected so applied to the gate (O _4), and the OR gate (O _4), the aND gate (N ₃ -N ₅₎ input, the output control section (3), Z 80 consisting of

And an output terminal Q of the flip-flop D ₃ of the clock latch unit 2, and a mode change output terminal (

) A two-input AND gate (N _6, N ₇₎ once the connection, these AND gates (N _6, N ₇₎ N _4, each AND gate of each of the input and output control unit 3 on the other end (a, and the N ₅ ) And the output of the AND gate (N ₆ ) is passed through a decoder (De) to the control signal latch unit (5) in units of 4 bits, the address latch unit (6) in units of 8 bits, and the data latch unit. (7) of the latch IC (L _1- L ₄ )

The control signal latch unit 5 includes the Z 80 read and write signals RD and WR, a non-maskable interrupt signal NMi, and a clock latch unit 2; ) Is connected to the input S, and the address bus connected to the address output terminal of Z 80 is connected to the address input terminals A ₀ and A ₁ of the decoder De and each address of the latch ICs L ₃ and L ₃ . Input terminals (A ₀ -A ₇ , A ₈ -A ₁₅ ) are connected, and each data input and output terminal (D ₀ -D ₇ ) and latches of the latching ICs (L ₂ , L ₃ , L ₄ ) are connected to the data bus. The data input and output terminals D ₀ -D ₃ of the IC L ₁ are connected, and the data D ₀ of the data bus is input to the input terminal D of the flip-flop D ₁ of the clock latch unit 2. Configure by connecting.

Referring to the operation and effects of the present invention configured as described above are as follows.

When the microprocessor, the Z 80 CPU, starts up for the first time, a reset operation is performed to enter the system mode.

)가 입력되면 래치세트부(11)의 오어 게이트(O₃)로 입력되는 리세트 신호(

)에 의하여 클럭래치부(2)의 플립플롭(D₁, D₂)이 세트되게 된다.That is, the reset signal from the outside (

Is input to the reset gate (O ₃ ) of the latch set unit 11

), The flip-flops D ₁ and D ₂ of the clock latch unit ₂ are set.

)가 하이레벨에서 로우레벨로 바뀌게 되므로, 클럭발생기(1)의 인버터(I₁)와 클럭래치부(2)의 오어 게이트(O₅)에 의하여 클럭래치부(2)의 플립플롭(D₃)의 입력단(CP)은 로우레벨에서 하이레벨로 되어 플립플롭(D₃)이 세트되게 되며, 이때에는 Z 80 CPU가 무조건 시스템 모우드로 되는 것이다.At this time, when reset is released and the first instruction starts to fetch,

) Is changed from the high level to the low level, the flip-flop (D ₃ of the clock latch unit 2 by the inverter I ₁ of the clock generator 1 and the or gate O ₅ of the clock latch unit 2). ), The input terminal CP is set from the low level to the high level so that the flip-flop D ₃ is set. In this case, the Z 80 CPU becomes the system mode unconditionally.

(None Maskable Interrupt)신호입력시, 즉 파워 정전시 또는 긴급히 수행하여야할 인터럽트 신호가 외부에서 요청되었을때는 이 또한 시스템 모우드로 되게 된다.Meanwhile, from the outside

When a (None Maskable Interrupt) signal is input, i.e. during a power outage or when an interrupt signal to be urgently requested is externally requested, this also becomes the system mode.

가 하이레벨에서 로우레벨로 되면, 이 신호는 오어게이트(O₁)를 거쳐서 하나는 Z 80 CPU의

단자로 입력되고, 또 하나는 오어게이트(O₂)와 래치세트부(11)의 오어게이트(O₃)를 거쳐 클럭 래치부(2)의 플립플롭(D₁, D₂)을 세트시키게 된다.That is, the external input as shown in FIG.

Goes from high level to low level, this signal goes through the or gate (O ₁ )

It is input to the terminal, and another one sets the flip-flops D ₁ and D ₂ of the clock latch unit 2 via the or gate O ₂ and the or gate O ₃ of the latch set unit 11. .

The output of the or gate O ₂ is delayed and input to the CP terminals of the latches L ₁ , L ₂ , L ₃ and L ₄ via the inverter O ₂ and the delay Dy.

At this time, the reason for the delay is that it is not known whether the Z 80 CPU is in user mode or system mode, and if the current system code is present, the following information should be stored after the execution of the command is completed. Then, address values A _{0 to} A ₁₅ of information are respectively input to the address latch unit 6, and old data values of the Z 80 CPU are read and written to the data latch unit 7 according to i / o instructions. This is for latching the traffic light into the control signal latch section 5, respectively. At this time, the output of the NAND gate N ₅ of the input / output control unit 3 and the signal of the mode change output terminal CS which decodes the address bus are input to the NAND gate N ₆ at a high level. ) Is not output to each of the latch portions 5, 6 and 7.

입력신호에 의한 동작이 Z 80 CPU에 설계된 프로그램대로 시스템모드로써 동작된 이후에

입력신호가 로우레벨에서 하이레벨로 될때, 또는 인출 명령시에 발생되는

이 LOW일때도 항상 시스템모드가 유지되는 것이다.after

After the operation by the input signal is operated in the system mode as the program designed for the Z 80 CPU

Generated when the input signal goes from low to high

The system mode is always maintained even in this LOW state.

가 모두 로우레벨이 되므로 낸드 게이트(N₁)의 출력은 로우레벨로 변하여 액티브 상태가 되고, 또한,

신호가 인버터(I₁), 낸드게이트(N₂)를 통하여 오어게이트(O₁)의 출력단에는 하이레벨로 나타나게 되므로

는 액티브 상태로 되지 못하게 된다.On the other hand, when the Z 80 CPU receives a simple interrupt request from the outside, M ₁ and

Since both are at the low level, the output of the NAND gate N ₁ is changed to the low level, and becomes active.

Since the signal is displayed at the high level at the output terminal of the or gate O ₁ through the inverter I ₁ and the NAND gate N ₂ .

Will not become active.

Meanwhile, since the output of the NAND gate N ₁ outputs the output of the latch set unit 11 to the high level through the output of the or gate O ₂ , the flip-flops D ₁ and D ₂ are set. The output of the clock pulse generator 1 activates the terminals CP of the latching ICs L _{1 to} L ₄ of the latch sections 5, 6, and 7 from the low level to the high level. Allow input values 5, 6, and 7 to latch.

That is, since the output signal S of the output terminal Q of the flip-flop D3 of the clock latch unit 2 becomes high level, at this time, the mode of the Z 80 CPU becomes the system mode. The corresponding values are stored in the address, the data latches 6 and 7 and the control signal latch 5.

의 입력에 따라 낸드게이트(N₁)의 출력이 액티부상태에서 해제될때에는, 플립플롭(D₃)의 단자(CP)로 입력되는 오어게이트(O₅)의 출력이 로우레벨에서 하이레벨로 되므로, 상기한 바에서와 같이 이미 세트된 플립플롭(D₂)의 출력을 래치시켜 플립플롭(D₃)의 출력단(Q)에서는 하이레벨이 나타나게 되어 Z 80 CPU의 모우드가 시스템 모우드로 되는 것이다. 이때, Z 80 CPU로 부터 입력되는

와

는 모두 액티브 상태 즉, 로우레벨 상태이므로, M₁의 로우레벨이 인버터(I₁), 오어게이트(O₄) 및 낸드게이트(N₃)를 통하게 되므로, 외부로 출력되는

는 로우레벨로 출력되게 된다.Meanwhile,

When the output of the NAND gate N ₁ is released in the active state according to the input of, the output of the or gate O ₅ input to the terminal CP of the flip-flop D ₃ goes from the low level to the high level. Therefore, as described above, the output of the already set flip-flop (D ₂ ) is latched so that a high level appears at the output terminal (Q) of the flip-flop (D ₃ ) so that the mode of the Z 80 CPU becomes the system mode. . At this time, input from Z 80 CPU

Wow

Since are all active states, that is, low level state, the low level of M ₁ is passed through the inverter (I ₁ ), the or gate (O ₄ ) and the NAND gate (N ₃ ), which is output to the outside

Will be output at the low level.

신호나 일반 인터럽트 요청시, 본 발명의 하드웨어가 사용자 모드시에는 그 사용자 모드를 정지시켜 시스템 모드로 하는 제어 출력신호 (

, S)를 하이레벨로 출력되게 하고, 제어출력신호 (

)상태는 그대로 유지시키는 변환 동작을 행하여, 시스템 루틴을 행하도록 하는 것이다.The same process from the outside on the Z 80 CPU

When a signal or a general interrupt request is requested, the control output signal for stopping the user mode to the system mode when the hardware of the present invention is in the user mode (

, S) to the high level and the control output signal (

The conversion state is maintained as it is, so that the system routine is executed.

가 LOW로 되는 것이므로, 이때는 제4도와 같이 앤드게이트(N₂)의출력은 하이레벨이 되어 오어게이트(O₁)를 거쳐, Z 80 CPU의

에 연결되는

신호를 보내고, 다른 하나는 오어게이트(O₃)를 거쳐 D플립플롭(D₁, D₂)을 각기 세트시킴과 동시에 각 래치부(5, 6, 7)의 단자(CP)에 로우레벨이 인가되므로 현재 진행중인 내용의 정보값이 각기 래치부(5, 6, 7)에 래치된다.Therefore, if a user wants to execute i / o command in a computer using Z 80 CPU,

Since LOW becomes low, at this time, the output of the AND gate N ₂ becomes high level through the OR gate O _{1 as} shown in FIG.

Connected to

Signal, the other sets the D flip-flops D ₁ and D ₂ via the or gate O ₃ , and at the same time, a low level is applied to the terminal CP of each latch section 5, 6, 7. The information value of the content currently in progress is latched by the latch portions 5, 6, and 7, respectively.

가 원 위치로 해제되면 오어게이트(O₅)출력이 하이레벨에서 로우레벨로 되므로 세트된 플립플롭(D₃)의 출력이 계속 high를 유지하여 시스템 모드 상태로 유지시킨다.after

When is released to the home position, the or gate (O ₅ ) output goes from high level to low level, so the output of the set flip-flop (D ₃ ) is kept high to maintain the system mode.

가 원 위치로 해제됨에 따라 플립플롭(D₃)의 출력은 로우레벨로,

가 하이레벨로 되므로서 상술한 바와같이

가 로우레벨로 되어 사용자 모드로 전환시키는 것이다.At this time

The output of flip-flop (D ₃ ) goes to low level as is released to the home position.

Becomes high level, as described above.

Goes to the low level and switches to user mode.

신호가 데코더(De)를 동작시켜서 래치부(5, 6, 7)의 내용을 시스템 모드로의 제어계로 선택시켜서 현재 시스템 모드가 i/o명령을 수행하고 있었다면 이를 시스템 모드의 레지스터로 저장시키고, i/o 명령이 없었다면 시스템모드의 제어계로써 상기 내용을 처리하여 i/o명령을 수행하는 것이다. 이러한 상태에서는 사용자 모드에서 내려진 입, 출력장치 구동명령 i/o인스트럭션을 직접 입, 출력 장치에 전달시키지 않고, 이를시스템모드로 전환한 다음 그 정보를 시스템 모드의 명령계통에 내려져서 시스템 계통에서 처리하여야 할 내용이 마무리 된뒤 i/o인스트럭션을 수행하도록 하는 프로그램을 시스템 모드에서 루틴으로 처리한다.That is, the contents of the i / o command in the aforementioned user mode are stored in the latch units 5, 6, and 7, while the system is switched to the system mode by the flip-flop D ₃ , and the operation is performed when the system mode is switched. Control signal to be

The signal operates the decoder De to select the contents of the latches 5, 6 and 7 as the control system to the system mode, and if the current system mode is performing i / o commands, it stores them in the system mode register. If there is no i / o command, the system processes the contents and executes the i / o command. In this state, I / O instructions issued from the user mode are not transferred directly to the I / O device. Instead, the system is converted to the system mode and the information is sent to the system mode to process the system. After the work is done, the program that executes the i / o instructions is processed as a routine in system mode.

를 high로 하고 출력데이타 중 D₀를 high로 하고 플립플롭(D₁)를 제5도와 같이 세트한다.Then, when switching from the system mode to the user mode, the output command is used.

To high, D ₀ of the output data to high, and flip-flop (D ₁ ) is set as shown in FIG.

이 두번 액티브(Active)되야만 플립플롭(D₂)의 출력이 플립플롭(D₃)으로 래치 되고, 출력명령 바로 다음의 명령을 시스템 모드에서만 사용할수 있는 메모리에서 인출되고 실행되며, 그 다음 명령의 인출시는 사용자 모드에서 행하여지는 것이다.However, after executing the output command in system mode, it does not go to user mode.

Twice it have to be active (Active), the output of the flip-flop (D ₂₎ are latched by the flip-flop (D _3), it is drawn out and execute the output instruction immediately following the instruction in the memory that can only be used in the system mode, then the command Withdrawal is done in user mode.

In addition, in the hardware configuration of the user mode and system mode, when configuring the dual memory module, the software should be processed as follows.

That is, in the interrupt service routine, after inputting the mode value S from the register L ₁ of the control signal latch unit 5 as an input command, the mode value S can be saved and returned to return the mode value at the time of performing the interrupt return function. In the interrupt return function, the interrupt disable mode value is latched to the flip-flop (D ₁ ) as an output command and the return interrupt command is processed in order.

At this time, if the interrupt disable function is deleted, the mode value is lost if another interrupt is performed after the instruction composed of the latch of the flip-flop D ₁ is executed.

서비스 루틴에서는, 콘트롤 신호 래치부(5)의 래치용 IC(L₁)에 래치된

값이, 외부

신호인가 또는 사용자 모우드에서 i/o 명령을 수행하므로써 발생된

신호인가가 식별되는 것이다.Also,

In the service routine, the latches of the control signal latch unit 5 are latched to the latching IC L ₁ .

Value, external

Generated by performing an i / o command on a signaled or user mode

Signaling is to be identified.

)시에 앤드게이트(N_7,N₆)를 제어하므로써 클럭래치부(2)의 플립플롭(D₁)을 홀드(hold)시켜 시스템 모드시의 플립플롭(D₃)출력상태를 LOW로 변하지 않도록 유지시키는 것이며, 시스템 모드에서 i/o명령실행시는 Z 80 CPU에

가 가해지면서,

또는

의 제어명령이 컨트롤 신호 래치부(5)로 래치되거나

또는

의 출력으로써 직접 작용하는 것이다.On the other hand, in the input and output control unit 3, each output (

The flip-flop D ₁ of the clock latch unit 2 is held by controlling the AND gates N _7, N ₆ so that the output state of the flip-flop D _{3 in} the system mode does not change to LOW. In the system mode when running i / o commands.

Is added,

or

Control command is latched to the control signal latch section 5 or

or

It acts directly as the output of.

A₀-A₁₅)를 선택적으로 제어하는 회로를 구성하여 사용자 모드와 시스템 모드를 하드 웨어적으로 분리하므로써, 사용자 조작의 잘못에 의한 시스템 파괴를 미연에 방지할 수 있는 유익한 특징이 있는 것이다.The present invention is a control signal according to each of these situations in the system mode and user mode when using the Z 80 CPU (

A ₀ -A ₁₅ ) can be configured to selectively control the circuit by separating the user mode and the system mode in a hardware manner, which is an advantageous feature that can prevent the system damage due to user error.

Claims (1)

In a computer system using a Z 80 CPU, a clock generator comprising NAND gates (N ₁ , N ₂ ), or gates (O ₁ , O ₂ ), inverters (I ₁ , I ₂ ), and a delay (Dy) 1) signal of Z 80 CPU at the input of

), (

) And external signal (

) Is connected to the input, the output of the clock generator 1 is connected to the input terminal (CP) of each latch unit (5, 6, 7), the output of the or gate (O ₂ ), inverter (I ₁ ) Signal and reset (

Signal is connected to the clock latch unit 2 through the or gates (O ₅ ) and (O ₃ ), and an input / output control unit composed of NAND gates (N ₃ -N ₅ ) and or gate (O ₄ ) (3) the CPU signal (

) And the output signal of the clock latch unit 2 are inputted, and the mode change output terminal signal (

) Is output through the NAND gate (N ₆ ), and the output of the decoder (De) is connected to each terminal of each latch IC (L _1- L ₄ ) (

The output S of the clock latch unit 2 and the external signal (

) And the signal from the CPU (

) Is connected to the input bus, and the address terminals A ₀ , A ₁ , (A ₀ -A ₇ ) and (A _8- ) of the decoder (De), the latching IC (L ₃ ) and (L ₂ ) A ₁₅ ) is a system program protection circuit for a Z 80 CPU, comprising a data input and an output terminal of each latch IC (L ₁ , L ₂ , L ₃ , L ₄ ) connected to a data bus.

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