JPS5582328A - Common bus control system - Google Patents

Common bus control system

Info

Publication number
JPS5582328A
JPS5582328A JP14622778A JP14622778A JPS5582328A JP S5582328 A JPS5582328 A JP S5582328A JP 14622778 A JP14622778 A JP 14622778A JP 14622778 A JP14622778 A JP 14622778A JP S5582328 A JPS5582328 A JP S5582328A
Authority
JP
Japan
Prior art keywords
ioc
signal
address
transmitted
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14622778A
Other languages
Japanese (ja)
Other versions
JPS583247B2 (en
Inventor
Takao Arai
Toshiki Hatanaka
Toshio Katsuki
Ryushi Hiroya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14622778A priority Critical patent/JPS583247B2/en
Publication of JPS5582328A publication Critical patent/JPS5582328A/en
Publication of JPS583247B2 publication Critical patent/JPS583247B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to give an IOC register address independently by providing signal transmission busses of address information commonly from common control unit CTL to I/O control unit IOC and providing them from IOC to CTL for every IOC.
CONSTITUTION: Common busses are constituted by address information lines ADBOWADB15, S signal (signal indicating availability of address information) line SO from CTLWIOC which is common to every IOC, and S signal lines S1W Sn from IOCWCTL which are provided for every IOC. In respect to information transfer from main memory MMWIOC, register address information of IO is transmitted to a common bus through control part CONT of CTL, and simultaneously, a S signal is transmitted to the SO line, and data is stored in a pertinent IOC register. Information from IOCWMM is transmitted to the common bus, and simultaneously, the S signal is transmitted to pertinent one of signal lines S1WSn, and data is accessed at the pertinent address of MM. As a result, the IO register address can be given independently of the MM address.
COPYRIGHT: (C)1980,JPO&Japio
JP14622778A 1978-11-27 1978-11-27 Common bus control method Expired JPS583247B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14622778A JPS583247B2 (en) 1978-11-27 1978-11-27 Common bus control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14622778A JPS583247B2 (en) 1978-11-27 1978-11-27 Common bus control method

Publications (2)

Publication Number Publication Date
JPS5582328A true JPS5582328A (en) 1980-06-21
JPS583247B2 JPS583247B2 (en) 1983-01-20

Family

ID=15402975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14622778A Expired JPS583247B2 (en) 1978-11-27 1978-11-27 Common bus control method

Country Status (1)

Country Link
JP (1) JPS583247B2 (en)

Also Published As

Publication number Publication date
JPS583247B2 (en) 1983-01-20

Similar Documents

Publication Publication Date Title
JPS57105879A (en) Control system for storage device
JPS5786959A (en) Data transfer control system
JPS5455132A (en) Input-output control system
JPS5476034A (en) Bus data transfer system
JPS54142950A (en) Data transfer system
JPS5582328A (en) Common bus control system
JPS55108027A (en) Processor system
JPS6478362A (en) One connection preparation of several data processors for central clock control multi-line system
JPS56118165A (en) Processor of video information
JPS5563422A (en) Data transfer system
JPS5487148A (en) Data processing system by multiplex processor
JPS5552130A (en) Information processing unit
JPS57125427A (en) Circuit for transmitting simultaneously command signal
JPS55150032A (en) Data transfer system
JPS55157027A (en) Input and output transfer control unit
JPS54104247A (en) Information processing system
JPS5578321A (en) Data transfer control system
JPS54140841A (en) Memory control system of multiprocessor system
JPS52129241A (en) Memory control system
JPS54157444A (en) Memory control system
JPS54122060A (en) Inter-processor information transfer system
JPS57168318A (en) Data transmitting device
JPS5622157A (en) Process system multiplexing system
JPS57127259A (en) System for high-speed data transfer
JPS55147720A (en) Multimemory bus