JP2903551B2 - Multiprocessor synchronization mechanism - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization mechanism of a multiprocessor system, and more particularly, to hardware capable of realizing a synchronization operation from a processor as a single memory access cycle.

[Conventional technology]

In a conventional multiprocessor system: (1) Synchronization is performed by software using a main storage device of a processor.

(2) A method has been proposed in which a wired OR signal is prepared, and detection of establishment of synchronization by issuing a synchronization request from all processors is performed by hardware.

[Problems to be solved by the invention]

However, in the method (1), it is necessary to scan the flag table by software, which takes a long processing time. In the method (2), although the scanning overhead is eliminated, the wired-OR signal is negated by software in order to prevent a preceding synchronization operation from being erroneously interpreted as a next synchronization operation. You need to monitor that.

Furthermore, if there is a faulty processor, an infinite wait occurs. To avoid this, when a watchdog timer is incorporated, there is a problem that processing becomes complicated and overhead increases.

An object of the present invention is to implement a synchronization mechanism with less overhead by implementing the synchronization problem as hardware.

In the present invention, since the synchronization mechanism can be regarded as a single memory access from the processor, there is no overhead for the software processing. Further, in the present invention, since the processor interface as the memory access is realized, synchronization can be directly described only with a standard descriptor without using a library even from an existing high-level language such as FORTRAN, C. In addition, it is possible to keep the application level synchronization overhead extremely low.

[Means for solving the problem]

The configuration of the synchronization mechanism of the multiprocessor according to the present invention is, first, in a multiprocessor having a plurality of element processors, an apparatus for realizing a synchronization mechanism between all processors in hardware, A plurality of synchronization adapters provided for each element processor and occupying one memory address of the element processor, and a single synchronization unit which receives a synchronization request line output from the synchronization adapter of each element processor and generates a synchronization grant signal. An apparatus configured to implement a mechanism in which a synchronization processor starts the synchronization process by accessing the memory address of the synchronization adapter and completes the memory access when the synchronization is established. , The grant line from the synchronization unit as the synchronization adapter After waiting until the gate is asserted, the synchronous request line is asserted, and after waiting for the synchronous grant line to be asserted, the request line is negated and a mechanism for simultaneously terminating the access cycle of the processor is provided. When the synchronous request lines from all the synchronous adapters are asserted, all the synchronous grant lines connected to each synchronous unit are asserted, and thereafter, all the synchronous request lines from all the synchronous adapters are negated. And a second mechanism for realizing a synchronization mechanism as a memory access according to claim (1), wherein a mechanism for negating the synchronization grant line is provided. In the meantime, start the watchdog timer instead of the normal bus monitoring timer, and set the synchronization timeout. Thirdly, a mechanism for transmitting a synchronization to a processor that has requested synchronization is added. Thirdly, in the synchronization mechanism according to the first aspect of the present invention, a processor that does not participate in synchronization is permitted to be synchronized. Fourthly, a signal line indicating a processor is added, and fourthly, the synchronization unit of the synchronization mechanism according to claim 1 is included in logic for detecting assertion of synchronization request lines of all synchronization units. A wired OR is used for all or a part of the AND gate and the AND gate included in the logic for detecting the negation of the synchronization request lines of all the synchronization units.

[Action]

The synchronization mechanism of the present invention occupies one memory address of the element's processor.

The synchronization process is started by accessing the memory address of the synchronization adapter by the processor that performs synchronization, and a mechanism that completes the memory access when the synchronization is established is realized.

Upon synchronization, the synchronization unit detects that the synchronization request lines of all processors have been asserted, and asserts the synchronization grant line of each synchronization unit. Further, the synchronization unit has a mechanism for detecting assertion of a synchronization acknowledge line from all processors and negating the synchronization grant line.

At this time, a watchdog timer set in advance for the synchronization timeout time is started as a bus error monitoring timer.

The synchronization mechanism according to claim 1, wherein a signal line indicating a processor to be synchronized and a synchronization request line and a synchronization acknowledge line of a processor whose signal line is asserted are allowed to allow the existence of a processor not participating in synchronization. And a synchronization unit for determining the value of the synchronization grant line.

〔Example〕

 Next, examples of the present invention will be described.

FIG. 1 shows an example of an apparatus composed of two processing apparatuses using claims (1), (2) and (3). In the figure, an asterisk (*) added to the end of the signal name indicates negative logic. In the figure, 11 and 12 are independent processing units, 13 is a synchronization unit composed of a sequential circuit, and 11 and 13 are connected by a request line 111, a grant line 112, and a presence line 113, and between 12 and 13. Is request line 12
1, connected by a grant line 122 and a presence line 123.

The processing devices 11 and 12 have the same configuration,
Has a decoder 119 for decoding an address output from the processor 117 and generating a select signal for the synchronous adapter, a bus counter 118 for generating a bus error signal BERR *, and a watch for performing a bus error count process during the synchronization process. Dog timer 116 and synchronization adapter 115
Consists of

Processor 117 outputs an address to address bus AD, asserts address strobe AS *, and starts a bus cycle. The peripheral device asserts the DTACK * signal to request the processor to end the bus cycle. The bus counter 118 monitors the length of AS * to prevent the bus cycle from being infinitely interrupted by accessing a non-existent device, and asserts the bus error signal BERR * if the assertion time of AS * is too long. Then, a bus error is transmitted to the processor.

Using the above device, a synchronization mechanism called a barrier is realized in hardware. The barrier is a method of establishing synchronization between all the processors to be synchronized. The concept of barrier is shown in FIG. Hereinafter, a request for synchronization from the processor is referred to as “issue of a barrier”, and establishment of synchronization is referred to as “establishment of barrier”.

When issuing a barrier using this apparatus, the processor accesses a memory address assigned to the decoder 119. The synchronization adapter 115 cooperates with the synchronization unit 13 and ends the bus cycle when the barrier is established. Normally, the detection time of BERR * by the bus counter 118 is smaller than the maximum value of the waiting time until the establishment of the barrier, so that the bus counter is prohibited from asserting the BERR * signal using the CINH signal line during the barrier processing. .

In claim (2), the maximum wait time for synchronization can be set by activating a programmable watchdog timer by a CNT signal from the synchronization adapter instead of the bus counter, and the synchronization timeout is set via the BERR * signal line. Is transmitted to the processor as a bus error. By making the watchdog timer programmable, the synchronization error reference can be set appropriately.

Hereinafter, the operation between the synchronization adapter 115 and the synchronization unit 13 will be described.

In FIG. 2, the data is input to the synchronization adapter 115. The timing of the main signal is shown.

(In) (out) before the signal name indicates the direction of the signal as viewed from the synchronization adapter.

The presence lines 113 and 123 are signal lines indicating that the processing device is a target of the barrier, and are asserted in the processor that generates the signal in FIG.

FIG. 2 shows a first barrier issuance indicated by checkpoints T1 to T5 and a second barrier indicated by checkpoints S1 to S4. Second
Indicates the timing of occurrence of a bus error.

A description of a normal process using the first barrier issuance will be given in time.

(Z) Barrier receivable phase.

(A) T1: start phase: the processor 117 starts accessing the address of the synchronous adapter, and the decoder 119
Assert *.

(B) T2: Request phase: The synchronization adapter 115 confirms that the grant line is negated, asserts the request line 111, and issues a synchronization process to the synchronization unit.

(C) T3: Grant phase: The synchronization unit 13 detects that the request lines of all the processing units to be synchronized are asserted, and simultaneously asserts a grant signal to each processing unit. The synchronous adapter 115 asserts CS * in response to the assertion of the grant, terminates the bus cycle, and
Inform the processor of the establishment of ier and negate the request line to notify the synchronization unit of the completion of the synchronization operation. (T4) (d) T5: Recovery phase: The synchronization unit 13 detects that the request lines from all the processing devices have been negated,
The grant line is negated, and the synchronization process ends.

The processing time from T3 to T5 is the signal propagation time, which is sufficiently shorter than the processing time of the normal processor,
The barrier issue S1 arrives later than T5. Accordingly, the same processing as in the above (a) to (d) is performed for the subsequent barrier issuance. However, the above (d)
In this phase, if some processing unit fails and the negate T4 of the request line propagates to the synchronization unit 13 with a delay or does not propagate at all, a situation occurs in which S1 precedes T5. In this case, the following processing is performed.

(E) S2: Late start phase: As shown in (a), the synchronous adapter 115 issues a request after waiting for the grant line negation T5, and determines whether the first barrier has been established earlier.
Is defined as the establishment of a barrier.

The time-out process is shown in the second barrier. S3
The watchdog timer has asserted BERR * because CNT was already asserted. In this case, the following suspension phase is performed.

(F) S4: Stop phase: By BERR *, the processor
The bus cycle is interrupted, whereby CS * is negated, and the synchronization adapter 115 negates S4, and returns to the barrier receivable state (z).

FIG. 3 shows a configuration of the synchronization unit satisfying the timing in the configuration of FIG. The request line is converted by the NOT gate 34 into an open line 35 requesting negation of the grant. The operation of the synchronization unit in the (d) restoration phase can be read as negating the grant line by asserting all release lines, and the AND gate having the number of request lines or the number of release lines of the processing device can be read. Via the SET input of SR flip-flop 33 or 33
Connected to the reset input. The 33 Q outputs are distributed to all processors as a grant signal.

FIG. 3 shows OR gates 36 and 37 corresponding to claim (3).
Is added. Since the existence line * is negative logic, the inputs of the AND gates 31 and 32 are always asserted with respect to the gate whose existence line * is negated by the OR gates 36 and 37, and the barrier of the processor negating the existence line * Remove from operation target.

Each of the AND gates 31 and 32 needs to input the number of processing devices, and it becomes difficult to realize the increase in the number of processing devices. Also, the synchronization unit 13 is connected. Request line,
Grant lines and existence lines also increase in proportion to the number of processing devices, but the problem can be solved by using claim (4).

FIG. 4 shows an example of a configuration using wired OR to which claim (4) is applied. Presence line * is wired OR by bus 43
In order to realize the selective barrier of claim (3), an OR gate 49 ORs a request line, a release line and an existence line.
And a wired OR is realized by the buses 41 and 44. The ground line is broadcast by the bus 42. 4, the request lines of a plurality of processors,
Integration of ground line and existing line, request line '45, ground line '
46, the existence line '47 and the release line '48 are generated. These signals may be connected to the request line, the existence line, the release line, and the grant line of the synchronization unit 13. However, the NOT gate 3 is removed.

When request lines, grant lines, and existence lines from all synchronous adapters are connected by wired OR as shown in Fig. 4, the gate
31,32,36,37 and bus 43 can be removed,
The synchronization unit 13 can be constituted only by the SR flip-flop 33. In this case, the request line '45 is connected to the S input of the SR flip-flop 33, and the release line '48 is connected to the SR flip-flop 33.
To the R input.

In FIG. 3, if the NOT gate is moved to the synchronous adapter side and the release line is read as a synchronous acknowledge line, it can be regarded as the configuration of claim (5). In particular, in the configuration using the wired OR in claim (4), it is more natural to regard the processing device side as a synchronous adapter than the wired OR, and this corresponds to the configuration in claim (5).

〔The invention's effect〕

In the present invention, a synchronization mechanism with little overhead is implemented by implementing the synchronization-related problem as hardware.

In the present invention, since the synchronization mechanism can be regarded as a single memory access from the processor, there is no overhead for the software processing.

Furthermore, in the present invention, since the processor interface as the memory access is realized, the FORTRA
Even from existing high-level languages such as N and C, synchronization can be described directly with only standard descriptors without going through a library.
It is possible to keep the synchronization overhead at the application level extremely low.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a timing diagram of main signals input to a synchronization adapter, FIG. 3 is a configuration diagram of a synchronization unit, and FIG. FIG. 5 is a conceptual diagram of the barrier. 11,12 …… Independent processing unit, 13 …… Synchronization unit, 11
1,121 …… Request line, 112,122 …… Grant line, 113,123…
... presence line, 115 ... synchronization adapter, 116 ... watchdog timer, 117 ... processor, 118 ... bus counter,
119: Decoder, 31, 32: AND gate, 33: SR flip-flop, 34: NOT gate, 35: Release line, 36, 37
…… OR gate, 41,42,43,44 …… Bus, 45,46,47,48 ……
Input to synchronous unit, 45: request line, 46: grant line, 47: presence line *, 48: release line, 49: OR gate.

Continuation of the front page (56) References JP-A-64-23361 (JP, A) JP-A-62-232065 (JP, A) Kai Hwang "Advanced Computer Architecture" McGraw Hill 1993 p363-367 Proceeding OSP ASP. {III} Vol. 24 spe lsne 1989 p54-63 Rajiv Gupta "The F uzzy Barriev: Mecha nism for High Spee d Synchronazdfim o f Processors " (58) investigated the field (Int.Cl. ^6, DB name) G06F 15/16 WPI JOIS INSPEC

Claims (5)

(57) [Claims] An apparatus for realizing a synchronization mechanism among all processors in hardware in a multiprocessor having a plurality of element processors, wherein one memory address of each element processor is provided for each element processor. A plurality of synchronization adapters to be occupied, and a single synchronization unit that receives a synchronization request line output from the synchronization adapter of each element processor and generates a synchronization grant signal, and the processor that performs synchronization is a processor of the synchronization adapter. A synchronization process started by accessing the memory address, and a mechanism for completing the memory access when the synchronization is established is realized, wherein the grant from the synchronization unit as the synchronization adapter is provided. Wait until the line is negated and then the synchronization request line After asserting and waiting for the synchronous grant line to be asserted, a mechanism for negating the request line and terminating the access cycle of the processor at the same time, and as a synchronous unit, synchronous request lines from all synchronous adapters A mechanism for asserting all of the synchronous grant lines connected to each synchronous unit when asserted, detecting that all synchronous request lines from all synchronous adapters have been negated, and negating the synchronous grant line A synchronization mechanism for a multiprocessor, comprising: 2. A device for realizing a synchronization mechanism as a memory access according to claim 1, wherein a watchdog timer is activated instead of a normal bus monitoring timer during the synchronization process. A synchronization mechanism characterized by adding a mechanism for transmitting a synchronization timeout as a bus error to a processor that has requested synchronization. 3. The synchronization mechanism according to claim 1, wherein a signal line indicating a processor to be synchronized is added to allow a processor not participating in synchronization to exist. 4. The synchronizing unit according to claim 1, wherein said synchronizing unit includes an AND gate included in a logic for detecting assertion of a synchronizing request line of all synchronizing units, and a synchronizing request line of all synchronizing units. A configuration method of a synchronization mechanism, wherein a wired OR is used for all or a part of an AND gate included in a logic for detecting negation. 5. An apparatus according to claim 1, further comprising a synchronization acknowledge line added to said synchronization mechanism, wherein said synchronization request line is asserted after waiting until a synchronization grant line from said synchronization unit is negated. A synchronous adapter having a mechanism for waiting for a synchronous grant line to be asserted and then asserting a synchronous acknowledge line and simultaneously terminating the access cycle of the processor, and when a synchronous request line of all processors is asserted, each synchronous A synchronizing mechanism for a multiprocessor, comprising: a synchronizing unit having a mechanism for asserting the synchronizing grant line of a unit and negating the synchronizing ground line with assertion of synchronizing acknowledge lines from all processors.