JPS61239348A - Direct memory access control circuit - Google Patents

Abstract

PURPOSE:To improve the execution efficiency of a microprocessor, by using the 1st bus which is directly connected with the microprocessor in parallel with the 2nd bus when the 2nd bus is used by a DMA device and the 2nd memory device. CONSTITUTION:This bus control circuit 32 of a direct memory access control circuit stops the operation of a microprocessor, when a direct memory access device (DMA device) connected to the 2nd bus 112 performs a data transferring process with the 1st memory device connected to the 1st bus 111. The bus control circuit 32 permits the microprocessor to make operations by using the 1st bus 111, when the DMA device performs a data transfer process with the 2nd memory device connected with the 2nd bus 112.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a direct memory access control circuit used in a computer system to which a direct memory access device is connected.

``Prior Art'' In order to improve efficiency when performing data transfer processing from an input/output device to another memory device, some input/output devices have been added with a function to perform data transfer processing operations. This is called a direct memory access (hereinafter referred to as DMA) device. FIG. 7 shows an example of a combi coater system to which such an MA device is connected.

This system uses a microprocessor (C: P
a first bus 111 that is directly connected to
and a second bus 1 indirectly connected to the CPU 10.
1. 11. and are connected by a bus control circuit 12.

First bus 11. For example, one memory device j41
(this will be referred to as a first memory device) is connected.

The second bus 112 also includes one J, ) MA device 13 and one memory device I4. The DMA device 13 (which is referred to as a second memory device) is connected to the first memory device 141 or the second memory device as necessary.
Data transfer processing is performed between the memory device 142 and the memory device 142 of the memory device 142 . The bus control circuit 12 includes a D
A first bus 11 for MA requests (DMA requests l-) and various signals for their execution. and second bus 11
It is provided to control the transfer between the two.

FIG. 8 is a block diagram of the configuration of the pass line and the bus control circuit 12.

(Configuration of Pass Line) In the figure, the left side of the bus control circuit 12 has a first
Bus 11. A second bus 11. is connected to the right of the bus control circuit 12. is connected.

As shown in the figure, the first bus 111 is composed of nine types of transmission lines each consisting of one or more parallel transmission lines, and the second bus 112 is similarly composed of eight types of transmission lines. ing.

Each transmission path is named according to its function, and DMA
DMA request that transmits a request signal)llz, 1121
, DMA request 0 transmitting a signal to permit DMA
K11.2.11,2, address bus 11.3.1128 for transmitting address signals, bus active bus 1121 for transmitting signals indicating whether or not the pass line is in use, from the DMA device 13 shown in FIG. A read signal when writing data to the device 141 or 1426, or conversely, a memory device 14. ．． DM the contents of 14゜
Read/write mode 1115 and 112S transmit a write signal when writing to the A device 13, strobes 111G and 11□5 transmit a strobe signal to control the data write operation, and transmit a response signal when data writing is completed. The data bus 11.8.112B transmits data, and the start 1119 transmits a timing pulse for restarting the CPU operation shown in FIG.

Hereinafter, the first bus 11. The transmission line belonging to the second bus 112 will be denoted by the word "first", and the transmission line belonging to the second bus 112 will be denoted by the word "second".

(Bus control circuit) configuration> On the other hand, bus control circuit Ha 12 Ha, DMA I
The JQuest/○ is composed of a control 21, an address bus transceiver 22, an address decoder 23, a CPU lift timing generator 26, a timing gate control 24, and a data bus transceiver 25.

DM A IJ Quest 10K Control 21 Ha, second DMA! A circuit having gates connected to each other so as to transfer the signal of JQuest) 112+ to the first DMA request 1111 and the signal of the first DMA request 0K1112 to the second DMA request 0K11□2. It is.

Address bus transceiver 22 and data bus transceiver 25 are circuits each having bidirectional gates that transfer addresses and data in designated directions.

The address decoder 23 determines whether the address transmitted through the second bus 1123 is from the first memory device 141 connected to the first bus 11 or from the second memory device 142 connected to the second bus 112. This is a circuit that determines whether it is the same and outputs a signal 27 for identifying it.

Based on the identification signal 27 of the address decoder 23, the timing gate control 24 outputs the above-described transfer direction designation signal 28 to the address bus transceiver 22 and data bus transceiver 25.

Further, this timing gate control 24 is connected between each read/write mode 11.5.1.1□ of the first bus 111 and the second bus 112, and the strobe 11.6.1.
126 and between the reply 1111.1121, and the first bus active 11, 4 and the second bus active 112. This circuit has a gate that connects the two as necessary.

The CPU restart timing generator 26 is a second
11. monitors the bus active 1124 and restarts the CPU start signal at the timing of its falling edge.
This is a circuit that outputs to .

(Bus control time! (7) Operation) The operation of the circuit shown in FIG. 8 will be explained using the timing chart of FIG. 9 and comparing FIGS. 7 to 9.

First, the DMA device 13 shown in FIG.
A case will be described in which data transfer processing is performed with the second memory device 142 connected to the second memory device 142.

A DMA request signal is issued from the DMA device 13 (second DMA request) 1121 rises (FIG. 9(a)),
This signal is transferred directly to the first DMA request 11.1 through the DMA request 10K control 21.

In response to this, the CPU 10 starts up the first DMA IJ quest 0K11,2 ((b) in the figure).

At the same time, the first bus 111 that has been in use is stopped and the first bus active 11.4 is turned down ((C) in the same figure).

When the second DMA request 0K1122 falls, the DM
The A device 13 causes the second DMA request 1121 to fall, and causes the second bus active 1124 to rise ((d) in the figure). Then, the mode designation signal is sent to the second lead/
The write mode 11□5 is set, and the address signal and data are placed on the second address bus 1]23 and the second data buses 11 and 8, respectively.

Thereafter, the DMA device 13 transfers one word of data to the second data bus 112. strobe pulses to the second strobe 112 . (same figure (h)
)). The second memory device 14□ then outputs a response signal to the second glue ply 11□ each time.

When these series of data transfer processes are completed, the DMA device 13 causes the second bus active 1124 to fall (
Figure (d)). The CPU IJ start timing generator 26 detects this and outputs a restart pulse to the lister) 11+s.

In response to this start pulse, the CPU 10 causes the first bus active 1114 to rise and resumes operation.

FIG. 10 shows that the DMA device 13 shown in FIG. 14 is a timing chart when data transfer processing is performed between the first memory device 14 connected to the first memory device 14 and the first memory device 14 connected to the first memory device 14;

This content is almost the same as in Figure 9, but the response signal is
The first memory device 1 outputs to the glue plies 11 and 7.
4. The difference is that

During the operation of the data transfer process shown in FIG. 9, the first bus 11. are not used at all, but during the operation of the data transfer process shown in FIG. 10, the first bus 11. The difference is that both the bus 112 and the second bus 112 are used.

- "Problems to be Solved by the Invention" As described above, the computer system as shown in FIG. 7 having the bus control circuit 12 as shown in FIG. While it was there, the operation was stopped unconditionally.

However, when the DMA device 13 performs data transfer processing between the second memory device 14□ connected to the second bus 11°, the first bus 11 connected directly to the CP[J 10 ．． is not used at all.

This first bus 11. Various devices (not shown) are connected to the CP Ll 10, and it is not preferable to stop the CP Ll 10 during this period from the viewpoint of execution efficiency.

The present invention has been made with attention to the above points, and an object of the present invention is to provide a direct memory access control circuit that improves the execution efficiency of a CPU.

"Means for Solving the Problems" The direct memory access control circuit of the present invention has a first bus that is directly connected to the microprocessor, and a second bus that is indirectly connected to the microprocessor. , a bus control circuit that connects a first bus and a second bus, and this bus control circuit includes:
When a direct memory access device connected to a second bus performs data transfer processing with a first memory device connected to a first bus, the operation of the microprocessor is stopped and direct memory access is performed. When the device performs data transfer processing with a second memory device connected to the second bus, the microprocessor is characterized in that it is allowed to perform the operation using the first bus.

In this bus control circuit, for example, when the direct memory access device makes a direct memory access request to the microprocessor, the bus control circuit temporarily stops the operation of the microprocessor, and the direct memory access device When the address of the memory connected to the second bus is specified at the start of data transfer processing, restart of the operation of the microprocessor is permitted.

"Operation" As described above, the direct memory access control circuit of the present invention allows the second bus indirectly connected to the microprocessor to communicate with the DMA device connected to the second bus. The first bus, which is directly connected to the microprocessor, is used in parallel while being used by the memory device to increase the execution efficiency of the microprocessor.

The bus control circuit separates the first bus and the second bus so that they can be used independently.
This bus control circuit outputs an instruction signal to the microprocessor to stop or permit operation.

When a DMA device makes a DMA request to a microprocessor, the microprocessor normally stops its operation, but when the data transfer process starts, the DMA device sends a DMA request to a second bus connected to a second bus. When the address of the memory device is specified, the bus control circuit detects this and restarts the operation of the microprocessor.

In this way, for example, the computer system can be improved by simply changing the configuration of the conventional bus control circuit.

``Example'' (Outline of bus control circuit and its operation) The direct memory access control circuit of the present invention is a bus control circuit shown in FIG. 8 used in a computer system shown in FIG. The configuration of the circuit 12 is changed as shown in FIG.

In this figure, a first bus 111 and a second bus 11
The structure of □ is the same as that explained in FIG. 8, and the same parts are given the same reference numerals and redundant explanation will be omitted.

Further, each block constituting the bus control circuit 32 is also substantially the same except for connections around the CPU restart timing generator 36, and the same parts are given the same reference numerals and redundant explanations will be omitted. - In the bus control circuit 32 shown in FIG. 1, the CPU restart timing generator is approximately
Perform the following actions.

The conventional generator 26 shown in FIG. 8 captures the falling edge of the second bus active 11□4, generates a list foot pulse at that timing, and sends it to the lister 1119.

In contrast, the CPU IJ start timing generator 36 of the circuit of the present invention receives the second bus active 11□ and the identification signal 27 output from the address decoder 23, as shown in FIG.

Then, from this identification signal 27, the DMA device 1 in FIG.
3 is a first memory device 1 connected to a first bus 11;
4. data transfer processing between the second bus 11 and
In the former case, a restart pulse is output at the falling edge of the second bus active 1124, and in the latter case, a restart pulse is output when the second bus active 1124 falls. , outputs a restart pulse at the rising edge of the second bus active 11□.

FIG. 2 is a timing chart for explaining the operation.

First, the DMA request 10K control 21 connects the second DMA request 112I to the first DMA request 1111, and connects the first DMA request ○ and 1112 to the second DMA request OK 112□. There is.

When the DMA device 13 initiates the second DMA request 1121 (second ffl(a)), in response, cp
uto causes the first DMA request 0K1112 to fall, and at the same time causes the first bus active 11.4 to fall ((C) in the same figure).

In response, the DMA device 13 activates the second bus active 1124 ((e) in the figure), and activates the second address bus 1123, second data bus 1128, and second read/write mode 1125. , the data transfer process is started using the second strobe 11□6 ((f) to (1) in the same figure).
)〉. Then, a reply pulse is sent from the second memory device 142 to which the DMA device 13 performs data transfer processing to the second reply 112 . ((j) in the same figure).

On the other hand, the address decoder 23 outputs an identification signal 27 indicating that the second memory device 142 is to be used at this time (solid line in FIG. 3(d)). This state is called a state in which the second memory space 27 is activated. That is, when the second bus active 1124 rises and the address signal specifying the address of the second memory device 14□ is applied to the second address buses 11, 3, the second memory space 27 rises.

At the timing when the second memory space 27 rises and the second bus active 11□4 rises, a restart pulse 53 is output to the lister) 11+s (see FIG.
K) solid line).

In response to this restart pulse 53, the CPU 10
bus active 111. Start up the DMA device 13
The operation is started using the first bus 11, which is unrelated to the operation (solid line in <C) in the same figure).

Conversely, when the DMA device 13 performs data transfer processing with the first memory device 14°, the second memory space 2
The signal No. 7 does not rise (broken line in (d) of the figure). At this time, a restart pulse 53' (pulse indicated by a broken line in FIG. 2(K)) is output at the time when the second bus active signal 11□ falls.

The CPU receives the start pulse and activates the first bus active 113. (dotted line in the same figure (C)) and restarts the operation.

As described above, in this embodiment, the restart pulse is generated to be sent to the CPU at either the rising edge or the falling edge of the second bus active 1124, thereby restarting the operation. Adjust the timing.

Note that the DMA device 13 shown in FIG. 7 is the first memory device 14. When performing data transfer processing with , in FIG. 1, timing gate control 24 controls first bus active 110 and second bus active 112 . Connect directly. In the opposite case, address bus 1113.1
123 and data buses 1118 and 112, all the transmission lines connected by the timing gate control 24 are disconnected.

Various circuits are conceivable for generating such a start pulse, examples of which will be explained below with reference to FIG.

(Description of CPU Restart Timing Generator) FIG. 3 is a block diagram of the CPU restart timing generator 36 suitable for being provided in the bus control circuit of the direct memory access control circuit of the present invention, and FIG. 4 shows its operation. It is a timing chart for explanation.

As previously explained using FIG. 1, this generator has the second memory space 27 and the second bus active 1124 connected to its input side, and the restart 11+
s is connected to its output side.

First, the second bus active 112. The signal is input manually to both the rising J two detection circuit 41 and the falling detection circuit 42, and the former outputs a rising pulse 51 at the rising timing, and the latter outputs the falling pulse 51 at the falling timing. 52 is output.

FIG. 4(b) shows the second bus active 1124,(C)
A rising pulse 51 and a falling pulse 52 are shown in (d). This rising pulse 51 is applied to the AND circuit 4 of FIG. 3 together with the second memory space 27 (FIG. 3(a)).
3, and the falling pulse 52 is input to the AND circuit 44 together with the inverted signal of the second memory space 27.

The outputs of the two AND circuits 43 and 44 are combined in an OR circuit 45 to form a list foot signal.

Here, when the second memory space 27 is rising, the rising pulse 51 is output as is from the AND circuit 43, but the AND circuit 44 does not allow the falling pulse 52 to pass through. Therefore, the start pulse 53 is generated from this generator 36 as shown by the solid line in FIG. 4(e).
11+s.

In this way, the restart pulse 53 can be output at the timing of the rise of the second bus active 11□.

On the other hand, when the second memory space 27 is not rising (broken line in FIG. 4(a)), the AND circuit 43 does not output the rising pulse 51, and the AND circuit 44 outputs the falling pulse 52. . This is restart 111. As shown by the broken line in Fig. 4(e),
Second bus active 112. A restart pulse 53' is output at the timing of the fall of .

FIG. 5 is a block diagram showing the rise detection circuit 41 and fall detection circuit 42 of FIG. 3 in more detail. Also,
FIG. 6 is a timing chart explaining the operation.

In this figure, the rising edge detection circuit 41 consists of two 7-lip-flops 41. ．． 41. , an AND circuit 413, and a delay line (DL) 414. Further, the falling detection circuit 42 includes an inverter 42.
and an AND circuit 422.

Now, each flip-flop 41 . of the rising edge detection circuit 41 .
．． A clock signal 60 is supplied to 41□ (see FIG.
b)) In synchronization with the timing of this clock signal 60, the signal on the second bus active 1124 is applied to the flip-flop 41. from the flip-flop 412 to the AND circuit 413 ((c), (d), (e)
), (f)).

One terminal of the AND circuit 413 is connected to a flip-flop 41. A signal that is the inverted Q output of is input ((f) in the same figure)
).

A second bus active is directly connected to the other terminal of the AND circuit 413 ((C) in the figure). Both AND outputs are sent to the AND circuit 4 through a delay line 414.
3 by hand ((g) in the same figure).

On the other hand, the fall detection circuit 42 detects the second bus active 1
12. Impark the upper signal 42. is inverted and applied to one terminal of the AND circuit 422, and the Q output of the flip-flop 412 of the rise detection circuit 41 is applied to the other terminal ((e) in the figure). This AND circuit 42
The output of 2 is directly input to the AND circuit 44 (see the same figure).
h)).

Here, the delay line 414 is provided to match the timing since it takes some time for the second bus active 1124 to rise and the second memory space 27 to rise.

In this way, a rising pulse 51 ((g) in the figure) is obtained from the rising detection circuit 41, and a falling pulse 52 ((h) in the same figure) is obtained from the falling detection circuit 42.

Thereafter, as explained in FIG. 3, when the second memory space 27 is on, the second bus active 1
The risk-to-bus 53 (solid line in FIG. 6(i)) is output at the timing when the bus 124 rises, and when the second memory space 27 does not rise, the second bus active 1
12. At the timing when
(Figure 6 (dashed line l) is output.

"Effects of the Invention" The direct memory access method of the present invention described above
The control circuit controls the microprocessor while performing data transfer processing between the DMA device and the second memory device connected to the second bus on the second bus indirectly connected to the microprocessor. Since the microprocessor can perform other processing using the first bus directly connected to the processor, its execution efficiency can be increased.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an embodiment of the bus control circuit installed in the direct memory access control circuit of the present invention, and Figure 2 explains the operation of the direct memory access control circuit of the present invention. 3 is a block diagram showing an embodiment of the main part of the direct memory access control circuit of the present invention, 1. FIG. 4 is a timing chart thereof, and 5.
The figure is a block diagram showing a more detailed embodiment of the main part of the direct memory access control circuit of the present invention, FIG. 6 is a timing chart thereof, and FIG. Block diagram, No. 8
The figure is a block diagram showing an example of a conventional bus control circuit, and FIGS. 9 and 10 are timing charts illustrating its operation. 10...Microprocessor, 11...
...First bus, 112...Second bus, 12...Bus control circuit, 13...
...direct memory access device, 14,...
. . . first memory device, 142 . . . second memory device. Applicant: Fuji Xerox Co., Ltd. Representative
Person Patent Attorney Ume Yamanouchi 1st
Figure 2nd (j) Restart
1119Figure 8■

Claims (1)

[Claims] 1. A first bus that is directly connected to the microprocessor, a second bus that is indirectly connected to the microprocessor, and the first bus and the second bus are connected. This bus control circuit has a bus control circuit.
When the direct memory access device connected to the second bus performs data transfer processing with the first memory device connected to the first bus, the operation of the microprocessor is stopped and the direct memory access device When the memory access device performs data transfer processing with a second memory device connected to the second bus, the microprocessor is allowed to perform the operation using the first bus. Direct memory access control circuit. 2. The bus control circuit allows the direct memory access device to directly access the microprocessor.
The operation of the microprocessor is stopped when a memory access request is made, and the operation of the microprocessor is stopped when the direct memory access device specifies an address of the memory connected to the second bus when starting a data transfer process. 2. The direct memory access control circuit according to claim 1, wherein the direct memory access control circuit allows restart of the direct memory access control circuit.