JP3055395B2 - Signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus requiring high-speed arithmetic processing in digital signal processing such as image processing and radar signal processing.

[0002]

2. Description of the Related Art As a method of processing at a high speed when a large amount of information is transmitted and such information is sent at a certain period, an input signal is divided into units of a certain period, and each divided signal is divided. There has been proposed a signal processing device which sequentially processes a plurality of processors. As such a signal processing device, there is, for example, a device described in “Advanced Parallel Signal Processing (page 164)” issued by Shokodo on August 10, 1992, which will be described below with reference to FIG. In the figure, reference numeral 20 denotes a processor that processes a plurality of divided signals in a pipeline manner, 21a, 21b, 21c, and 21d denote memories that store the divided input signals and processing results of the processor 20, and 22 denotes a processor 20 and a memory 21a. , 21b, 2
A high-speed bus for transferring input signals or processing results between 1c and 21d; 23, a host CPU for controlling the entire apparatus;
Reference numeral 24 denotes the processor 20 and the memory 2
It is a control bus for controlling 1a, 21b, 21c, 21d. Reference numeral 25 denotes the processor 20 and the control bus 24.
26a, 26b, 26c are RAMs for storing instructions and processing programs from the host CPU 23 to the processor 20, 27 is a data storage device for storing input signals, and 28 is an input stored in the data storage device 27. A bus for transferring signals to the memory 21;
29a, 29b, 29c and 29d are processor boards composed of the processor 20, the interface 25 and the RAMs 26a, 26b and 26c.

Next, the operation will be described. (1) The host CPU 23 controls the RAM 2 of the processor boards 29a, 29b, 29c, 29d via the control bus 24.
The processing program is loaded into 6a, 26b, 26c, and then the signal data stored in the data storage device 27 is transferred to the memory 21a via the data transfer bus 28 and the high-speed bus 22. (2) When the data transfer to the memory 21a is completed, the host CPU 23
A command to start processing is sent to 0. Then, the processor 20 starts processing the data stored in the memory 21a, while the host CPU 23 transfers the next signal data from the data storage device 27 to the memory 21b via the data transfer bus 28 and the high-speed bus 22. . (3) When the data transfer to the memory 21b is completed, the host CPU 23
A command to start processing is sent to 0. The processor 20 is a memory 2
1b, the host CPU 23 transfers the next signal data from the data storage device 27 to the memory 21c via the data transfer bus 28 and the high-speed bus 22. (4) When the data transfer to the memory 21c is completed, the host CPU 23
A command to start processing is sent to 0. The processor 20 is a memory 2
The host CPU 23 starts processing the data stored in 1c, while the host CPU 23 transfers the next signal data from the data storage device 27 to the memory 21d via the data transfer bus 28 and the high-speed bus 22. (5) When the data transfer to the memory 21d is completed, the host CPU 23 sets the processor 2 on the processor board 29d.
A command to start processing is sent to 0. The processor 20 is a memory 2
Processing is started for the data stored in 1d. (6) Each processor board 29a, 29b, 29c, 2
When the processing of the processor 20 mounted on the 9d is completed, the processing result is transferred to the memory 21 via the high-speed bus 22.
a, 21b, 21c, 21d, and then to the data storage device 27 via the data transfer bus 28. In the first stage, the above (1) to (6) are executed, and thereafter, the above (2) to (6) are repeatedly executed, thereby shifting the processing time of each processor and time-sharing a single high-speed bus. The process was progressed in a pipeline while using it, thereby speeding up the process.

[0004]

The conventional signal processing device is configured as described above, and the processing of the processor 20 mounted on each of the processor boards 29a, 29b, 29c, 29d takes a certain period of time. Was operating on the premise that the processing would end. Therefore, if the amount of data increases during the series of processing or the load of the processor 20 increases rapidly due to the increase in the complexity of the data, the processor cannot finish the processing within a predetermined processing time, and However, there is a problem that in a system that requires high performance, consistency of processing cannot be maintained. In addition, since four processors always process one input signal in a time-division manner in a pipeline manner, there is a problem that it is not possible to flexibly cope with a change in processing of an input signal. Further, the processor 20 stores the input signal in the memory at the start of the processing, and writes the processing result to the memory again after the processing is completed. Therefore, a waiting state of the processor occurs during the memory input / output period, and thus the processor is enabled. There was a problem that it could not be used. In radar signal processing and image processing, two-dimensional matrix operations such as FFT (fast Fourier transform) and inverse FFT are mainly performed. In this case, the processing program develops the input signal data on the memory as a two-dimensional array, and accesses the two-dimensional array data on a row basis on the memory. For this reason, there is a problem in that when the access operation is continuously performed in the column direction of the two-dimensional array, the processing time is significantly increased as compared with the case where the access is performed in the row direction. The processor 20 of the processor board 29a finishes the processing and starts the processing again for the next input signal because of the other processor boards 29b, 29c, and 29d.
After all of the processing in the processor 20 mounted on the device has been completed and the processing result has been transferred to the data storage device 27,
During this period, there is a problem that the processor 20 of the processor board 29a cannot start the next process. Furthermore, since there is only one high-speed bus 22 for transferring an input signal from the data storage device 27 to each of the memories 21a, 21b, 21c, 21d, a plurality of input signal data cannot be processed at the same time. However, there is a problem that the processing that extends over the two signal data cannot be performed. In addition, the processor boards 29a, 2
When 9b, 29c, and 29d fail, the failed processor board cannot be switched to the standby processing board, and the processing cannot be continued.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and it is possible to perform high-speed processing of signal data sent from outside via a plurality of input signal lines in parallel and continuously. It was done. It is another object of the present invention to provide a system that can be operated continuously without reducing the amount of processing data even when a failure occurs in a processing device.

[0006]

According to a first aspect of the present invention, there is provided a signal processing apparatus comprising: a plurality of operation modules for performing data processing; and a plurality of operation modules for dividing an input signal sent from the outside at a predetermined period. An arithmetic module selector for sequentially assigning the arithmetic module selector, an input bus for connecting the arithmetic module selector to a plurality of arithmetic modules, and an input bus to the arithmetic module, provided independently of the arithmetic module, and in parallel with the data input operation via the input bus. And an operation module output bus for outputting the operation result of
The arithmetic module is connected to a local memory, a plurality of processors configured for the local memory and processing data in the local memory in parallel, and connected to an input bus and an arithmetic module output bus to acquire data or to obtain an arithmetic result. An internal bus that is used in common when transferring data to an arithmetic module output bus, and a data connection operation via the input bus connected to the internal bus and an access process from the processor can be performed in parallel for each memory device. And a two-dimensional memory device as described above.

[0007] The signal processing device according to the second invention comprises a first processing device.
In the signal processing device according to the present invention, the two-dimensional memory device can be accessed by the processor in any of the row direction and the column direction.

[0008] A signal processing apparatus according to a third aspect of the present invention comprises:
In the signal processing apparatus according to the invention or the second invention, a local computer connected to an arithmetic module output bus, and an arithmetic module for controlling an arithmetic module selector based on a command sent from the local computer to process an input signal And an arithmetic module selector control unit for variably controlling the number of the arithmetic modules.

[0009] A signal processing apparatus according to a fourth aspect of the present invention comprises:
In the signal processing device according to the third to third inventions,
A plurality of input signals to the arithmetic module selector, a plurality of input buses to each arithmetic module and a plurality of output buses from each arithmetic module are provided, and a local computer is connected to the arithmetic module output bus,
One of the local computers is defined as a master local computer, and the arithmetic module selector control section distributes an input signal to each arithmetic module corresponding to each input signal system based on a command sent from the computer. .

The signal processing device according to a fifth aspect of the present invention provides a signal processing device according to the fourth aspect.
In the signal processing apparatus according to the invention, an arbitrary number of the plurality of arithmetic modules is used as a standby arithmetic module, the operation status of the arithmetic modules is monitored, and information regarding the operating status of each arithmetic module is transmitted to the master local computer. The master local computer instructs the arithmetic module selector control unit to incorporate the standby system arithmetic module when detecting a failure in the operating arithmetic module based on the information sent from the arithmetic module inspection unit. Is issued.

The signal processing device according to a sixth aspect of the present invention provides a signal processing device according to the fourth aspect.
In the signal processing device according to the invention, an arbitrary number of the plurality of operation modules is used as a standby operation module, the operation state of the operation module is monitored, and information regarding the operation state of each operation module is sent to the master local computer. The master local computer is provided with an inspection unit, detects a failure in the operating operation module based on the information sent from the operation module inspection unit, and operates the master local computer when the standby operation module is already installed and operating. An instruction is issued to the module selector control unit regarding the number of operation modules for processing input signals and a combination change.

A signal processing device according to a seventh aspect of the present invention is the
In the signal processing apparatus according to the invention or the sixth invention, a plurality of signal processing modules each including a plurality of arithmetic modules configured as one signal processing module, an output bus connecting the plurality of signal processing modules, and a signal processing module And a host computer connected to the output bus.

The signal processing device according to an eighth aspect of the present invention is the signal processing device according to the seventh aspect.
In the signal processing device according to the present invention, a signal processing module selector for distributing a plurality of input signals sent from outside to a plurality of signal processing modules is provided, and the host computer is transmitted from a master local computer in each signal processing module. This is to control the signal processing module selector based on the coming information.

According to a ninth aspect of the present invention, there is provided a signal processing apparatus comprising:
In the signal processing device according to the present invention, an arbitrary number of the plurality of signal processing modules is used as a standby signal processing module, and when a malfunction occurs in the active signal processing module, the host computer sends the standby signal to the signal processing module selector. A command is issued to incorporate the processing module.

A signal processing device according to a tenth aspect of the present invention is the signal processing device according to the eighth aspect, wherein an arbitrary number of the plurality of signal processing modules is used as a standby signal processing module, and the active signal processing module is defective. Occurs, and when all the standby signal processing modules are already installed and operating, the host computer changes the signal processing module selector so that the combination of the input signal and the signal processing module for processing the input signal is changed. This is to issue a command.

[0016]

The signal processing apparatus according to the present invention divides an input signal at a fixed period and distributes the input signal to the operation modules in order, and the processor in the operation module processes the data stored in the local memory in parallel. The signal data transmitted via the input bus during the processing by the processor is stored in the other two-dimensional memory not accessed by the processor. The data stored in the two-dimensional memory can be accessed by the processor from either the row direction or the column direction. Further, the local computer performs an operation on the processing results of the plurality of processors. In addition, the number of arithmetic modules is variably controlled in accordance with an increase or decrease in the processing amount for the input signal.

Further, the operation modules are divided into groups corresponding to the input signal system, and a series of processing including signal input, operation processing, and operation result output processing is performed independently and in parallel for each input signal. Also, the master local computer variably controls the number of arithmetic modules that process the signal system according to the increase or decrease in the processing amount of the signal system.

If the operation module fails, a spare operation module is incorporated. Further, when all the standby operation modules are already operating, the operating operation module is assigned in place of the failed operation module.

Further, a plurality of arithmetic modules are configured as one signal processing module, input signals are processed in parallel for each signal module, and the host computer further performs processing on these processing results as necessary.

Further, the combination of the input signal and the signal processing module for processing the input signal is determined according to the processing amount of the input signal or the load condition of the signal processing module.

Further, when the signal processing module breaks down, a standby signal processing module is incorporated.
Furthermore, when a plurality of signal processing modules fail and there are no standby signal processing modules, the host computer changes the combination of the input signal processing amount and the signal processing module for processing the input signal processing amount and continues the processing. I do.

[0022]

【Example】

Embodiment 1 FIG. Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. In FIG. 1, reference numerals 1a and 1b denote two-dimensional memories, 2a, 2b, and 2 which store one of input signals divided in a certain period unit in a two-dimensional array image.
c and 2d are local memories for storing the input signals stored in the two-dimensional memories 1a and 1b in row or column units.
3a, 3b, 3c, 3d are local memories 2a, 2b,
A processor that processes data stored in 2c and 2d in parallel, 4 is a shared bus connecting the two-dimensional memories 1a and 1b and processors 3a, 3b, 3c and 3d, 5 is an input bus 8 and an arithmetic module This is an internal bus connecting the output bus 10 and the two-dimensional memories 1a and 1b. Also,
6a, 6b, 6c and 6d are two-dimensional memories 1a and 1b, local memories 2a, 2b, 2c and 2d and a processor 3
a, 3b, 3c, 3d, a shared bus 4 and an internal bus 5, an arithmetic module 7 divides a plurality of input signals sent from the outside at a certain period, and divides the plurality of divided input signals into one. One or more arithmetic modules 6a, 6
an operation module selector for sequentially assigning the operation modules b, 6c and 6d; an input bus 8 for connecting the operation module selector 7 to the internal bus 5 in the operation modules 6a, 6b, 6c and 6d; , 6d, the processor 3a, 3b, 3c, 3d performs processing on the processing results, and furthermore, the arithmetic module selector controller 1
1 is a value indicating the amount of processing and the processing amount of the input signal in units of the period.
Since the larger the value is, the larger the processing amount and the longer the processing time, the processing is allocated to a large number of arithmetic modules to distribute the load. Conversely, the smaller this value is, the smaller the processing amount is.
Processing is performed by a small number of operation modules. ) To send to the local host computer. Reference numeral 10 denotes a local host computer 9 and operation modules 6a, 6b, 6
An operation module output bus 11 for connecting the internal buses 5 in c and 6d, and controls the operation module selector 7 using information on the cycles and processing amounts of a plurality of input signals sent from the local host computer 9. The operation module selector controller 12 is an input signal sent from the outside. FIG. 2 shows an arithmetic module selector controller 1
1 is a configuration diagram of a distribution table used to determine an input destination of an input signal 12 in a cycle unit. In the figure,
Reference numeral 13 denotes a distribution table, and each entry corresponds to each of the operation modules 6a, 6b, 6c, and 6d in order from the top.

Next, the operation will be described with reference to the time chart of FIG. First, the arithmetic module selector control unit 11 controls the arithmetic module selector 7 using the period and the processing amount of the input signal 12 which is information sent from the local host computer 9 and designates the input signal 12 sent from the outside. The input signal is divided by a period, and the input signal in units of a period is divided into one or a plurality of operation modules 6a, 6b, 6c, 6
The input data is sequentially and repeatedly input to the two-dimensional memories 1a and 1b in the internal memory 5 via the input bus 8 and the internal bus 5 of each of the operation modules 6a, 6b, 6c and 6d. In this distribution process, for example, the distribution table 13 shown in FIG. 2 is prepared in the arithmetic module control unit 11 in advance, and the same number of entries as the processing amount sent from the local host computer 9 are obtained in order from the upper entry of the distribution table 13. Input signals are sequentially input to the devices (arithmetic modules, two-dimensional memories) entered in those entries in units of a cycle.

For example, if the processing amount sent from the local host computer 9 is 1, the input signal in units of a cycle is the two-dimensional memory 1a of the operation module 6a specified by the first entry and the two-dimensional memory of the operation module 6a. 1
b is input alternately. On the other hand, when the processing amount is 4, as shown in the input flowchart of FIG.
After the input signal is sequentially input to the two-dimensional memory 1a of the arithmetic module d in the cycle unit, the two-dimensional memory is switched. This time, the input signals are sequentially input to the two-dimensional memory 1b of the arithmetic modules 6a to 6d in the periodic unit. Is input to

FIG. 3 corresponds to the case where the processing amount is 4, and the period from the period 1 to the period 4
Is sequentially input to the two-dimensional memory 1a of the operation modules 6a, 6b, 6c, 6d via the input bus 8 (30a, 30b, 30c, 30).
d), and then the data (30
e) is performed in the same manner as the arithmetic modules 6a, 6b, 6c, 6
This shows how the data is input to the two-dimensional memory 1b of FIG. In this way, in the arithmetic module which has finished storing the input signal for one cycle in the two-dimensional memory 1a or 1b, the processors 3a, 3b
b, 3c, 3d respectively connected to local memories 2a,
Data transfer to rows 2b, 2c, and 2d is performed in units of rows or columns, and processing is started.

FIGS. 5 and 6 show the processors 3a, 3b,
This shows a method of accessing the two-dimensional memories 1a and 1b of 3c and 3d. FIG. 5 shows that after the input signal 12 is stored in the two-dimensional memories 1a and 1b as a two-dimensional array, the data on the two-dimensional
It shows a state where data is stored in a, 2b, 2c, and 2d.
The processors 3a, 3b, 3c, 3d can access the data on the local memory stored in units of rows in this way. On the other hand, FIG. 6 shows a state in which the input signal 12 is stored in the two-dimensional memories 1a and 1b as a two-dimensional array, and then cut out in units of columns and stored in the local memories 2a, 2b, 2c and 2d. I have. The processors 3a, 3b, 3c, 3d can access data on the local memory stored in column units.

In this way, the processors 3a, 3b, 3
c, 3d are local memories 2a, 2b, 2c, connected to each processor from a two-dimensional memory in accordance with the processing contents.
Data transfer in the row direction or the column direction is performed to 2d, and when the transfer processing is completed, the processors 3a, 3b, 3
c and 3d start processing in parallel with the data stored in the local memories 2a, 2b, 2c and 2d, respectively. After the processing, the processing results of the processors 3a, 3b, 3c, and 3d are stored in the two-dimensional memory 1a or 1b. Similarly, when the processing by all the rows or columns of the two-dimensional memory is completed by the arithmetic module, Local computer 9
Extracts the processing results of each arithmetic module from the two-dimensional memory 1a or 1b via the arithmetic module output bus 10 and the internal bus 5 as shown in FIG. 3 as 31a, 31b, 31c, and 31d, and further, if necessary. Performs arithmetic processing across arithmetic module data. On the input bus 8, the input signal 30e of the period 5 to be processed next by the arithmetic module 6a is transmitted to the processor 3 of the arithmetic module 6a.
a, 3b, 3c, and 3d are performing parallel processing on the two-dimensional memory 1a while the other two-dimensional memory 1b is not being accessed in parallel by the processors 3a, 3b, 3c, and 3d. Is input to

According to the present embodiment, a local memory is provided for a processor, and a two-dimensional memory for storing input signals and processing results of the processor has a double buffer structure.
Since the data in the two-dimensional memory is appropriately transferred to the local memory for calculation, a plurality of processors can proceed in parallel, and the calculation processing speed can be improved. Further, since the two-dimensional memory can be accessed by the processor in the arithmetic module from either the row direction or the column direction according to the content of the processing, the memory access time can be reduced. Furthermore, the input bus and the output bus of the operation module are independent, so that the input signal to the operation module and the output signal from the operation module can be prevented from colliding on the bus, enabling continuous data processing. Becomes In addition, since the local computer is connected to the output bus of each arithmetic module, the output result of the arithmetic module can be further processed across data.

Embodiment 2 FIG. A second embodiment of the present invention will be described with reference to FIGS. The configuration of this embodiment is
Since the configuration is the same as that of FIG. 1 showing the configuration of the first embodiment, the description is omitted.

Next, the operation of this embodiment will be described with reference to the time chart of FIG. FIG. 7 corresponds to the case where the processing amount is 4, the signal data of cycle 1 on the input bus 8 is stored in the two-dimensional memory 1a of the arithmetic module 6a, and is processed in parallel by the processors 3a, 3b, 3c and 3d. Is done.
Similarly, signal data corresponding to periods 2, 3, and 4 on the input bus 8 are similarly processed by the operation modules 6b, 6c, and 6 respectively.
d and stored in the two-dimensional memory 1a. Next, with respect to the data of period 5, which has been period-divided by the operation module selector 7 and taken into the input bus 8, the processing for the data of period 1 previously stored in the two-dimensional memory 1a of the operation module 6a has already been completed. Irrespective of whether or not it is stored in the two-dimensional memory 1b of the operation module 6a.
In the example of FIG. 7, at the timing of the cycle 5, although the processing for the data of the cycle 1 has not yet been completed,
Is stored in the two-dimensional memory 1b in parallel with this. Accordingly, each processor of the operation module 6a can immediately start processing on the data in cycle 5 without having to wait for processing for transferring data to the two-dimensional memory 1b after processing on the data in cycle 1 is completed. The same applies to the other operation modules 6b, 6c, 6d.

According to this embodiment, two two-dimensional memories are prepared for each operation module for storing input signal data, and can be accessed independently from the processor side and the operation module selector side. Even if the next input signal is sent during the processor processing in the arithmetic module, this can be stored in the other two-dimensional memory, so that the processor processing and data input / output can be performed in parallel, The processor can perform continuous processing without causing a wait state during the input / output period of the two-dimensional memory.

Embodiment 3 FIG. A third embodiment of the present invention will be described with reference to FIGS. 1, 8, and 9. FIG. Since the configuration of the present embodiment is the same as FIG. 1 showing the configuration of the first embodiment,
Description is omitted. The operation of the present embodiment will be described below separately for (A) a case where the processing amount decreases during the processing of the arithmetic module and (B) a case where the processing amount increases.

(A) The operation when the processing amount decreases during the processing of the arithmetic module will be described with reference to the time chart of FIG. According to the operation described in the first embodiment, the signal data corresponding to the cycle 1, the cycle 2 and the cycle 3 on the input bus 8 are input to the two-dimensional memories 1a of the operation modules 6a, 6b and 6c, respectively. I have. Next, immediately after the signal data of period 4 is input to the two-dimensional memory 1a of the operation module 6d, the operation module selector control unit 11 changes the processing amount from 4 to 2 by the local host computer 9 from the local host computer 9. Suppose you have received Then, the operation module selector control unit 11 refers to the distribution table 13 and the newly obtained processing amount is 2, so that in the subsequent processing, the operation modules 6a and 6b described in the upper two entries of the distribution table 13 Only valid. In this way, the arithmetic module selector control unit 11 controls the arithmetic module selector 7 to input a signal of period 5 to the two-dimensional memory 1b of the arithmetic module 6a written in the upper two entries, A signal having a period of 6 is input to the two-dimensional memory 1b. Further, the two-dimensional memory is switched from 1b to 1a for the signals having the periods 7 and 8, and the two-dimensional memories 1a, 1a of the operation module 6a are respectively switched.
And input to the two-dimensional memory 1a of the operation module 6b. The input signal 12 captured in each operation module in this manner is thereafter processed in the same manner as in the first embodiment in each cycle unit.

(B) A case where the processing amount increases during the processing of the arithmetic module. A case where the processing amount increases during the processing of the arithmetic module will be described with reference to FIGS. 1 and 9. At present, since the processing amount is 2, the arithmetic modules 6a and 6b are in the state of processing the input signal 12. Here, after the signal of the cycle 7 on the input bus 8 is input to the two-dimensional memory 1a of the arithmetic module 6a, the arithmetic module selector control unit 11 issues a command from the local host computer 9 to change the processing amount from 2 to 4. Suppose you have received it. Then, the operation module selector control unit 11 refers to the distribution table 13 and determines that the operation module described in the upper four entries of the distribution table 13 is valid in the subsequent processing because the newly obtained processing amount is 4. I do. Then, the arithmetic module selector 7 is controlled to input the signal of the period 8 to the two-dimensional memory 1a of the arithmetic module 6b. Next, since the processing amount becomes 4 and the upper 4 entries are valid, a signal of period 9 is input to the two-dimensional memory 1a of the operation module 6c, and a signal of period 10 is input to the two-dimensional memory 1a of the operation module 6d. . Then, for signals after period 11, the two-dimensional memory is switched from 1a to 1b,
The signal of period 11 is stored in the two-dimensional memory 1 of the arithmetic module 6a.
b. The input signal 12 captured in each arithmetic module in this manner is hereinafter referred to as the first embodiment in each cycle unit.
Is processed in the same manner as

According to the present embodiment, the input signals are appropriately distributed to other arithmetic modules according to the increase or decrease of the input signal amount, so that the load can be adjusted and equalized between the processors. In addition, the number of arithmetic modules is appropriately increased even during the processing so that the load is not concentrated on a specific processor, and the input signals are distributed.
Even in the case of a sudden increase in the processing amount, the processing can be completed within the time requested initially, and the consistency as a system can be maintained.

Embodiment 4 FIG. A fourth embodiment of the present invention will be described with reference to FIGS. FIG. 10 shows the configuration of the present embodiment, in which two input signals are input to the arithmetic module selector with respect to FIG.
The input bus and the operation module output bus are also added one by one to two, and a local computer is connected to each operation module output bus. In the figure, 8a and 8b are operation module selectors 7 and buses 5 in operation modules 6a, 6b, 6c and 6d.
, And 9b are operation modules 6a, 6b.
Processors 3a, 3b, 3c, 3d in b, 6c, 6d
9a is a master local computer for sending the cycle and processing amount of the two input signals 12a and 12b to the arithmetic module selector control unit 11 in addition to the processing for the arithmetic result of the processor. is there. 10a and 10b are local computers 9a and 9b and operation modules 6a and 6b,
Arithmetic module output buses connecting the internal buses 5 in 6c and 6d, and 12a and 12b are input signals sent from outside. Other components are the same as those shown in FIG.

Next, the operation of this embodiment will be described with reference to the time chart shown in FIG. The arithmetic module selector control unit 11 controls the arithmetic module selector 7 in a cycle corresponding to the input signal 12a sent from the master local computer 9a, and divides the input signal 12a into cycles. In this embodiment, since the processing amount for the input signal 12a sent from the master local computer is 2, the operation module described in the upper two entries of the distribution table 13 becomes effective. Therefore, the signal of the cycle 1 of the input signal 12a is stored in the two-dimensional memory 1 of the arithmetic module 6a.
a, and a signal of period 2 is input to the two-dimensional memory 1a of the operation module 6b. Further, the signal of period 3 is input to the two-dimensional memory 1b of the operation module 6a, and the signal of period 4 is input to the two-dimensional memory 1b of the operation module 6b. The input signal 12a input to the operation modules 6a and 6b in this manner is processed in each cycle unit as in the first embodiment. On the other hand, similarly, the input signal 12b is divided at a period corresponding to the input signal 12b sent from the master local computer 9a. In this embodiment, since the processing amount for the input signal 12b sent from the master local computer is 2, the input signal 1
The operation module described in the next two entries after the upper two entries of the distribution table 13 used in 2a becomes effective. Therefore, the signal of cycle 1 of the input signal 12b is input to the two-dimensional memory 1a of the arithmetic module 6c,
Is input to the two-dimensional memory 1a of the operation module 6d. Further, the signal of period 3 is transmitted to
The signal is input to the two-dimensional memory 1b of the arithmetic module 6d. In this manner, the input signal 12 input to the arithmetic modules 6c and 6d
b is processed in each cycle unit as in the first embodiment.

According to this embodiment, two input signals sent from the outside are sequentially allocated to the respective operation modules in the two operation module groups via different input buses for each input signal, and Can be taken out by the local computer via a different operation module output bus for each input signal, so that a series of processing from signal input, operation processing, and result output can be performed in parallel with respect to two signal systems. , And continuously.

Embodiment 5 FIG. A fifth embodiment of the present invention will be described with reference to FIGS. The configuration of the present embodiment is the same as that of the fourth embodiment shown in FIG.

Next, the operation of this embodiment will be described with reference to the time chart of FIG. As described in the fourth embodiment,
The operation modules 6a and 6b are processing the input signal 12a, and the operation modules 6c and 6d are processing the input signal 12b. Now, the arithmetic module selector 7 inputs the signal of the cycle 4 of the input signal 12a to the two-dimensional memory 1b of the arithmetic module 6b, and converts the signal of the cycle 4 of the input signal 12b into the two-dimensional memory 1b of the arithmetic module 6d.
After the input, the arithmetic module selector controller 11 receives information from the master local computer 9a that changes the processing amount for the input signal 12a from 2 to 1 and the processing amount for the input signal 12b from 2 to 3. . Then, the arithmetic module selector control unit 11
Controls the operation module selector 7 and the processing amount of the input signal 12a sent from the master local computer becomes 1. Therefore, the two-dimensional memories 1a and 1b of the operation module 6a written in the upper one entry of the distribution table 13 Then, the input signals 12a after the period 5 are alternately input in units of a period. The input signal 12a input to the arithmetic module 6a in this way is processed in each cycle unit as in the first embodiment. On the other hand, since the processing amount for the input signal 12b is 3, the operation modules 6b, 6c, and 6d specified by the next three entries after the upper one entry of the sorting table 13 used for the input signal 12a previously process the input signal 12b. Is effective. Therefore, the input signal 12b
Is stored in the two-dimensional memory 1 of the arithmetic module 6b.
a, and the signal of period 6 is
The signal of period 7 is input to the two-dimensional memory 1a of the arithmetic module 6d. Next, the two-dimensional memory is switched from 1a to 1b, and the signal of period 8 is input to the two-dimensional memory 1b of the operation module 6b. In this way, the input signal 12b input to the operation modules 6b, 6c, 6d is processed in each cycle unit as in the first embodiment.

According to this embodiment, two input signals sent from the outside are sequentially allocated to the respective operation modules in the two operation module groups via different input buses for each input signal, and The local computer 9a, 9b can take out the processing result of (1) through an operation module output bus different for each input signal, and even if the processing amount of one input signal increases during the processing, the other Since the load can be distributed to the arithmetic modules that are processing the input signal of the above, the processing can be performed consistently without being affected by a sudden increase or decrease in the load. Further, the processing can be performed without affecting the influence of the increase in the load of the operation module on one input signal to the operation module group processing the other input signal.

Embodiment 6 FIG. A sixth embodiment of the present invention will be described with reference to FIGS. 13, 14, 15, and 16. FIG. 13 shows the configuration of the present embodiment, in which a standby system operation module that normally stands by as a standby and performs processing when another operation module has failed, and all operation modules including the standby system operation module, An operation module check unit for checking whether the operation is normal or not and sending operation information of the operation module to the master local computer is provided. In the figure, reference numeral 6e denotes a standby operation module which normally stands by as a standby and performs processing when another operation module fails, and 14 checks whether all the operation modules including the standby operation module are operating normally. An operation module inspection unit that sends operation information of the operation module to the master local computer 9a.
The other parts are the same as those of the fifth embodiment, and the description is omitted.

FIG. 14 is a configuration diagram of a distribution table for the arithmetic module selector control section 11 to determine the input destinations of the input signals 12a and 12b divided on a cycle-by-period basis. FIG. FIG. 14B shows a case where there is no operation module, and FIG. 14B shows a case where a failure operation module exists in the system. In the figure, reference numeral 15 denotes a distribution table, and each entry is composed of operation modules 6a, 6b, 6c, 6d,
And the standby system operation module 6e.
Denotes an operation display unit indicating the operation status of each arithmetic module;
Reference numeral b denotes a distribution data input device display unit indicating a two-dimensional memory provided in each operation module.

First, using the time chart of FIG.
The operation in the case where there is no fault operation module in the system will be described. The master local computer 9a sends the operation modules 6a, 6b, 6c, 6d and the standby system operation module 6e from the operation module checking unit 14.
Receives the operation information indicating that all of them are operating normally, and writes “0” into the operation display sections 15 a of all entries of the distribution table 15 in the arithmetic module selector control section 11. The arithmetic module selector control section 11 controls the arithmetic module selector 7 to divide the input signal 12a at a period corresponding to the input signal 12a sent from the master local computer 9a. In this example, since the processing amount of the input signal 12a sent from the master local computer 9a is 2, two entries whose operation display section 15a from the upper entry of the distribution table 15 is "0" are valid. Therefore, the signal of period 1 of the input signal 12a is input to the two-dimensional memory 1a of the operation module 6a, and the signal of period 2 is input to the two-dimensional memory 1a of the operation module 6b.
The signal of period 3 is stored in the two-dimensional memory 1b of the operation module 6a.
And the signal of period 4 is input to the two-dimensional memory 1b of the operation module 6b. In this way, the input signal 12a input to the arithmetic module is processed in each cycle in the same manner as in the first embodiment. On the other hand, the input signal 12b is the input signal 1 sent from the master local computer 9a.
2b. In this example, input signal 1
Since the processing amount for 2b is 2, the input signal 12b
The operation modules 6c and 6d corresponding to the two entries of which the operation display section 15a is "0" become effective after the upper two entries of the distribution table 15 used in "a". Accordingly, the signal of cycle 1 of the input signal 12b is input to the two-dimensional memory 1a of the operation module 6c, the signal of cycle 2 is input to the two-dimensional memory 1a of the operation module 6d, and the signal of cycle 3 is input to the two-dimensional memory of the operation module 6c. The signal of cycle 4 is input to the two-dimensional memory 1b of the arithmetic module 6d. The input signal 12b input to the arithmetic module in this way is processed in each cycle unit in the same manner as in the first embodiment.

Next, the operation when a failure occurs in an arithmetic module in the system will be described with reference to the time chart of FIG. Now, the operation modules 6a and 6b process the input signal 12a, and the operation modules 6c and 6b
d is processing the input signal 12b.
The arithmetic module selector 7 inputs the signal of the cycle 4 of the input signal 12a to the two-dimensional memory 1b of the arithmetic module 6b, and outputs the signal of the cycle 4 of the input signal 12b to the arithmetic module 6
It is assumed that the master local computer 9a obtains information from the operation module checking unit 14 that the operation module 6d has failed after the input to the two-dimensional memory 1b. Then, "1" is displayed in the operation display section 15a of the entry corresponding to the operation module 6d of the distribution table 15.
Write. FIG. 14B shows the state of the distribution table 15 when the operation module 6d is out of order. The operation module selector control unit 11 controls the operation module selector 7 and processes the input signal 12a sent from the master local computer 9a by two.
5a makes two entries “0” valid, and the input signal 12a
Is stored in the two-dimensional memory 1 of the arithmetic module 6a.
a, a signal of period 6 is input to the two-dimensional memory 1a of the operation module 6b, a signal of period 7 is input to the two-dimensional memory 1b of the operation module 6a, and a signal of period 8 is input to the two-dimensional memory of the operation module 6b. Input to the memory 1b. The input signal 12a input to the arithmetic module in this manner is processed in each cycle unit as in the first embodiment. On the other hand, the input signal 12b is divided by the cycle of the input signal 12b sent from the master local computer 9a.
In this example, since the processing amount for the input signal 12b is 2, the sorting table 1 previously used for the input signal 12a is used.
After the upper two entries of the operation modules 5, the operation display sections 15 a indicate that the operation modules 6 c and 6 correspond to the two entries “0”.
e becomes effective. Therefore, the signal of the period 5 of the input signal 12b is input to the two-dimensional memory 1a of the operation module 6c,
The signal of period 6 is input to the two-dimensional memory 1a of the standby operation module 6e, the signal of period 7 is input to the two-dimensional memory 1b of the operation module 6c, and the signal of period 8 is input to the two-dimensional memory of the standby operation module 6e. 1b. That is,
The divided signal of the input signal 12b is input to the standby operation module 6e which has been in the standby state until now, and the input signal 12b is processed by the operation module 6c and the standby operation module 6e. In this way, the input signal 12b input to the arithmetic module is processed in each cycle unit as in the first embodiment.

According to the present embodiment, the standby operation module is put on standby, and even if one operation module fails, the standby operation module is made to take over the processing of the failed operation module. Without,
Simultaneous continuous processing of two input signals can be continued without reducing the processing amount of the input signals.

Embodiment 7 FIG. A seventh embodiment of the present invention will be described with reference to FIG. The configuration of this embodiment is the same as that of FIG. 13 showing the configuration of the sixth embodiment, and a description thereof will be omitted.

Next, the operation of this embodiment will be described with reference to the time chart of FIG. As described in the sixth embodiment, it is assumed that the standby operation module 6e is performing processing in place of the failed operation module 6d. Here, the operation module selector 7 sets the input signal 12
After inputting the signal of period 7 on a to the two-dimensional memory 1b of the operation module 6a and inputting the signal of period 7 on the input signal 12b to the two-dimensional memory 1b of the operation module 6c,
It is assumed that the master local computer 9a has obtained information from the operation module checking unit 14 that the operation module 6c has failed. Then, the master local computer 9a operates the operation module 6 in the distribution table 15.
At the same time as writing "1" to the operation display section 15a of the entry corresponding to c, information indicating that the processing amount of the input signal 12b is changed from 2 to 1 is sent to the arithmetic module selector control section 11. The arithmetic module selector control unit 11 controls the arithmetic module selector 7 so that the processing amount of the input signal 12a sent from the master local computer 9a is 2
Therefore, the operation display unit 15a validates two entries of “0” from the upper level of the distribution table 15. Therefore,
The signal of period 8 of the input signal 12a is input to the two-dimensional memory 1b of the operation module 6b, the signal of period 9 is input to the two-dimensional memory 1a of the operation module 6a, and the signal of period 10 is input to the two-dimensional memory of the operation module 6b. 1a, and a signal having a period of 11 is input to the two-dimensional memory 1b of the arithmetic module 6a.
To enter. The input signal 12a input to the arithmetic module in this manner is processed in each cycle unit as in the first embodiment. On the other hand, since the processing amount for the input signal 12b sent from the master local computer 9a is 1, the operation display section 15a sets the value of "0" to "1" after the upper two entries of the sorting table 15 previously used for the input signal 12a. Input signals are alternately input to the two-dimensional memories 1a and 1b of the standby operation module 6e written in the entry. The signal 12b input to the standby operation module in this manner is processed in each cycle unit in the same manner as in the first embodiment.

In this embodiment, the processing of the input signal 12b is performed only by the standby processing module 6e for the failure of the processing module 6c, but the processing amount of the input signal 12a from the master local computer 9a is reduced from 2 to 1. Information to be changed to the operation module selector control unit 11
, The processing of the input signal 12a can be performed only by the operation module 6a, and the processing of the input signal 12b can be performed by the two modules of the operation module 6b and the standby operation module 6e.

According to the present embodiment, the standby operation module is made to stand by, and even if two operation modules fail, the standby operation module is incorporated as an active operation module. By adjusting the processing amount of the input signal of the signal system including, continuous processing can be maintained without stopping the apparatus.

Embodiment 8 FIG. An eighth embodiment of the present invention will be described with reference to FIG. The configuration of the present embodiment is the same as that of FIG. 13 showing the configuration of the seventh embodiment, and a description thereof will be omitted.

Next, the operation of this embodiment will be described with reference to the time chart of FIG. As described in the seventh embodiment, the operation modules 6c and 6d are in a failure state,
It is assumed that the input signal 12a is processed by the operation modules 6a and 6b, and the input signal 12b is processed only by the standby operation module 6e. Now, the operation module selector 7
Calculates the signal of the input signal 12a having the period 10 by the arithmetic module 6
after inputting the signal of cycle 10 of the input signal 12b to the two-dimensional memory 1b of the standby operation module 6e, the master local computer 9a
It is assumed that information has been obtained from the operation module inspection unit 14 indicating that the standby operation module 6e has failed. Then
The master local computer operates the operation display unit 1 of the entry corresponding to the operation module 6e of the distribution table 15.
At the same time, "1" is written in 5a, and information to change the processing amount of the input signal 12a from 2 to 1 is sent to the arithmetic module selector control unit 11. The operation module selector control unit 11 controls the operation module selector 7 to
Since the processing amount of the input signal 12a sent from the master local computer 9a is 1, the sorting table 15
The operation module 6a in which the operation display unit 15a is one entry of “0” from the upper level is made valid. Therefore, the input signal 12a is alternately input to the two-dimensional memories 1a and 1b of the arithmetic module 6a after the period 11, and the input signal 12a input to the arithmetic module 6a in this manner is the same as in the first embodiment. Processed on a cycle-by-cycle basis. On the other hand, since the processing amount of the input signal 12b is still 1, the first one in the sorting table 15 used for the input signal 12a is first.
One entry whose operation display section 15a is "0" becomes valid after the entry, and in the period 11 and thereafter, the two-dimensional memories 1a and 1b of the operation module 6b written therein are valid.
The input signal 12b is input alternately. The input signal 12b input to the arithmetic module 6b in this way is processed in each cycle unit as in the first embodiment.

According to the present embodiment, the standby system operation module is made to stand by, and even if a plurality of operation modules fail, as long as there are at least as many operable operation modules as the number of input signals, these operation modules are not operated. By appropriately reassembling the modules for input signals, the amount of input signal processing is adjusted, so that continuous processing of input signals can be continued without stopping the apparatus.

Embodiment 9 FIG. A ninth embodiment of the present invention will be described with reference to FIGS. FIG. 19 shows the configuration of the present embodiment.
These are connected to a host computer via a signal processing module output bus. In the figure, 12c, 12
d, 12e, 12f, 12g, and 12h are input signals sent from the outside, 16a, 16b, 16c, and 16d are signal processing modules having the configuration shown in FIG. 13, and 17 is the signal processing modules 16a, 16b, 16c, and 16d. A host computer for performing further processing on the processing result of
8 is a signal processing module 16a, 16b, 16c, 16
d is a signal processing module output bus connecting the host and the host computer. The signal processing module has the same configuration as that shown in FIG.

Next, the operation of this embodiment will be described with reference to the time chart of FIG. The host computer 17
Signal processing module 1 for each cycle of input signal 12a
The processing result of 6a and the processing result of the signal processing module 16b for each cycle of the input signal 12c are alternately taken out via the arithmetic module output bus 18, and the processing result corresponding to each cycle of the two signal processing modules is obtained. Further, processing such as correlation calculation is performed. In the present embodiment, the host computer 17 has shown that the correlation operation can be performed on two signals processed by different signal processing modules. However, the host computer 17 processes the signals in the same signal processing module and handles two input signal systems. In the same manner as in the present embodiment, the processing results output to different arithmetic module output buses
It is possible to perform a correlation operation and the like by alternately taking out the two processing results.

According to this embodiment, a plurality of signal processing modules are connected to the host computer via the signal processing module output bus. The host computer can perform further processing.

Embodiment 10 FIG. A tenth embodiment of the present invention will be described with reference to FIG. The configuration of this embodiment is
Since the configuration of the ninth embodiment is the same as that of FIG. 19, the description is omitted.

Next, the operation of this embodiment will be described with reference to the time chart of FIG. The host computer 17 controls the signal processing module 16 for each cycle of the input signal 12a.
a, the processing result of the signal processing module 16b for each cycle of the input signal 12c, the processing result of the signal processing module 16c for each cycle of the input signal 12e, and the processing result of the signal processing module 16d for each cycle of the input signal 12g. The processing results are sequentially taken out via the signal processing module output bus 18. Then, the input signal 12a
And a correlation operation between the processing result of the input signal 12c and the processing result of
The correlation operation between the processing result of the input signal 12e and the processing result of the input signal 12g is performed alternately. In the present embodiment, the host computer 17 has been shown to be able to perform the correlation operation for each two signals among the four signals processed by the different signal processing modules. However, the host computer 17 relates to two signal systems processed in the same module. The correlation operation can also be performed by sequentially taking out four processing results as in the present embodiment.

According to the present embodiment, a plurality of signal processing modules are connected to the host computer via the signal processing module output bus. Further processing can be performed by the host computer.

Embodiment 11 FIG. An eleventh embodiment of the present invention will be described with reference to FIGS. FIG. 22 shows the configuration of the present embodiment. In FIG. 19 which shows the configuration of the tenth embodiment, a signal processing module selector for selecting a plurality of input signals and inputting them to a signal processing module is provided. The other parts are the same as those in FIG. 19 showing the configuration of the tenth embodiment, and the description is omitted. In the figure, reference numeral 19 denotes a signal processing module selector for inputting a plurality of input signals to a plurality of signal processing modules under the control of the host computer according to the processing amount of the input signal and the processing performance of the signal processing module.

The operation of this embodiment will be described with reference to the configuration diagram shown in FIG. Signal processing modules 16a, 16
b, 16c, 16d, the operation module inspection unit 1
Reference numeral 4 denotes operation modules 6a, 6b, 6c, 6
d and the standby operation module 6e are inspected for normal operation, and when a faulty operation module is found,
The operation information is sent to the master local computer 9a. The master local computer 9a further sends the received operation information to the host computer 17. The host computer 17 controls each of the signal processing modules 16a, 16
b, 16c, 16d, and receives the operation information and the input signals 12a, 12b, 12c, 12d, 12
Based on the processing amounts of e, 12f, 12g, and 12h, a combination of which input signal is input to the signal processing module is created.

FIG. 23 shows a combination of an input signal and a signal processing module. FIG. 23A shows a state in which the number of operating modules in the signal processing modules 16b and 16d is three, and all of the other signal processing modules are operating.
Then, each of the input signals 12a, 12b, 12c, 12d,
The processing amounts of 12e, 12f, 12g, and 12h are 3,
In the case of 1, 1, 2, 3, 1, 2, 1, the signal processing module 16a performs processing on the input signals 12a and 12b, and the signal processing module 16b performs processing on the input signals 12g and 1g.
The combination of 2h, the signal processing module 16c performs processing on the input signals 12c and 12e, and the signal processing module 16d performs processing on the input signals 12d and 12f. Further, a combination as shown in FIG. 23B is also possible.

The host computer 17 controls the signal processing module selector 19 on the basis of the combination information shown in FIG. 23 (a), inputs each input signal to the signal processing module, and sets each of the signal processing modules 16a, 16b. ,
The period of two input signals input to the signal processing module and the processing amount are sent to the master local computers 9a of 16c and 16d. Then, the signal processing module 16
a, the master local computer 9a distributes the operation information obtained from the operation module inspection unit 14 to the distribution table 15a.
Of the input signal 12a and the processing amount (3) of the input signal 12a, and the period and the processing amount (1) of the input signal 12b to the operation module selector control unit 11. The arithmetic module selector control unit 11 controls the arithmetic module selector 7 to control the input signal 12a in each cycle.
And 12b, and the processing amount of the input signal 12a is 3, so that the operation display unit 15
a is valid for three entries, and the two-dimensional memory 1a of the operation module 6a, the two-dimensional memory 1a of the operation module 6b, the two-dimensional memory 1a of the operation module 6c, and the three-dimensional memory The input signals 12a that have been periodically divided are sequentially input in the order of the two-dimensional memory 1b. In this way, the operation modules 6a, 6b,
The input signal 12a input to 6c is processed in each cycle unit as in the first embodiment. On the other hand, the input signal 12b is stored in the two-dimensional memories 1a and 1b of the operation module 6d in which the operation display section 15a is written in one entry of "0" after the upper three entries of the sorting table 15 used for the input signal 12a. Input alternately. Thus, the input signal 12b input to the arithmetic module 6d
Is processed in each cycle unit in the same manner as in the first embodiment. The same processing is performed for the other signal processing modules 16b, 16c, and 16d.

According to the present embodiment, the combination of an input signal and a signal processing module for processing the input signal can be appropriately determined according to the processing amount of the input signal and the processing capability of the signal processing module. Optimal load distribution according to the amount and the processing capacity of the signal processing module can be performed.

Embodiment 12 FIG. A twelfth embodiment of the present invention will be described with reference to FIG. The configuration of this embodiment is
Since it is the same as FIG. 22 showing the configuration of the eleventh embodiment, the description is omitted.

Next, the operation of this embodiment will be described with reference to FIGS.
4 will be described. In the eleventh embodiment, it is assumed that one operation module of the signal processing module 16b has failed and the number of operation modules operating normally becomes two. At this time, the host computer 17 newly creates a combination of the input signal and the operation module, and performs the same processing as in the eleventh embodiment. FIG. 24 shows a combination in a case where one operation module of the signal processing module 16b fails in FIG. 23A and the number of operation modules that are operating normally becomes two. Since the number of operation modules in which the signal processing module 16b operates normally changes from 3 to 2, the number of processed input signals 12g is changed from 2 to 1 to cope with a failure of the operation module. It is also possible to change the processing amount of another input signal and create a new combination.

According to the present embodiment, even if the arithmetic module fails, by adjusting the processing amount of the input signal, it is possible to continue the continuous and simultaneous processing of the input signal without stopping the apparatus.

Embodiment 13 FIG. A thirteenth embodiment of the present invention will be described with reference to FIGS. 25, 26, and 27. FIG. 25 shows the configuration of the present embodiment. In FIG. 22 showing the configuration of the eleventh embodiment, a standby signal which normally stands by as a standby and performs a substitute process when another signal processing module fails. The processing module is provided, and the other parts are the same as those of the eleventh embodiment shown in FIG. In the figure, reference numeral 16e denotes a standby signal processing module that normally stands by as a standby, and performs processing when another signal processing module fails.

Next, the operation of this embodiment will be described with reference to FIGS. 25, 26, and 27. When processing is performed with the combination of the input signal and the signal processing module shown in FIG. 26A, the operation modules 6a, 6b, 6c, 6d and the standby operation module 6e in the signal processing module 16b are processed.
If all of the failures occur, this operation information is sent from the operation module inspection unit 14 to the host computer 17 via the master local computer 9a. The host computer 17 newly activates the standby signal processing module 16e which has been in the standby state since there is no normally operating operation module and the standby operation module in the signal processing module 16b, and FIG. ), A new combination of the input signal and the operation module is created. In this combination, the processing amounts of the input signals 12g and 12h, which have been processed by the signal processing module 16b, are respectively set to 1, 1 as before, and the standby signal processing module 16e is processed. In addition, although the standby system signal processing module 16e has all the operation modules that can normally operate, but there is an operation module that is not used in this combination, the processing amounts of the input signals 12g and 12h are reduced by 3, 1 respectively. Alternatively, it is also possible to change to 2, 2 or 1, and to make the standby signal processing module perform processing. Also, by changing the combination of input signals to the signal processing module and changing the processing amount of each input signal, it is also possible to create a new combination as shown in FIG.

Further, in the sixth to twelfth embodiments, the operation module checking unit 14 can be provided inside the master local computer 9a. Further, in the first to twelfth embodiments, the arithmetic module selector control unit can be provided inside the master local computer 9a. Further, in Examples 4 to 12,
When the local computers 9a and 9b in each signal processing module communicate with each other and the master local computer 9a fails, the local computer 9b
Can also take the place.

According to the present embodiment, when one of the signal processing modules fails, a standby signal processing module is incorporated, and the input signal and the input signal are converted according to the processing amount of the input signal and the processing capability of the signal processing module. Since the combination of the signal processing modules to be processed is newly determined, it is possible to perform the optimum load distribution according to the processing amount of the input signal and the processing capability of the signal processing module. Further, even if a signal module fails, continuous and simultaneous processing of input signals can be continued without stopping the apparatus and without reducing the processing amount of input signals.

[0072]

Since the present invention is configured as described above, the following effects can be obtained. According to the present invention, an input signal from the outside is divided in units of a certain period, is sequentially allocated to one or more operation modules, and is double buffered with respect to a plurality of two-dimensional memories in the operation modules. And
A plurality of processors in the operation module can perform parallel processing, and the input bus and the output bus to the operation module are independent, so that input signals can be processed at high speed and continuously.

Further, the processing time of the two-dimensional memory can be reduced because the processor in the arithmetic module can access the column memory in both the column direction and the row direction.

Since the computer is connected to the output bus of the arithmetic module, processing can be added to the output result of the arithmetic module as needed.

Further, since the load distribution of the operation modules is performed according to the processing amount of the input signal, the processor can be used efficiently and the consistency as a system can be maintained.

The operation modules can be grouped corresponding to a plurality of input signal systems, and signal input, operation processing, and operation result output can be performed independently for each group, so that parallel processing can be performed for the signal systems. It is.

When one of the operation modules fails, a spare operation module is incorporated. When all of the standby operation modules are already operating,
Since a part of the operating arithmetic module is substituted for the processing, a plurality of input signals can be processed simultaneously and continuously without reducing the number of input signals to be processed even if the arithmetic module fails. is there.

Further, since a plurality of arithmetic modules are configured as one signal processing module and a computer is connected to the output bus of each signal module, parallel processing can be performed for each signal processing module. Further, a processing operation can be added to the output result of the signal processing module as needed.

Further, the combination of the input signal and the signal processing module for processing the input signal is determined according to the processing amount of the input signal and the processing capability of the signal processing module (the number of operation modules operating normally). Optimal load distribution according to the processing amount and the processing capability of the signal processing module can be performed, and the processor can be used efficiently. Further, even if the arithmetic module fails, a plurality of input signals can be simultaneously and continuously processed without reducing the number of input signals to be processed.

In addition, if the signal processing module fails, a standby signal processing module is incorporated. If all the standby signal processing modules in standby are already operating, an input to the active signal processing module is input. Since the combination of signals and the processing amount are changed and adjusted, continuous processing can be performed without reducing the number of input signals to be processed even if the signal processing module fails.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of first, second, and third embodiments of the present invention.

FIG. 2 is a configuration diagram of a distribution table according to the first embodiment of the present invention.

FIG. 3 is a time chart showing an operation in the first embodiment of the present invention.

FIG. 4 is a flowchart showing an input signal storage location in a cycle unit according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a method of accessing a two-dimensional memory according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a method of accessing a two-dimensional memory according to the first embodiment of the present invention.

FIG. 7 is a time chart showing the operation of the second embodiment of the present invention.

FIG. 8 is a time chart showing the operation of the third embodiment of the present invention.

FIG. 9 is a time chart showing the operation of the third embodiment of the present invention.

FIG. 10 is a diagram illustrating a configuration of a fourth and a fifth embodiment of the present invention.

FIG. 11 is a time chart showing the operation of the fourth embodiment of the present invention.

FIG. 12 is a time chart showing the operation of the fifth embodiment of the present invention.

FIG. 13 is a diagram illustrating a configuration of a sixth, a seventh, and an eighth embodiment of the present invention.

FIG. 14 is a configuration diagram of a distribution table according to a sixth embodiment of the present invention.

FIG. 15 is a time chart showing the operation of the sixth example of the present invention.

FIG. 16 is a time chart showing the operation of the sixth example of the present invention.

FIG. 17 is a time chart showing the operation of the seventh embodiment of the present invention.

FIG. 18 is a time chart showing the operation of the eighth example of the present invention.

FIG. 19 is a diagram illustrating a configuration of ninth and tenth embodiments of the present invention.

FIG. 20 is a time chart showing the operation of the ninth embodiment of the present invention.

FIG. 21 is a time chart showing the operation of the tenth embodiment of the present invention.

FIG. 22 is a diagram illustrating a configuration of eleventh and twelfth embodiments of the present invention.

FIG. 23 is a diagram showing a combination of an input signal and a signal processing module according to an eleventh embodiment of the present invention.

FIG. 24 is a diagram showing a combination of an input signal and a signal processing module according to a twelfth embodiment of the present invention.

FIG. 25 is a diagram illustrating a configuration of a thirteenth embodiment of the present invention.

FIG. 26 is a diagram showing a combination of an input signal and a signal processing module according to a thirteenth embodiment of the present invention.

FIG. 27 is a diagram showing a combination of an input signal and a signal processing module according to a thirteenth embodiment of the present invention.

FIG. 28 is a configuration diagram of a conventional signal processing device of the present invention.

[Explanation of symbols]

1a, 1b Two-dimensional memory 2a, 2b, 2c, 2d Local memory 3a, 3b, 3c, 3d Processor 4 Shared bus 5 Internal bus 6a, 6b, 6c, 6d Operation module 6e Spare operation module 7 Operation module selector 8, 8a , 8b Input bus 9, 9b Local computer 9a Master local computer 10, 10a, 1
0b Operation module output bus 11 Operation module selector control unit 12, 12a, 12b, 12c, 12d, 12e, 12
f, 12g, 12h input signal 13, 15 distribution table 14 operation module inspection unit 15a distribution table operation display unit 15b distribution table data input device display unit 16a, 16b, 16c, 16d signal processing module 16e standby signal processing module 17 host computer 18 Signal processing module output bus 19 Signal processing module selector

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-2-224186 (JP, A) JP-A-3-2055985 (JP, A) JP-A-5-143552 (JP, A) JP-A-4- 299743 (JP, A) JP-A-4-62641 (JP, A) Information Processing Society of Japan Vol. 92, NO. 64 1992 pp. 49-56 Information Processing Society of Japan Research Report VOL. 96, NO. 80 1996 pp89-94 (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 15/167 G06F 15/177 678 INSPEC (DIALOG) JICST file (JOIS) WPI (DIALOG)

Claims (10)

(57) [Claims] 1. A signal processing device for processing a signal which is divided and input at a fixed period, wherein the plurality of arithmetic modules for performing data processing and the input signal which is sent from outside are divided at a certain period and An operation module selector for sequentially distributing the operation modules to a plurality of operation modules; an input bus for connecting the operation module selector and the plurality of operation modules; and an input bus provided independently of the input bus to the operation modules, via the input bus. An operation module output bus that outputs an operation result of the operation module in parallel with the operation;
A plurality of processors, each of which is configured for a local memory and performs a parallel process on data on the local memory; a local memory; a data input connected to the input bus and the arithmetic module output bus; And an internal bus shared when the operation result is transferred to the operation module output bus, and a data fetch operation via the input bus connected to the internal bus and an access process from the processor for each memory device. Multiple 2s configured to run in parallel
A signal processing device comprising: a three-dimensional memory device. 2. The signal processing apparatus according to claim 1, wherein said two-dimensional memory device is capable of accessing said processor in any of a row direction and a column direction. 3. A local computer connected to the arithmetic module output bus, and a variable number of arithmetic modules for controlling the arithmetic module selector and processing an input signal based on a command sent from the local computer. 3. The signal processing device according to claim 1, further comprising: an operation module selector control unit that performs the operation. 4. An input signal to the operation module selector is provided in a plurality of systems, and an input bus to each operation module and an output bus from each operation module are also provided in the same plurality of systems, so that a plurality of operation module output buses are supported. A local computer is connected, and one of the local computers is used as a master local computer. The arithmetic module selector control unit sends an input signal to each arithmetic module corresponding to each input signal system based on a command sent from the master local computer. 4. The signal processing device according to claim 1, wherein the signal is distributed. 5. An operation module checker that allows an arbitrary number of the plurality of operation modules to stand by as a standby operation module, monitors an operation state of the operation module, and sends information on an operation state of each operation module to the master local computer. The master local computer incorporates a spare operation module into the operation module selector control unit when a malfunction is detected in the operating operation module based on the information sent from the operation module inspection unit. 5. The signal processing device according to claim 4, wherein a command is issued to set the operation state. 6. Arithmetic module inspection in which an arbitrary number of the plurality of arithmetic modules are put on standby as a standby arithmetic module, an operation status of the arithmetic module is monitored, and information on an operation status of each arithmetic module is sent to the master local computer. A failure detecting unit that detects an occurrence of a defect in the operating arithmetic module based on the information sent from the arithmetic module checking unit, and when the standby arithmetic module is already installed and operating, the master local 5. The signal processing apparatus according to claim 4, wherein the computer issues an instruction to the arithmetic module selector control unit regarding the number of arithmetic modules for processing input signals and a change in combination of the arithmetic modules. 7. A plurality of signal processing modules each including the plurality of arithmetic modules as one signal processing module; an output bus connecting the plurality of signal processing modules; and an output bus of the signal processing module. 7. The signal processing device according to claim 5, comprising a host computer connected to the signal processing device. 8. A signal processing module selector for distributing a plurality of input signals sent from the outside to the plurality of signal processing modules, wherein the host computer is transmitted from a master local computer in each of the signal processing modules. 8. The signal processing device according to claim 7, wherein the signal processing module selector is controlled based on information that comes. 9. An arbitrary number of the plurality of signal processing modules is used as a standby signal processing module, and when a malfunction occurs in an active signal processing module, the host computer instructs the signal processing module selector to execute a standby signal processing. 9. The signal processing device according to claim 8, wherein a command is issued to set the module into an operating state. 10. A case where any number of the plurality of signal processing modules are used as a standby signal processing module, and a failure occurs in an active signal processing module, and all the standby signal processing modules are installed and operating. 9. The signal processing apparatus according to claim 8, wherein the host computer issues a command to the signal processing module selector to change a combination of an input signal and a signal processing module for processing the input signal.