JP2001257740A - Subordinate unit opposite test system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a subordinate unit opposite test system that can reduce a test time for a test opposite to a subordinate unit by conducting subordinate unit opposite tests at the same time. SOLUTION: A test program 11 is a program that is built in a host device to control the entire test. A dual port memory 12 is used for an interface area. A subordinate unit 2 and 2a have a test program 3 and 3a. An address conversion section 13 converts a test address into an address of a common area 23 being the same areas as the test program 3a of the opposite subordinate unit 2a for an opposite test when receiving an access to the test address from the test program 3 in the subordinate unit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lower device facing test method, and more particularly to a lower device facing test method for mutually controlling the execution of a test procedure among a plurality of lower devices.

[0002]

2. Description of the Related Art In general, a test as to whether or not a device incorporating a microprocessor is normal is executed by executing a self-diagnosis program by the microprocessor.

As an example of such a test using a microprocessor, there is known a "microprocessor diagnostic method" described in Japanese Patent Application Laid-Open No. 3-12747.

This publication describes a technique for testing the function of the entire device as a microprocessor system using a diagnostic program stored in the device.

[0005] Further, when an apparatus having a built-in microprocessor constitutes a hierarchical system of a higher-level device and a lower-level device, it is necessary to test the lower-level device.

[0006] Such a lower device facing test method uses a dual port memory to perform an facing test between lower devices while interfacing an upper device with a processor and a plurality of lower devices with a processor. Since the interface between the device and the lower device is one-to-one, the test program in the upper device issues an instruction to each lower device test program via the dual port memory and controls each lower device test program during the test. It will be tested while doing.

[0007]

In the above-mentioned conventional lower device facing test method, since the upper device and the lower device take an interface via the dual port memory, the lower devices cannot directly communicate with each other. Since the test program in the upper device must sequentially control a plurality of test programs in the lower device and perform the opposition test in order, there is a disadvantage that the lower device opposition test takes time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a lower device facing test method for simultaneously executing a plurality of lower device facing tests and reducing the test time without being controlled by a test program in the upper device during the lower device facing test. It is in.

[0009]

According to the present invention, there is provided an electronic system comprising a plurality of lower devices and an upper device for controlling the lower devices, wherein a test program stored in each of the lower devices is provided. Performs information exchange between the lower-level devices using a common area of the dual-port memory of the upper-level device, thereby controlling the test procedure of the lower-level device without being controlled by the test program of the upper-level device. It is characterized by doing.

Each of the plurality of lower devices includes a processor, and one higher device includes a processor. The plurality of lower devices communicate with each other via the dual port memory in the higher device. When performing the interface test of a plurality of the lower device facing each other,
An address conversion unit in the higher-level device that allows the plurality of lower-level devices to access the same address of the dual-port memory allows direct exchange of information between test programs in the lower-level device via the same address of the dual-port memory to test. The test is performed while controlling the procedure of (1).

A high-level device having a processor and a plurality of low-level devices each having a processor;
The higher-level device includes a test program, a dual-port memory used as an interface area, and an address converter connected to the dual-port memory. Each of the plurality of lower-level devices has a test program, The device and the plurality of lower devices are respectively connected to the plurality of lower devices via the address converter and a plurality of higher device interfaces connected thereto,
The plurality of lower-level devices are interconnected by a lower-level device interface.

[0012] When the first address conversion unit accesses the test address from the first test program in the first lower-level device, the address conversion unit performs a second test of the second lower-level device on the opposite side to perform the opposite test. The address is converted to a common area which is the same area as the program, and the first test program in the first lower device and the second test program in the second lower device are converted.
The test program is characterized in that the test is performed while mutually notifying the test execution state of the own program via the common area.

[0013] The test program in the host device includes:
For the first and second test programs in the first and second lower-level devices, a lower-level device facing test start instruction is sent to a first area and a second area, which are normal interfaces of the dual port memory. The test is started by writing each.

Further, the present invention is characterized by a multiprocessor system using a lower device facing test method.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the lower device facing test system of the present invention.

The embodiment shown in FIG. 1 comprises a host device 1 having a processor mounted thereon, and a plurality of lower devices 2, 2a, 2n each having a processor mounted thereon.

The upper device 1 has a test program 11, a dual port memory 12 used as an interface area, and an address converter 13 connected to the dual port memory 12. The lower devices 2, 2a, and 2n each have It has test programs 3, 3a and 3n. The upper device 1 and the lower devices 2, 2a, 2n
3 and the higher-level device interfaces 15 and 15 connected thereto
a, 15n are connected to the lower devices 2, 2a, 2n, respectively. The lower-level device 2 and the lower-level device 2a are mutually connected by a lower-level device interface 16.

FIG. 2 is a detailed block diagram showing the operation of the lower device facing test method of the present invention.

In FIG. 2, components corresponding to those shown in FIG. 1 are denoted by the same reference numerals or symbols, and description thereof will be omitted.

Referring to FIG. 2, the address translator 13
When there is an access from the test program 3 in the lower device 2 to the test address, the address is converted to the common area 23 in the same area as the test program 3a of the lower device 2a on the opposite side that performs the opposite test. The test program 3 in the lower order device 2 and the test program 3a in the lower order device 2a execute a test while mutually notifying the test execution state of the own program via the common area 23.
Note that the test address means a virtual address when the dual port memory 12 is viewed as a virtual memory.

FIG. 3 is a flowchart showing the operation of FIG.

FIG. 3A is a flowchart of the test program in the upper device, FIG. 3B is a flowchart of the test program in the lower device 2, and FIG.
3 shows a flowchart of a test program in a.

FIG. 4 is a diagram showing the operation of a test program between lower-level devices.

Next, the operation of the present embodiment will be described in more detail with reference to FIG. 2, FIG. 3, and FIG.

The test program 11 in the higher-level device 1 issues a lower-device-facing test start instruction to the test programs 3 and 3a in the lower-level devices 2 and 2a. The test is started by writing the data into the lower device 2a area 22 (step 11: S11).

The test program 3 in the lower-level device 2 reads the lower-level device 2 area 21, executes the processing 1, accesses the test address when completed, and returns to the lower-level device 2 status 4 in the common area 23 of the dual port memory 12. The completion notice 5 is written (step 21: S21).

The test program 3 in the lower device 2a
a reads out the lower device 2a area 22, executes the process 2, accesses the test address when completed, and writes the completion notification 5a to the lower device 2a status 4a of the common area 23 of the dual port memory 12 (step 31:
S31).

The test program 3 in the lower-level device 2 reads the status 4a of the lower-level device 2a in the common area 23 of the dual port memory 12, checks whether the processing 2 of the test program 3a in the lower-level device 2a is completed, and completes. If not, the reading of the status of the lower-level device 2a 4a is repeated until it is completed (Steps 22 and 23: S22, S2
3).

The test program 3 in the lower device 2a
“a” reads the lower device 2 status 4 in the common area 23 of the dual port memory 12 and checks whether the processing 1 of the test program 3 in the lower device 2 has been completed. (Steps 32 and 33: S32, S3
3).

The test program 3 in the lower order device 2 executes the process 3 if the process 2 of the test program 3a in the lower order device 2a is completed, and accesses the test address when the process 2 is completed. The completion notification 5 is written to the lower-level device 2 status 4 of the shared area 23 (step 24: S24).

The test program 3 in the lower device 2a
a, if the processing 1 of the test program 3 in the lower-level device 2 is completed, the processing 4 is executed; if completed, the test address is accessed, and the common area 2 of the dual port memory 12 is accessed.
The completion notification 5a is written to the status 4a of the third lower-level device 2a (step 34: S34).

The test program 3 in the lower device 2 reads the status 4a of the lower device 2a in the common area 23 of the dual port memory 12, checks whether the processing 4 of the test program 3a in the lower device 2a is completed, and completes. If not, the reading of the status 4a of the lower device 2a is repeated until it is completed (Steps 25 and 26: S25, S2
6).

The test program 3 in the lower device 2a
a reads the status 4 of the lower device 2 in the common area 23 of the dual port memory 12 and checks whether the processing 3 of the test program 3 in the lower device 2 has been completed. (Steps 35 and 36: S35, S3
6).

The test program 3 in the lower order device 2 executes the process 5 if the process 4 of the test program 3a in the lower order device 2a is completed.
2 is written to the lower device 2 area 21 (S2).
7) Notify to the test program 11 in the host device 1.

The test program 3 in the lower device 2a
If the process 3 of the test program 3 in the lower device 2 is completed, the process 6 is executed, and if it is completed, a completion notification is written to the lower device 2a area 22 of the dual port memory 12 (S37), and the upper device 1 Notify to the test program 11 within.

The test program 11 in the upper device 1 reads the lower device 2 area 21 and the lower device 2a area 22 of the dual port memory 12 (S13), and ends the test.

As described above, the lower device test program performs the lower device facing test while controlling the test. More specifically, when the lower-level device accesses the dual-port memory 12 of the higher-level device, the address conversion unit 13 converts the address to a common area 23 that can be accessed by a plurality of lower-level devices. It has a test program 3 in the lower device 2 and a test program 3a in the lower device 2a for controlling a test by exchanging information and performing a lower device facing test, and is controlled by the test program 11 in the higher device. Without, the lower device test program 3
Since the test is controlled by exchanging information between the devices 3a and 3a, a plurality of lower device facing tests can be performed simultaneously.

That is, a test program in a lower device performs a test between lower devices in an electronic device having a plurality of lower devices while controlling a test procedure.

In the above description, the area of the dual port memory 12 has been described as being limited to the two lower devices 2 and 2a, but the present invention is not limited to this.

Also, by using the above-described lower device facing test method in an electronic system having a multiprocessor system configuration, it is possible to perform a lower level facing test.

[0042]

As described above, according to the lower apparatus opposing test method of the present invention, the test program in the upper apparatus only starts the test for all the test programs in the lower apparatus, and the test is sequentially controlled during the test. This eliminates the necessity and allows simultaneous execution of a plurality of lower-level device facing tests. Therefore, when conducting a facing test of a plurality of lower-level devices, there is an effect that the total test time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a lower device facing test system of the present invention.

FIG. 2 is a detailed block diagram showing the operation of the lower device facing test method of the present invention.

FIG. 3 is a flowchart showing the operation of FIG. 2;

FIG. 4 is a diagram showing the operation of a test program between lower-level devices.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Upper device 2, 2a, 2n Lower device 3, 3a, 3n Test program 4 Lower device 2 status 4a Lower device 2a status 5, 5a Completion notification 11 Test program 12 Dual port memory 13 Address conversion unit 15, 15a, 15n Upper device Interface 16 Lower device interface 21 Lower device 2 area 22 Lower device 2a area 23 Common area

Claims (6)

[Claims] 1. An electronic system comprising a plurality of lower devices and a higher device controlling the lower devices, wherein a test program of each of the lower devices uses a common area of a dual port memory of the higher device. A lower device facing test method, wherein a test is performed while controlling a test procedure of the lower device by exchanging information between the lower devices without being controlled by a test program of the higher device. 2. A plurality of lower-level devices each including a processor, and one higher-level device including a processor, wherein the plurality of lower-level devices are connected via a dual-port memory in the higher-level device. When performing an interface test between devices with a plurality of the lower devices facing each other,
An address conversion unit in the upper-level device directly exchanges information between test programs in the lower-level device via the same address in the dual-port memory so that a plurality of the lower-level devices can access the same address in the dual-port memory. A lower-level device facing test method, wherein a test is performed while controlling the test procedure. 3. A high-level device including a processor, and a plurality of low-level devices each including a processor. The high-level device includes a test program, a dual-port memory used as an interface area, and a dual-port memory. An address translator connected to a memory, wherein each of the plurality of lower devices has a test program; and the upper device and the plurality of lower devices are the address translator and a plurality of upper devices connected thereto. A lower device facing test method, wherein the lower device is connected to each of the plurality of lower devices via a device interface, and the plurality of lower devices are connected to each other by a lower device interface. 4. The address conversion unit according to claim 2, wherein when the first test program in the first lower-level device accesses the test address, the address converter converts the second lower-level device on the opposite side that performs the opposite test. The first test program in the first lower-level device and the second test program in the second lower-level device perform address conversion to a common area which is the same area as the test area of the common area. 4. The lower-device-facing test method according to claim 3, wherein the test is performed while mutually notifying the test execution status of the own program via each other. 5. The dual-port memory according to claim 1, wherein the test program in the host device sends a lower device facing test start instruction to the first and second test programs in the first and second lower devices. 5. The test is started by writing to the first area and the second area, respectively, which are the normal interfaces of the test.
The lower device facing test method described. 6. A multiprocessor system using the lower device facing test method according to claim 1. Description: