JP3177131B2 - Electronic circuit analyzer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation analysis apparatus for an electronic circuit equipped with a microprocessor (MPU), and more particularly, to an operation analysis of a plurality of electronic circuits or one electronic circuit equipped with a plurality of MPUs. The present invention relates to a novel device that can be applied to motion analysis. In recent years, high-performance electronic devices equipped with an MPU have been produced in various fields. This is because, simply by replacing the ROM (read only memory) in which the software is written, the system can be easily modified or the functions can be changed, and a highly flexible system can be developed. By the way, in such an electronic circuit, debugging of hardware and software is considerably difficult due to its high functionality, and some kind of debugging support device is indispensable.

[0002]

2. Description of the Related Art As this kind of support device, conventionally,
Electronic circuit to be debugged (hereinafter referred to as "target")
An in-circuit emulator (hereinafter referred to as "ICE") that simulates the execution of a program, a ROM in-circuit debugger, and the like are known. For example, ICE is the target side M
The MPU on the ICE side operates instead of the PU, and this MP
The operation of U is traced by emulator software one by one.
By monitoring, the operating state of the target is comprehensively determined.

[0003]

However, in such a conventional support device, since the MPU on the target side and the MPU on the support device correspond one-to-one, for example, a plurality of targets (electronic circuits) are required. )
In the case of performing the processing in parallel, the same number of support devices as the target is required, or when a single target is equipped with a plurality of MPUs (multi-MPU), all the MPUs are required. There is a problem that the motion analysis cannot be performed for the

[0004] Therefore, an object of the present invention is to provide a novel apparatus which can be applied to the operation analysis of a plurality of electronic circuits or the operation analysis of one electronic circuit having a plurality of MPUs.

[0005]

According to the present invention, a target M
N units for connecting electronic circuits to be analyzed with PU
Interface section and the interface section
Access means, the interface unit and the
A system bus directly connected to the control means.
The interface unit may be configured such that the control unit is configured to control the
Access via a bus and the target MPU
And the programs that are accessed and executed by the target MPU
And various data necessary to execute the program and the
A storage device that stores the result of execution of a target MPU in an updatable manner
A step and the target set by the control means.
A mode register including a flag reset by the MPU;
And the control unit includes the interface unit.
When the program and the data are transferred to storage means
Together, the target is set by setting the flag.
Command to start execution of each transfer program by MPU
And the target MPU resets the flag.
Wait for the flag to reset and the flag is reset.
The execution result is read from the storage unit of the interface unit.
It is characterized by including and evaluating .

[0006] According to this, by simply transferring a required program or data to the n interface units, and instructing the start of the execution of the program, n target MPUs can be simultaneously and simultaneously transmitted through the n interface units. They can be operated in parallel, and each execution result can be read into the control means and evaluated and analyzed. Therefore, it is possible to analyze not only the operation of a plurality of electronic circuits but also the operation of one electronic circuit having a plurality of MPUs.

Alternatively, a plurality of computers are connected via a network, at least one of the plurality of computers is used as a remote machine, and other computers except the remote machine are used as local machines, and each local machine operates. Communication of the electronic circuit to be analyzed
With connecting parts, allocates memory means the local machine has a virtual drive of the remote machine, by accessing the respective local machine from the remote machine, if the operation analysis of said electronic circuit so as to remotely control This is preferable because the motion analysis can be performed from a remote place.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 are views showing an embodiment of an electronic circuit analysis device according to the present invention. First, the configuration will be described. In FIG. 1, 1 is a host computer (mapping unit and control unit), 2 is a system bus of the host computer, and 3 is an external slot (connection unit) connected to the system bus.

The host computer 1 has at least four elements of a digital computer (arithmetic unit, main storage unit, input / output unit, and control unit), and is compatible with an architecture.
It executes an arbitrary application program under S (operating system) (such as a personal computer or a workstation). Note that the application program of the present embodiment is an “electronic circuit analysis program” that analyzes the operation of n electronic circuits or the operation of one electronic circuit equipped with n MPUs. Here, n is 1 or an integer of 1 or more, but the maximum value is limited by the number of external slots 3 in terms of hardware.

The system bus 2 is connected to the host computer 1
, An internal bus connected to the CPU, and composed of a plurality of address lines 2A, a plurality of data lines 2D, and a plurality of control lines 2C, for example, an ISA bus, a PC
An I bus, a VL bus, a C bus and the like. The number of each line is determined by the architecture of the host computer 1. In the present embodiment, the system bus 2 is used, because it is easy to use . The system bus 2 is shown in FIG.
As shown in the figure, the option
Board (interface part) 4, 5 and host
Computer 1 directly.

The external slot 3 is an expansion slot for mounting various option boards using the system bus 2. In the present embodiment, the external slot 3 functions as an interface with an electronic circuit to be analyzed. (N = 2 for simplicity) optional boards (hereinafter, referred to as “first board 4 and second board 5”) are mounted. Note that a board generally refers to a printed board having a standardized size and connector, but is not limited to this in the present specification. Card type (typically PCMCI
A card).

The number of boards mounted is determined by the number of physical external slots 3. Since the number of slots limits the number of electronic circuits for operation analysis, and is used for other purposes other than operation analysis (for example, an additional memory board),
It is desirable to do as much as possible. The first board 4
A first electronic circuit includes a mode register 4a and an emulation ram (storage means) 4b, and a first electronic circuit via a first cable 6 including a plurality of address lines 6A, a plurality of data lines 6D, and a plurality of control lines 6C. Similarly, the second board 5 includes a mode register 5a and an emulation ram (storage means) 5b, a plurality of address lines 8A, and a plurality of data lines 8a.
It is connected to a second electronic circuit 9 via a second cable 8 composed of D and a plurality of control lines 8C.

The emulation ram 4b (5b)
This is an AM (random access memory), which is normally accessed from the host computer 1 via the system bus 2. However, while the "analysis mode flag" in the mode register 4a (5a) is set, the first Cable 6
(Second cable 8) through the first electronic circuit 7 (second
From the electronic circuit 9).
The setting of the analysis mode flag is performed by the host computer 1, and the reset is performed by the first electronic circuit 7 (second electronic circuit 9) that has completed a series of analysis sequences.

FIG. 2 is a memory map in the electronic circuit analyzer of this embodiment. 10 is a memory map of the host computer 1 (hereinafter, referred to as “host map”), 11 is a memory map of the first electronic circuit 7 (hereinafter, “first map”), and 12 is a memory map of the second electronic circuit 9 (Hereinafter referred to as “second map”). Host Map 10
Is a system user area 10a for an OS and an application program (electronic circuit analysis program),
The target areas 10b and 10c are divided into a plurality of target areas 10b and 10c, and the number of target areas 10b and 10c corresponds to the number of boards mounted in the external slot 3 (here, two), and the size of each target area 10b and 10c Corresponds to the capacity of the emulation ram 4b (5b). One target area 10c maps the emulation ram 4a of the first board 4, and the second target area 10b maps the emulation ram 5b of the second board 5. In the figure, the size of each of the target areas 10b and 10c (the capacity of the emulation rams 4b and 5b) is set to 1 Mbyte for convenience. That is, although not particularly limited, 500,000
One megabyte from (H) and one megabyte from 600,000 (H) are allocated to each target area 10b, 10c.

On the other hand, the first map 11 and the second map 1
2 is determined by the architecture of the first and second electronic circuits 7, 9, but here, the first electronic circuit 7,
Target MPU of “8086”, the second electronic circuit 9
Is assumed to be “68000”, and a map structure as shown in the figure is assumed. That is, the first map 11 has a dual port ram area, a static ram (S-RAM) area, and an EPROM area,
The second map 12 has an EPROM area, an S-RAM area, and an I / O area, but is not limited thereto.
The start address of the EPROM area of the first map 11 is the start address (F
FFF: 0 (H)) and the second map 12
The start address of the EPROM area is the same as the start address (0 (H)) of the 68000 type MPU.

FIG. 3 is a schematic flow chart of the electronic circuit analysis program. In this flow, the following processes are sequentially executed. That is, the first board 4 to which the first electronic circuit 7 was connected via the first cable 6 was mounted on the external slot 3, and the second electronic circuit 9 was connected via the second cable 8. After mounting the second board 5 in the external slot 3 and loading the OS and the electronic circuit analysis program into the main memory of the host computer 1 and then executing the electronic analysis program, first, the second board 5 is mounted in the external slot 3. The option boards are recognized, and a board for electronic circuit analysis (here, the first board 4 and the second board 5) is identified from the option boards (step 20). Then, the identified emulation rams 4b and 5b of the first board 4 and the second board 5 are mapped on the host map 10 (see FIG. 2) without duplication (step 21), and the emulation ram of the first board 4 is obtained. The required program and data are transferred to 4b (step 22). Here, the first board 4
The required programs and data to be transferred to the emulation ram 4b are programs to be executed by the target MPU of the first electronic circuit 7 and various data necessary for executing the programs. After transferring the required program and data, the "analysis mode flag" of the mode register 4a of the first board 4 is set (step 23) so that the emulation ram 4b can be accessed from the first electronic circuit 7. After that, the execution of the transfer program is instructed to enter a standby state (step 24).

In the standby state, the target MPU of the first electronic circuit 7 executes the program transferred to the emulation ram 4b, writes the execution result one by one into the emulation ram 4b, and terminates the program (normal termination). Or abnormal termination), the mode register 4
The “analysis mode flag” of a is reset. In response to this reset, the electronic circuit analysis program releases the standby state, reads the execution result in the emulation ram 4b, analyzes it (step 25), reads the following, and repeats the above steps 22 to 25 ( The number of repetitions is the number of boards mounted).

First board 4 → second board 5 Mode register 4a → mode register 5a Emulation memory 4a → emulation memory 5b First electronic circuit 7 → second electronic circuit 9 Thus, in this embodiment, The required programs and data are transferred from the host computer 1 to the emulation memories 4b and 5b of the boards 4 and 5 and the operation of the first and second electronic circuits 7 and 9 is analyzed simply by instructing the execution of the programs. Can be performed by the host computer 1, and the number of electronic circuits to be analyzed can be easily increased to the maximum number (n) of mounted boards.
A device suitable for use in analyzing the operation of a plurality of electronic circuits can be realized.

Although the operation of the first electronic circuit 7 is analyzed and then the operation of the second electronic circuit 9 is analyzed in the flow of FIG. 3, the present invention is not limited to this. For example, if the required programs and data are transferred to the emulation rams of all the boards and then the execution of the transfer program is instructed to each electronic circuit, the electronic circuits link and communicate with each other. In addition, the present invention can be applied to a system that operates while operating, and also to a so-called multi-MPU system in which a plurality of MPUs are mounted on one electronic circuit.

In the above embodiment, the option boards for operation analysis (boards 4 and 5) are directly connected to the system bus 2 of the host computer 1, but this is an example of a configuration in a case where the system is used stand-alone. When used in a network environment, for example, the following configuration may be used. 4 to 8 show another embodiment of the electronic circuit analyzing apparatus according to the present invention, which is an example configured in consideration of a network environment.

In FIG. 4, reference numeral 30 denotes a network such as a LAN or WAN, and a plurality of (three in FIG. 3) computers 31 to 33 are connected to the network 30 via network boards 31a to 33a. Have been. In all the computers 31 to 33, a network OS for both a server and a client is installed, and a so-called peer-to-peer network environment is realized. Note that the “server” refers to a computer that provides its own hardware assets to another computer, and the “client” refers to a computer that uses the server assets. Generally, in a peer-to-peer network OS, when a specific command is executed to load a server program into main memory, the computer becomes a server machine, and when a client program is loaded, the computer becomes a client machine, and both are loaded. Then, it becomes a server / client dual-purpose machine (the three computers 31 to 33 of the present embodiment).
Works as a server / client machine). In the following, for the sake of identification, the left computer 31 is referred to as a first computer, and the upper right computer 32 is referred to.
To the second computer, and the lower right computer 33 to the third computer.
Computer.

Communication boards 32b and 33b such as RS-232C are mounted on the second and third computers 32 and 33, respectively. Second and third computers 32, 33
Are the communication boards 32b and 33b and the cable 3
4, 35, and via the communication boards 36a, 36b (communication units of the electronic circuit ) mounted on the electronic circuit 36, control the operation of the electronic circuit 36 and collect information on the operation results.

FIG. 5 shows a memory map 37 of the second computer 32 and a memory map 3 of the third computer 33.
8 and the drive map 3 of the first computer 31
FIG. Although not particularly limited, the memory map 37 of the second computer 32 includes a dual port RAM area 37a, an S-RAM area 37b, and an EPROM area 3.
7c (when the target MPU mounted on the electronic circuit 36 is “8086”), and the memory map 38 of the third computer 33 has a sampling area 38
a, display data area 38b and I / O data area 38c
Consists of On the other hand, the drive map 39 indicates the local drive area 3 connected to the first computer 31.
1a, and a remote drive area 31b virtually connected via the network 30. In particular, the remote drive area 31b has a first remote drive area 31c corresponding to the memory map 37 of the second computer 32. , The memory map 38 of the third computer 33
And a second remote drive area 31d corresponding to the above. In other words, the local computer has
Map columns to virtual drives on remote machines
Has become. The “drive” may be an individual drive such as a floppy disk, a RAM disk, or a hard disk, a partition area in the hard disk, or a directory in an individual drive or a partition.

FIG. 6 is an overall schematic flow in the configuration example of FIG. In this flow, first, a network OS for a server and a network OS for a client are loaded on the first to third computers 31 to 33, respectively (step 40). The second and third computers 32 and 33 recognize the electronic circuit 36 connected to each of them, exchange basic information, and develop data including the information of the electronic circuit 36 on the memory maps 37 and 38 (step). 41). Next, the first computer 31 is operated as a client machine, the second and third computers 32 and 33 are accessed, and the respective memory maps 37 and 38 are stored in the first computer 31.
Are assigned to the first and second remote drive areas 31c and 32d of the computer 31 (step 42). Next, the first and second remote drive areas 31c, 31
d: the second and third computers 32,
The program and various data necessary for the operation analysis of the electronic circuit 36 are transferred to the memory maps 37 and 38 of the 33 (step 43), and the execution command of the transfer program is transmitted from the first computer 31 to the second and second memories. 3 (step 44). The second and third computers 32, 33 execute the required operation analysis program in response to the execution command, control the operation of the electronic circuit 36, collect the operation results, and read the memory maps 37, 38. Store in a predetermined area (Step 4
5). Then, the second and third computers 32, 33
Notifies the first computer 31 of the completion of the execution of the operation analysis program, and the first computer 31 receives the notification and sends the first and second remote drive areas 31
Contents of c and 31d, that is, contents of the memory maps 37 and 38 of the second and third computers 32 and 33.
Are evaluated or output to a printer or a display (step 46).

As described above, according to this embodiment, the second
And the memory map 3 of the third computer 32, 33
7 and 38 can be handled as the remote drive areas 31c and 31d of the first computer 31, for example, from the first computer 31 installed in a remote place,
The advantageous effect that the operation analysis of the electronic circuit 36 can be performed is obtained.

Alternatively, the first to third computers 31 to 3
Load some kind of remote control software in 3,
When the first computer is the master and the second and third computers 32 and 33 are operated as slaves, the keyboard and the display of the first computer 31 are used as if the keyboard and the display of the second computer 32 or the third computer 33 were provided. Can be treated the same as According to this, the master side (the first computer 3)
For example, when a predetermined memory debug command (see FIG. 7) is input to the display of 1), the same command is executed by the second computer 32 or the third computer 33 on the slave side, and the execution result (in this case, the memory Since the dump list) is also displayed on the display of the master side simultaneously with the slave side (see FIG. 8), the computer on the master side (first computer 31) is used by the computer on the slave side (second or third computer 3).
2, 33) can be remotely controlled, and a remote debugging environment can be easily constructed.

[0027]

According to the present invention, with the above-described configuration, not only the operation analysis of a plurality of electronic circuits but also the operation analysis of one electronic circuit having a plurality of MPUs can be performed. Alternatively, the motion analysis can be performed from a remote location.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of one embodiment.

FIG. 2 is a memory map diagram of one embodiment.

FIG. 3 is a schematic flowchart of one embodiment.

FIG. 4 is a schematic configuration diagram of another embodiment.

FIG. 5 is a memory map and drive map diagram of another embodiment.

FIG. 6 is a schematic flowchart of another embodiment.

FIG. 7 is a command input screen diagram of another embodiment.

FIG. 8 is an execution screen diagram of another embodiment.

[Explanation of symbols]

 1: host computer (mapping unit, control unit) 3: external slot (connection unit) 4: first board (interface unit) 4b, 5b: emulation ram (storage unit) 5: second board (interface unit) 30 : Network 31: first computer (remote machine) 32: second computer (local machine) 33: third computer (local machine) 36: electronic circuit

Continuation of front page (56) References JP-A-2-3836 (JP, A) JP-A-7-234805 (JP, A) JP-A-5-342038 (JP, A) JP-A-1-111238 (JP) JP-A-63-4346 (JP, A) JP-A-6-103106 (JP, A) JP-A-5-282471 (JP, A) JP-A-3-313954 (JP, A) 6-202901 (JP, A) JP-A-3-269735 (JP, A) JP-A-62-203238 (JP, A) JP-A-59-53457 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 11/22-11/36

Claims (3)

(57) [Claims] 1. An interface unit for connecting an electronic circuit to be analyzed for operation on which a target MPU is mounted, a control unit for accessing the interface unit, and a system bus for directly connecting the interface unit and the control unit And the interface unit, wherein the control unit accesses the target MP via the system bus.
A program to be accessed by the U and executed by the target MPU, various data necessary for the execution of the program, and storage means for storing the execution result of the target MPU in an updatable manner; the control means being set and the target MPU being reset A mode register including a flag, wherein the control unit transfers the program and the data to the storage unit of the interface unit,
By setting the flag, the target M
Commanding the start of execution of each transfer program by a PU, and waiting until the target MPU resets the flag; reading and evaluating the execution result from the storage means of the interface unit in which the flag has been reset; An electronic circuit analysis device characterized by the following. 2. A plurality of computers are connected via a network, at least one of the plurality of computers is a remote machine, and other computers except the remote machine are local machines. By connecting the communication unit of the electronic circuit to be analyzed, allocating storage means of the local machine to a virtual drive of the remote machine, and accessing each local machine from the remote machine, to analyze the operation of the electronic circuit. An electronic circuit analysis device characterized by remote control. 3. The electronic circuit analyzer according to claim 2, wherein said local machine includes said interface unit, said system bus, and said control means.