JPH0981412A - Electronic circuit analyzing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new device which can be applied to the operating analyses of plural electronic circuits or the operating analysis of an electronic circuit on which plural MPU are mounted. SOLUTION: This device is provided with n interface parts 4 and 5 having storage means storing programs to be executed in a target MPU, various kinds of data and the execution results of the target MPU so that they may be updated, at least (n) connection parts 3 to be connected with the interface parts 4 and 5, a mapping means 1 recognizing the (n) interface parts 4 and 5 via each connection part 3 and assigning the storage means 4b and 5b of each interface part 4 and 5 to an address map, and a control means 1 transferring the programs and data to the storage means 4b and 5b of each interface part 4 and 5 in accordance with an address map, commanding the execution starting of each transfer program by the target MPU, reading the execution results stored in the storage means 4b and 5b of each interface part 4 and 5 and evaluating the results.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation analyzing apparatus for an electronic circuit equipped with a microprocessor (MPU), and more specifically to an operation analysis of a plurality of electronic circuits or one electronic circuit equipped with a plurality of MPUs. The present invention relates to a novel device that can be applied to the motion analysis of the. In recent years, highly functional electronic devices equipped with MPUs have been manufactured in various fields. This is because it is possible to easily modify the system or change the function by simply replacing the ROM (read only memory) in which the software is written, and it is possible to develop an extremely flexible system. By the way, in such an electronic circuit, it is very difficult to debug hardware and software because of its high function, and some sort of debugging support device is indispensable.

[0002]

2. Description of the Related Art As a support device of this type, conventionally,
Electronic circuit to be debugged (hereinafter referred to as "target")
There are known in-circuit emulators (hereinafter referred to as "ICEs") that execute the above in a pseudo manner, ROM in-circuit debuggers, and the like. For example, ICE is M on the target side.
Operate MPU on ICE side instead of PU
Tracking the operation contents of U one by one with emulator software
By monitoring, the operating state of the target is comprehensively determined.

[0003]

However, in such a conventional assisting device, since the target-side MPU and the assisting-device-side MPU have a one-to-one correspondence, for example, a plurality of targets (electronic circuits ) Motion analysis simultaneously
When performing in parallel, the same number of support devices as the targets are required, or even if one target has a plurality of MPUs (multi-MPUs), all the MPUs are installed. However, there is a problem in that it is not possible to perform a motion analysis for.

Therefore, an object of the present invention is to provide a novel apparatus applicable to the operation analysis of a plurality of electronic circuits or the operation analysis of a single electronic circuit having a plurality of MPUs.

[0005]

The present invention is directed to a target M
A program executed by the PU, various data necessary for executing the program, and n interface units having a storage unit that can updateably store the execution result of the target MPU, and at least n connection units connected to the interface units. Mapping means for recognizing n interface parts via each connection part and allocating storage means of each interface part to an address map, and the program and the data in the storage means of each interface part according to the address map. And a control means for instructing the execution start of each transfer program by the target MPU, and for reading and evaluating the execution result stored in the storage means of each interface unit. To do.

According to this, by simply transferring a required program or data to the n interface units and instructing the execution start of the programs, the n target MPUs can be simultaneously operated through the n interface units. It can be operated in parallel, and each execution result can be read into the control means and evaluated and analyzed. Therefore, it is possible to analyze not only the operation of a plurality of electronic circuits but also the operation of a single electronic circuit equipped with a plurality of MPUs.

Alternatively, a plurality of computers are connected via a network, at least one computer of the plurality of computers is a remote machine, and other computers except the remote machine are local machines, and each computer operates. If each part of the electronic circuit to be analyzed is connected and each local machine is accessed from the remote machine to remotely control the operation analysis of the electronic circuit, the operation analysis is performed from a distant place. It is preferable because it is possible.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 are views showing an embodiment of an electronic circuit analyzing apparatus according to the present invention. First, the configuration will be described. In FIG. 1, 1 is a host computer (mapping means and control means), 2 is a system bus of the host computer, and 3 is an external slot (connection portion) connected to the system bus.

The host computer 1 comprises at least four elements of a digital computer (arithmetic unit, main memory unit, input / output unit and control unit), and is compatible with the architecture.
It is an S (operating system) that executes an arbitrary application program (personal computer, workstation, etc.). The application program of this embodiment is an "electronic circuit analysis program" that analyzes the operation of n electronic circuits or the operation of one electronic circuit equipped with n MPUs. However, n is 1 or an integer of 1 or more, but its maximum value is limited by the number of external slots 3 in terms of hardware.

The system bus 2 is a host computer 1
Is an internal bus connected to the CPU, and is composed of a plurality of address lines 2A, a plurality of data lines 2D and a plurality of control lines 2C, for example, an ISA bus, a PC
It is an I bus, a VL bus, a C bus, or the like. The number of lines is determined by the architecture of the host computer 1. In this embodiment, the system bus 2 is used, but this is because it is easy to use, and it does not prevent the use of buses other than the system bus.

The external slots 3 are expansion slots for mounting various option boards that utilize the system bus 2. In this embodiment, n external slots function as an interface with an electronic circuit to be analyzed. (For simplicity, n = 2) option boards (hereinafter referred to as “first board 4 and second board 5”) are mounted. The board generally refers to a printed circuit board whose size and connector are standardized, but is not limited to this in the present specification. Card type (typically PCMCI
A card).

The number of boards mounted is determined by the physical number of external slots 3. Since the number of slots limits the number of electronic circuits for operation analysis, and is also used for other purposes other than operation analysis (for example, additional memory boards),
It is desirable to make as many as possible. The first board 4
A first electronic circuit including a mode register 4a and an emulation ram (storage means) 4b, and a first cable 6 including a plurality of address lines 6A, a plurality of data lines 6D and a plurality of control lines 6C. Similarly, the second board 5 includes a mode register 5a and an emulation ram (storage means) 5b, a plurality of address lines 8A, and a plurality of data lines 8 in the same manner.
It is connected to the second electronic circuit 9 via the second cable 8 composed of D and a plurality of control lines 8C.

The emulation ram 4b (5b) is R
AM (random access memory), which is normally accessed from the host computer 1 via the system bus 2. However, while the "analysis mode flag" in the mode register 4a (5a) is set, the first Cable 6
Via the (second cable 8) the first electronic circuit 7 (second
It can be accessed from the electronic circuit 9).
The analysis mode flag is set by the host computer 1 and reset by the first electronic circuit 7 (second electronic circuit 9) that has completed the series of analysis sequences.

FIG. 2 is a memory map in the electronic circuit analysis apparatus of this embodiment. 10 is a memory map of the host computer 1 (hereinafter referred to as "host map"), 11 is a memory map of the first electronic circuit 7 (hereinafter "first map"), 12 is a memory map of the second electronic circuit 9. (Hereinafter, referred to as “second map”). Host map 10
Is a system user area 10a for an OS and an application program (electronic circuit analysis program),
The target areas 10b and 10c are divided into a plurality of target areas 10b and 10c, and the number of the target areas 10b and 10c corresponds to the number of boards (here, two) mounted in the external slot 3, and the size of each target area 10b and 10c. Corresponds to the capacity of the emulation ram 4b (5b). The first target area 10c is a mapping of the emulation ram 4a of the first board 4, and the second target area 10b is a mapping of the emulation ram 5b of the second board 5. In the figure, the size of each target area 10b, 10c (capacity of the emulation rams 4b, 5b) is set to 1 Mbyte for convenience. That is, although not particularly limited, 500000
1 Mbytes from (H) and 1 Mbytes from 600,000 (H) are assigned to each target area 10b, 10c.

On the other hand, the first map 11 and the second map 1
The structure of 2 depends on the architecture of the first and second electronic circuits 7, 9, but here the first electronic circuit 7
Target MPU of "8086", second electronic circuit 9
Assuming that the target MPU of “68000” is “68000”, the map structure shown in the figure is assumed. That is, the first map 11 has a dual port RAM area, a static RAM (S-RAM) area, and an EPROM area, and
The second map 12 has an EPROM area, an S-RAM area, and an I / O area, but is not limited to this.
The start address of the EPROM area of the first map 11 is the start address (F
FFF: 0 (H)), and the second map 12
The start address of the EPROM area of No. 2 matches the start address (0 (H)) of the 68000 type MPU.

FIG. 3 is a schematic flow of the electronic circuit analysis program. In this flow, the following processes are sequentially executed. That is, the first board 4 to which the first electronic circuit 7 is connected via the first cable 6 is mounted in the external slot 3, and the second electronic circuit 9 is connected via the second cable 8. After mounting the second board 5 in the external slot 3 and loading the OS and the electronic circuit analysis program in the main storage unit of the host computer 1, the electronic analysis program is executed, and then the second board 5 is first mounted in the external slot 3. The option board is recognized, and the boards for electronic circuit analysis (here, the first board 4 and the second board 5) are identified (step 20). Next, the emulation rams 4b and 5b of the identified first board 4 and second board 5 are mapped onto the host map 10 (see FIG. 2) without duplication (step 21), and the emulation rams of the first board 4 are mapped. The required program and data are transferred to 4b (step 22). Where the first board 4
The required programs and data to be transferred to the emulation ram 4b are a program executed by the target MPU of the first electronic circuit 7 and various data necessary for executing the program. After the required program and data are transferred, next, the "analysis mode flag" of the mode register 4a of the first board 4 is set (step 23) so that the emulation ram 4b can be accessed from the first electronic circuit 7. After that, the execution start of the transfer program is instructed to enter the standby state (step 24).

When entering the standby state, the target MPU of the first electronic circuit 7 executes the program transferred to the emulation ram 4b, writes the execution result into the emulation ram 4b, and terminates the program (normal end). Or abnormal termination), the mode register 4
The "analysis mode flag" of a is reset. In response to this reset, the electronic circuit analysis program releases the standby state, reads the execution result in the emulation ram 4b and analyzes it (step 25), then performs the following replacement, and repeats the above steps 22 to 25 ( The number of repetitions is the number of boards mounted).

First board 4 → second board 5 Mode register 4a → Mode register 5a Emulation memory 4a → Emulation memory 5b First electronic circuit 7 → Second electronic circuit 9 Thus, in this embodiment, Only by transferring a required program and data from the host computer 1 to the emulation memories 4b, 5b of the boards 4, 5, and instructing the execution start of the program, the operation analysis of the first and second electronic circuits 7, 9 is performed. Can be performed by the host computer 1, and the number of electronic circuits to be analyzed can easily be increased up to the maximum number (n) of boards to be mounted.
It is possible to realize a suitable device by using it for operation analysis of a plurality of electronic circuits.

In the flow of FIG. 3, the operation analysis of the second electronic circuit 9 is performed after the operation analysis of the first electronic circuit 7, but the invention is not limited to this. For example, after transferring the required programs and data to the emulation rams of all the boards and then instructing each electronic circuit to start executing the transfer program, each electronic circuit links and communicates with each other. In addition to being applicable to a system that operates while operating, it is also applicable to a so-called multi-MPU system in which a plurality of MPUs are mounted in one electronic circuit.

In the above embodiment, the operation analysis option boards (boards 4 and 5) are directly connected to the system bus 2 of the host computer 1, but this is an example of the configuration when used standalone. When used in a network environment, for example, it may be configured as follows. 4 to 8 are diagrams showing another embodiment of the electronic circuit analyzing apparatus according to the present invention, which is an example constructed in consideration of the network environment.

In FIG. 4, reference numeral 30 denotes a network such as a LAN or WAN, and a plurality of computers (three for convenience in the figure) computers 31 to 33 are connected to the network 30 via network boards 31a to 33a. Has been done. The network OSs of both the server and the client are installed in all the computers 31 to 33 to realize a so-called peer-to-peer type network environment. The "server" is a computer that provides its own hardware assets to other computers, and the "client" is a computer that uses the server assets. Generally, in a peer-to-peer type network OS, when a specific command is executed to load a server program into the main memory, that computer becomes a server machine, and when a client program is loaded, that computer becomes a client machine and both are loaded. Then, it becomes a server / client combined machine (the three computers 31 to 33 of this embodiment).
Operates as a server / client dual-purpose machine). In the following, for the sake of identification, the computer 31 on the left is the first computer, and the computer 32 on the upper right.
To the second computer and the computer 33 in the lower right to the third
Computer.

Communication boards 32b and 33b such as RS-232C are mounted on the second and third computers 32 and 33. Second and third computers 32, 33
Is the communication board 32b, 33b, cable 3
4, 35 and the communication boards 36a, 36b mounted on the electronic circuit 36 control the operation of the electronic circuit 36 and collect information on the operation result.

FIG. 5 shows the memory map 37 of the second computer 32 and the memory map 3 of the third computer 33.
8 and the drive map 3 of the first computer 31
FIG. Although not particularly limited, the memory map 37 of the second computer 32 includes a dual port RAM area 37a, an S-RAM area 37b, and an EPROM area 3
7c (when the target MPU mounted on the electronic circuit 36 is “8086”), the memory map 38 of the third computer 33 is the sampling area 38.
a, display data area 38b and I / O data area 38c
Consists of On the other hand, the drive map 39 is the local drive area 3 connected to the first computer 31.
1a and a remote drive area 31b virtually connected via the network 30. In particular, the remote drive area 31b is a first remote drive area 31c corresponding to the memory map 37 of the second computer 32. , Memory map 38 of the third computer 33
And a second remote drive area 31d corresponding to. The “drive” in the drive area may be an individual drive such as a floppy disk, a RAM disk, a hard disk, a partition area in the hard disk, or an individual drive or a directory in the partition.

FIG. 6 is an overall schematic flow in the configuration example of FIG. In this flow, first, the server OS and the client network OS are loaded on the first to third computers 31 to 33, respectively (step 40). The second and third computers 32 and 33 recognize the electronic circuits 36 connected to each other, exchange the basic information, and expand the data including the information of the electronic circuits 36 on the memory maps 37 and 38 (steps). 41). Next, the first computer 31 is operated as a client machine, the second and third computers 32 and 33 are accessed, and the respective memory maps 37 and 38 are set to the first.
The computer 31 is allocated to the first and second remote drive areas 31c and 32d (step 42). Next, the first and second remote drive areas 31c, 31
d ......... that is, the second and third computers 32,
The programs and various data necessary for the operation analysis of the electronic circuit 36 are transferred to the memory maps 37, 38 of the memory 33 (step 43), and the execution command of the transfer program is transferred from the first computer 31 to the second and the third. 3 to the computers 32 and 33 (step 44). The second and third computers 32 and 33 receive the execution command and execute the required operation analysis program to control the operation of the electronic circuit 36 and collect the operation result to collect the memory maps 37 and 38. Store in a predetermined area (step 4)
5). Then, the second and third computers 32, 33
Notifies the first computer 31 of the completion of execution of the operation analysis program, and the first computer 31 receives the notification and the first and second remote drive areas 31
Contents of c and 31d ... That is, contents of the memory maps 37 and 38 of the second and third computers 32 and 33.
Is evaluated or output to a printer or a display (step 46).

As described above, according to this embodiment, the second
And the memory map 3 of the third computer 32, 33
7 and 38 can be treated as the remote drive areas 31c and 31d of the first computer 31, for example, from the first computer 31 installed in a remote place,
The advantageous effect that the operation analysis of the electronic circuit 36 can be performed is obtained.

Alternatively, the first to third computers 31 to 3
Load a kind of remote control software in 3,
When the first computer is operated as a master and the second and third computers 32, 33 are operated as slaves, the keyboard and display of the first computer 31 are as if they were the keyboard and display of the second computer 32 or the third computer 33. Can be treated the same as. According to this, the master side (the first computer 3
For example, when a predetermined memory debug command (see FIG. 7) is typed into the display of 1), the same command is executed by the second computer 32 or the third computer 33 on the slave side, and the execution result (memory in this case) Since the dump list) is displayed on the display on the master side at the same time as the slave side (see FIG. 8), the computer on the master side (first computer 31) causes the computer on the slave side (second or third computer 3
2, 33) can be remotely controlled, and a remote debug environment can be easily constructed.

[0027]

According to the present invention, since it is configured as described above, it is possible to analyze not only the operation of a plurality of electronic circuits but also the operation of one electronic circuit equipped with a plurality of MPUs. Alternatively, the motion analysis can be performed from a remote location.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of one embodiment.

FIG. 2 is a memory map diagram of an example.

FIG. 3 is a schematic flowchart of one embodiment.

FIG. 4 is a schematic configuration diagram of another embodiment.

FIG. 5 is a memory map and drive map diagram of another embodiment.

FIG. 6 is a schematic flow chart of another embodiment.

FIG. 7 is a command input screen diagram of another embodiment.

FIG. 8 is an execution screen diagram of another embodiment.

[Explanation of symbols]

 1: Host computer (mapping means, control means) 3: External slot (connection part) 4: First board (interface part) 4b, 5b: Emulation ram (storage means) 5: Second board (interface part) 30 : Network 31: first computer (remote machine) 32: second computer (local machine) 33: third computer (local machine) 36: electronic circuit

Claims (2)

[Claims] 1. An n number of interface units having a storage unit for updatablely storing a program executed by the target MPU, various data necessary for executing the program, and an execution result of the target MPU, and the interface unit is connected. Recognize at least n connections and n interfaces through each connection,
Mapping means for allocating the storage means of each interface section to an address map, transferring the program and the data to the storage means of each interface section according to the address map, and instructing execution of each transfer program by the target MPU. And a control unit for reading and evaluating the execution result stored in the storage unit of each interface unit. 2. A plurality of computers are connected via a network, at least one computer of the plurality of computers is a remote machine, and other computers except the remote machine are local machines, which operate on each local machine. An electronic circuit analysis device, wherein each part of an electronic circuit to be analyzed is connected, and the local machine is accessed from the remote machine to remotely control the operation analysis of the electronic circuit.