JP2000010608A - Communication equipment, plc unit and display unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide communication equipment, a PLC unit and a display unit by which the load on a controller is reduced and data is effectively transferred to a display device. SOLUTION: An I/O (master) unit 10 directly writes data in a buffer RAM (buffer RAM (B)) 33 without using a control (CPU) unit 20, which data is only displayed on a display screen without any special change among data which are stored in the buffer RAM (buffer RAM (B)) being shared between the controller 100 and the display device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device, a PLC unit, and a display in a control device system having a communication device, a control device, and a display device.
Among the data shared between the control device and the display device, the data that is only displayed on the display screen without any particular change and is directly shared between the display device and the control device without passing through the control means. Communication device and PLC for reducing processing time and communication time in control device by writing to memory
Units and indicators.

[0002]

2. Description of the Related Art Conventionally, a control equipment system generally includes an execution unit such as an I / O or an actuator according to a control program in a unit called a control device, such as a PLC (programmable logic controller), a personal computer, and a microcomputer. control,
I have control.

[0003] In recent years, as the size of control devices has become larger and more sophisticated, the number of devices to be controlled has been increasing, and at the same time, their speed has also been required.

Therefore, the control which has been executed by one control device (control unit) is distributed to a plurality of control devices for each function, and these are connected by a network to reduce the load on each control device. In addition, there has been proposed a system capable of maintaining and improving high performance even when the number of devices to be controlled increases.

On the other hand, in the control system, the state of the control equipment,
A display device that confirms settings and the like and displays a message based on the state thereof to a control system, a control device designer, an operator, or the like has become indispensable.

[0006] Among them, for example, data of a control device which changes every moment, for example, generally called logging data, for example, a current temperature value of a temperature control unit, etc., is taken into a display device and displayed as a graph. Has also been done.

Here, a conventional display data fetching method will be described with reference to FIGS.

FIG. 13 is a flowchart showing a method of capturing display data in a communication device in a PLC system having a control device called a CPU unit.
When the processing is started (step 501), the communication device
It is checked whether there is a signal from a communication I / F circuit (corresponding to the communication I / F circuit 15 in FIG. 1) which interfaces with an external device (step 502). If there is (YES in step 502), the buffer RAM (the buffer RAM in FIG. 1) which is a shared memory between the communication device (I / O master unit) and the CPU unit
(A) (13), and writes the received data (step 503).

When the writing process is completed and when there is no signal from the communication I / F circuit (NO in step 502), another process is performed (step 5).
04), returning to the process of step 502;

In the system shown in FIG. 13, the communication device is a buffer R which is a shared memory with the CPU unit.
The data written in the AM (corresponding to the buffer RAM (A) 13 in FIG. 1) is transmitted by the CPU unit to the high-performance unit (shared memory between the CPU unit and the display) by the CPU unit after executing the user program in the CPU unit. Buffer R (corresponding to the advanced unit 30 in FIG. 1)
AM (corresponding to the buffer RAM (B) 33 in FIG. 1) is used for display. In this system, the display is connected to a high-function unit (corresponding to the high-function unit 30 in FIG. 1) and separately installed.

FIG. 14 shows a method of taking in display data in a stand-alone display unit in which a display unit and a control unit are integrally formed, connected to an I / O bus, and independently collect display data. In the functional block diagram shown in the figure, a control arithmetic unit 1 for controlling the entire apparatus, a display arithmetic unit 2 for controlling a display, a buffer RAM 3 serving as a shared memory of the control arithmetic unit 1 and the display arithmetic unit 2, a bus control Circuits 4 and 5 are provided.

The display data displayed on the display arithmetic unit 2 is buffered by the control arithmetic unit 1 controlling the bus control circuit 4 from the I / O bus via a communication unit (communication arithmetic unit). Take it into RAM3.

Thereafter, the control arithmetic unit 1 accesses the buffer RAM 3 via the bus control circuit 4, and the display arithmetic unit 2 also accesses the buffer RA via the bus control circuit 5.
Access to the shared memory of the control arithmetic device 1 and the display arithmetic device 2 by accessing M3 is adjusted by notifying the buffer RAM busy signals 6 and 7 to each other.

[0014]

However, in the conventional control device and communication device, all of the data exchange with the communication device is performed by the control device, and all of the data exchange with the display device is performed by the control device. I do.

That is, in the system shown in FIG.
The data written in the buffer RAM (corresponding to the buffer RAM (A) 13 in FIG. 1), which is a shared memory with the CPU unit, by the communication device is transmitted to the CPU unit by the CPU unit after the user program of the CPU unit is executed.
Writing to the buffer RAM (corresponding to the buffer RAM (B) 33 of FIG. 1) of the high-function unit (corresponding to the high-function unit 30 of FIG. 1) which is a shared memory between the PU unit and the display, and using the display. To serve.

In the display shown in FIG. 14, the control arithmetic unit 1 for controlling the entire apparatus controls the bus control circuit 4 from the I / O bus via a communication unit (communication arithmetic unit). The display data is taken into the buffer RAM3.

However, in the above-described conventional configuration, since the amount of data displayed on the display device is increasing, the control devices are all involved in the exchange of data. The load on the arithmetic unit (CPU) is unnecessarily increased.

That is, even if the data is updated frequently, such as the above-mentioned logging data, the data of which the frequency of the control program is small is not related to the control device. (CPU)
There is a problem that there is much waste in the processing time, communication time, etc.

Accordingly, an object of the present invention is to provide a communication device, a PLC unit, and a display capable of effectively transferring data to a display device by reducing the load on the control device.

[0020]

In order to achieve the above object, the present invention is configured as described above.

That is, according to the first aspect of the present invention, in the communication device of the control device system connected to the network, the data acquired via the network is stored in the buffer memory, and the writing means is stored in the buffer memory. At least the data required by the display device of the control device system among the data is directly written into a memory accessible by the display device without involving the control device.

As described above, according to the first aspect of the present invention, the writing means displays at least data required by the display device of the control device system among the data stored in the buffer memory without passing through the control device. Write directly to memory accessible by the device.

In the communication device of the control device system to which the control device is directly connected, the data directly obtained from the control device is stored in the buffer memory, and the writing means is stored in the buffer memory. At least the data required by the display device of the control device system out of the obtained data is directly written into a memory accessible by the display device without involving the control device.

As described above, in the invention according to the second aspect, the writing means displays at least data required by the display device of the control device system among the data stored in the buffer memory without passing through the control device. Write directly to memory accessible by the device.

Further, according to the third aspect of the present invention, the first aspect
In the invention described in the second aspect, the data written by the writing means is data that has been considered so as not to be changed by the display device.

According to the fourth aspect of the present invention, the first aspect is provided.
In the invention described in (2), the writing means displays the data required by the display device of the control device system among the data stored in the buffer memory without involvement of the control device of the control device system. Write to memory accessible by the device.

According to the fifth aspect of the present invention, there is provided a communication unit for communicating with an external control device, a control unit for controlling the entire apparatus, and a display for outputting display data on the external control device to a display device. P having data output means.
In the LC unit, the communication means has a first shared memory which is a memory in which device data obtained from the control device is stored and which can be accessed together with the control means, and the display data output means has the display device and A second shared memory accessible by the control means, wherein the communication means determines whether or not the first shared memory has display data which is not changed by the display device; and the determination means If it is determined that there is display data that is not changed by the display device,
The display data is directly output to the second shared memory of the display data output means.

As described above, in the invention according to the fifth aspect, the judging means in the communication means judges whether there is display data which is not changed by the display device in the first shared memory, and the judging means judges whether the display data is not changed. When it is determined that there is display data that is not changed by the device, the display data is directly output to the second shared memory of the display data output unit without going through the control unit.

According to the present invention, a communication means for storing device data acquired from the controlled device by communicating with the controlled device in a buffer memory; a display device for displaying the device data; In a display device having a device control unit for controlling a device to be controlled, and a shared memory accessible by the display device and the device control unit, the communication unit may include, among data stored in the buffer memory, First means for checking whether there is data not changed by the display device, and determining that there is data not changed by the display device among data stored in the buffer memory by the first means. A second means for reading the corresponding data from the buffer memory and writing the data to the shared memory.

Thus, in the invention according to claim 6, the first means in the communication means checks whether there is data which is not changed by the display device among the data stored in the buffer memory, and The second means, when it is determined by the first means that there is data which is not accompanied by the change by the display device among the data stored in the buffer memory, the corresponding data is not passed through the device control unit. Read from the buffer memory and write to the shared memory.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A communication device according to the present invention,
One embodiment of an LC unit and a display will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a communication device according to the present invention, a PLC.
It is a block diagram showing one embodiment of a control equipment system constituted by applying a unit and a display.

Referring to FIG. 1, the control device system includes:
The control device 100 includes a control device 100 configured by connecting an I / O (master) unit 10, a control (CPU) unit 20, and a high-performance unit 30 via a CPU bus 40.

Here, the I / O (master) unit 10
The communication device according to the present invention comprises a communication operation device (1) 11 for integrally controlling the operation of the I / O (master) unit 10, and a communication operation device (1) 1
System ROM storing the control program etc.
12. A buffer RAM (buffer RA) for storing device data and the like of a device to be controlled by the control device 100 acquired by the I / O (master) unit 10 through communication.
M (A)) 13, a system bus I / F circuit 14 connected to the CPU bus 40, and a communication I / F connected to the I / O (slave) unit shown in FIG.
The circuit 15 is provided.

The control (CPU) unit 20 forms the center of the control device 100. The control arithmetic device 21 for overall controlling the operation of the control (CPU) unit 20, the control arithmetic device 21 ROM 22 storing a control program and the like, a user memory (UM) 23 storing a user program and the like, and an I / O memory (IO) storing input / output data of a device to be controlled.
M) 24, a work RAM 25 functioning as a work area of the control (CPU) unit 20, a CPU bus 40
And a system bus I / F circuit 26 connected to the system bus.

The high function unit 30 enables the transfer of display data and the like to a display device (not shown).
A communication arithmetic unit (2) 31 for integrally controlling the operation of the high function unit 30, a system ROM 32 storing a control program of the communication arithmetic unit (2) 31, and the like;
A buffer RAM (buffer R) that stores input / output data of a device to be controlled used in the control (CPU) unit 20 and shared data serving as display data of a display device.
AM (B)) 33, a system bus I / F circuit 34 connected to the CPU bus 40, and a communication I / F circuit connected to the display device.
An F circuit 35 is provided.

FIG. 2 is a block diagram showing details of an I / O (slave) unit connected to the I / O bus shown in FIG.

In FIG. 2, the I / O (slave) unit 60 includes a communication arithmetic unit (3) 61 for integrally controlling the operation of the I / O (slave) unit 60, and a communication arithmetic unit (3). A system ROM 62 in which a control program 61 is stored; a buffer RAM 6 in which device data of a control device (not shown) to be controlled is stored;
3, a communication I / F circuit 64 connected to the I / O bus 50,
Parallel I / O connected to the control device to be controlled
It comprises an I / F circuit 65.

By the way, in the control device system of this embodiment, the buffer RAM (buffer RAM (B)) 3 shared between the control device 100 and the display device.
3, the I / O (master) unit 10 directly controls the buffer RAM (buffer RAM (B) )) 33 so that the processing time and communication time in the control device can be greatly reduced.

FIG. 3 is a flowchart showing details of the processing of the I / O (master) unit (communication device) shown in FIG.

In FIG. 3, when this processing is started (step 201), the communication arithmetic unit (1) 11 of the I / O (master) unit 10 firstly sets the communication I / F circuit 1
It is checked from step 5 whether there is a signal (step 202). Here, when it is determined that a signal is present from communication I / F circuit 15 (YES in step 202), buffer RAM (buffer R) which is a shared memory of I / O (master) unit 10 is used.
AM (A)) 13 to write data (step 20).
3) Go to step 204.

If it is determined in step 202 that there is no signal from the communication I / F circuit 15 (NO in step 202), the flow directly proceeds to step 204.

In step 204, the high function unit 30
RAM (buffer RAM) which is a shared memory of
(B)) Check 33 data. Then, it is checked whether or not there is data in the buffer RAM (buffer RAM (B)) 33 only for the monitor that does not change the contents of the I / O (step 205).

Here, the buffer RAM (buffer RAM)
(B) If it is determined that there is data only for the monitor that does not change the contents of I / O in 33 (step 2)
05 and YES), the corresponding data is I / O (master)
It is read from a buffer RAM (buffer RAM (A)) 13 which is a shared memory of the unit 10, and the read data is written to a buffer RAM (buffer RAM (B)) 33 which is a shared memory of the high function unit 30 (step 206). . Thereafter, another process is executed (step 207), and the process returns to step 202.

In step 205, the buffer RAM
If it is determined that there is no data in the (buffer RAM (B)) 33 only for the monitor that does not change the contents of the I / O (NO in step 205), another process is executed as it is (step 207). ), And return to step 202.

In the flowchart shown in FIG. 3, in step 205, the buffer RAM (buffer R
It has been determined whether or not there is data only for the monitor that does not change the I / O contents in the AM (B) 33. However, the determination may be omitted.

FIG. 4 is a flowchart showing a processing procedure in the case of such a configuration.

That is, in FIG. 4, when this processing is started (step 211), the communication arithmetic unit (1) 11 of the I / O (master) unit 10 firstly sets the communication I / O
It is checked whether there is a signal from the F circuit 15 (step 21).
2). If it is determined that a signal is present from communication I / F circuit 15 (YES in step 212), buffer RAM serving as a shared memory of I / O (master) unit 10
(Buffer RAM (A)) 13 to write data (step 213), and then proceed to step 214.

If it is determined in step 212 that there is no signal from the communication I / F circuit 15 (NO in step 212), the flow directly proceeds to step 214.

In step 214, the high-performance unit 30
RAM (buffer RAM) which is a shared memory of
(B)) Check 33 data. Then, the corresponding data is read from a buffer RAM (buffer RAM (A)) 13 which is a shared memory of the I / O (master) unit 10, and the read data is read from the high-performance unit 3.
Buffer RAM (buffer RAM)
(B)) 33 is written (step 215). afterwards,
Other processing is executed (step 216), and step 212 is executed.
Return to

In the control device system shown in FIG. 1, the display device is constructed separately from the control device 10.
This can be integrally formed.

FIG. 5 shows a communication device according to the present invention, a PLC.
It is a block diagram showing a 2nd embodiment of a control equipment system constituted by applying a unit and a display.

In FIG. 5, parts that perform the same functions as those shown in FIG. 1 are given the same reference numerals as those used in FIG. 1 for convenience of explanation.

In the control device system of the embodiment shown in FIG. 5, the display device is formed integrally with the control device.

That is, in FIG. 5, the I / O bus 50
Includes an I / O (master) unit 10 and a control (CPU)
A control device 100 including a unit 20 and a high-performance unit 30, an I / O (slave) unit 60, and a display 70 are connected.

Here, the I / O constituting the control device 100
The (master) unit 10 collects input data about the control device from the I / O (slave) unit 60 by communicating with the I / O (slave) unit 60, and sends the input data to the I / O (slave) unit 60. In this embodiment, unlike the embodiment shown in FIG. 1, data for the display is not directly transmitted to the high-functional unit 30. .

It should be noted that the control (C
The configuration of the PU) unit 20 and the advanced unit 30 is the same as the configuration of the control (CPU) unit 20 and the advanced unit 30 shown in FIG.

The configuration of the I / O (slave) unit 60 is the same as that of the I / O (slave) unit 60 shown in FIG.

On the other hand, the display 70 is a stand-alone display as shown in FIG. 14 in which the display device is integrally formed with the control device. In this embodiment, the communication I / F connected to the I / O bus 50 is used. The circuit 71 includes a buffer RAM (buffer RAM) for storing device data and the like of a device to be controlled by the control device 100 acquired by the display 70 through communication.
(A)) 72, a communication operation device 73 for controlling the communication operation of the display 70, a display operation device 74 for controlling the display operation of the display 70, and a control device for controlling the entire operation of the display 70. Arithmetic unit 75, bus control circuits 76, 77,
79, a buffer RAM (buffer RA) that stores input / output data of a control target device used in the control arithmetic device 75 and shared data serving as display data of the display device.
M (B)) 78, a display memory 80 for storing display data of the display 81, a display 81 for displaying data of a control device, such as logging data, which changes every moment, a control device to be controlled. Parallel I / O-I / F connected to
A circuit 82 is provided.

Here, the communication arithmetic unit 73, the buffer R
AM (buffer RAM (A)) 72, parallel I / O-
An I / F circuit 82 is connected via a CPU bus 87a,
The communication arithmetic unit 73, the control arithmetic unit 75, and the display arithmetic unit 74 are connected by buffer RAM busy signal transmission lines (83, 84, 85, 86), respectively. C between control circuit 77
The display arithmetic unit 7 is connected via the PU bus 87b.
4. Bus control circuit 79, display unit memory 80, display unit 81
Are connected via the CPU bus 87c.

By the way, the display 70 shown in FIG. 5 is characterized in that a communication arithmetic unit 73 is provided, and a part of the received data is transmitted directly from the communication arithmetic unit 73 to the display arithmetic unit 74. That is, the load on the arithmetic unit 75 is reduced, and the processing speed in the display 70 is increased.

Therefore, a buffer RAM busy signal (buffer RAM use permission signal) 84 is transmitted from the communication arithmetic unit 73 to the control arithmetic unit 75, and the control arithmetic unit 75 sends a signal to the communication arithmetic unit 73. Buffer RA
The M busy signal 83 is returned.

The communication arithmetic unit 73 transmits a buffer RAM in-use signal (buffer RAM use permission signal) 86 to the display arithmetic unit 74, and the display arithmetic unit 74 sends a signal to the communication arithmetic unit 73. The buffer RAM busy signal 85 is returned.

The communication arithmetic unit 73 and the buffer RA
M (buffer RAM (A)) 72, communication I / F circuit 71
(I / O (master) unit 1 shown in FIG. 1)
0, and the portion including the control arithmetic unit 75 corresponds to the control (CPU) unit 20 shown in FIG.
AM (buffer RAM (B)) 78, bus control circuit 7
The portion including 6, 77, 79 corresponds to the high-functional unit 30 shown in FIG. A portion including the display operation device 74, the display unit memory 80, and the display unit 81 corresponds to the display device in FIG.

FIGS. 6 and 7 are flowcharts showing the details of the processing of the communication operation device (communication device) shown in FIG.

In FIG. 6, when this processing is started (step 301), a buffer RAM (buffer RAM (B)) 78 as a shared memory is sent from the control arithmetic unit 75.
Check if there is a request for access to
02).

If it is determined that there is a request for access to the buffer RAM (buffer RAM (B)) 78 from the control arithmetic unit 75 (Y in step 302).
ES), buffer RAM (buffer RAM (A)) 72
The I / O data is read from the CPU, and the read data is written to the buffer RAM (buffer RAM (B)) 78 (step 303). Then, the control arithmetic unit 75
The access to the buffer RAM (buffer RAM (B)) 78 is permitted (step 304).

Next, from the control arithmetic unit 75 to the buffer R
It is checked whether there is a signal indicating that access to the AM (buffer RAM (B)) 78 has been completed (step 305). Here, a buffer RAM (buffer RAM)
(B)) When it is determined that there is no signal indicating that access to 78 has been completed (NO in step 305), another process is executed (step 306), and the process returns to step 305. Buffer RAM from device 75
If it is determined that there is a signal indicating that access to (buffer RAM (B)) 78 has been completed (YES in step 305), the flow advances to step 307.

In step 302, the buffer RAM (buffer RAM (B)) 78 is sent from the control arithmetic unit 75.
If it is determined that there is no request for access to (NO in step 302), the process directly proceeds to step 307.

In step 307, the display arithmetic unit 74
Is allowed to access the buffer RAM (buffer RAM (B)) 78, and the type of I / O data required as the display operation device 74 (display device) is written into the buffer RAM (buffer RAM (B)) 78. .

Then, a buffer RAM (buffer RAM)
(B)) Check the contents of 78 (step 308),
Proceed to step 309 in FIG.

In FIG. 7, in step 309, I / O is stored in a buffer RAM (buffer RAM (B)) 78.
Check whether there is data for only the monitor that does not change the contents of. Here, the buffer RAM (buffer RAM)
(B) If it is determined that there is data only for the monitor which does not change the contents of I / O in 78 (step 3)
09, YES), the corresponding data is read from the buffer RAM (buffer RAM (A)) 72, and the read data is read from the buffer RAM (buffer RAM (B)) 7
8 (step 310).

Then, the buffer R is stored in the display operation device 74.
Access to the AM (buffer RAM (B)) 78 is permitted (step 311).

Next, the buffer R
It is checked whether there is a signal indicating that access to the AM (buffer RAM (B)) 78 has been completed (step 312). Here, a buffer RAM (buffer RAM)
(B)) If it is determined that there is no signal indicating that access to 78 has been completed (NO in step 312), another process is executed (step 313), and the process returns to step 312. Buffer RAM from device 74
If it is determined that there is a signal indicating that access to (buffer RAM (B)) 78 has been completed (YES in step 312), another process is executed (step 314), and step 3 in FIG.
Return to 02.

In step 309, the buffer RAM
If it is determined that there is no data in the (buffer RAM (B)) 78 for the monitor that does not change the I / O contents (NO in step 309), another process is executed as it is (step 314). ), Returning to step 302 in FIG.

In the flowchart shown in FIG. 7, in step 309, the buffer RAM (buffer R
It is determined whether or not there is only data of the monitor that does not change the contents of the I / O in the AM (B) 78. However, as in FIG. 4, the determination may be omitted. .

The processing procedure in this case is shown in FIGS. 8 and 9. However, the processing procedure is different from that shown in FIGS. 6 and 7 in that the processing in step 309 in FIG. 7 is 309A in FIG. 9, and the processing in step 309a is A process of checking data in a buffer RAM (buffer RAM (B)) 78 as a shared memory is performed.

Next, a third embodiment of the present invention will be described with reference to FIG. Note that the same members as those used in the description of FIG. The feature of this embodiment is that the control arithmetic unit 75 in the configuration of FIG.
Is deleted, and the operation of the control arithmetic unit 75 is
Is a control (CPU) unit 20 that configures

That is, first, the configuration will be described.
The bus 50 is connected to a control device 100 including an I / O (master) unit 10, a control (CPU) unit 20, and an advanced unit 30, an I / O (slave) unit 60, and a display 90. .

Here, the I / O constituting the control device 100
The (master) unit 10 collects input data about the control device from the I / O (slave) unit 60 by communicating with the I / O (slave) unit 60, and sends the input data to the I / O (slave) unit 60. In this embodiment, as in the embodiment shown in FIG. 5, data for the display is not directly transmitted to the high-functional unit 30 in this embodiment. .

Next, the control (CPU) unit 20 controls the entire control device 100. As described above, in the present embodiment, the display unit 90 is further controlled.

The configuration of the advanced unit 30 is the same as the configuration of the advanced unit 30 shown in FIG.

The configuration of the I / O (slave) unit 60 is the same as that of the I / O (slave) unit 60 shown in FIG.

On the other hand, the display device 90 is a stand-alone display device as shown in FIG. 14 in which the display device is integrally formed with the control device (the communication operation device 73 and the display operation device 74). A communication I / F circuit 71 connected to the I / O bus 50; a buffer RAM (buffer RAM (A)) for storing device data and the like of a device to be controlled by the control device 100 acquired by the display 90 through communication; )
72, a communication arithmetic unit 73 for overall control of the communication operation of the display 90, a display arithmetic unit 74 for overall control of the display operation of the display 90, bus control circuits 76 and 79, and the control device 10.
Buffer RAM (buffer RAM (B)) 78 for storing input / output data of a device to be controlled used in the control (CPU) unit 20 and shared data serving as display data of the display device, and display on the display unit 81 A display unit memory 80 in which data is stored; a display unit 81 in which data of a control device, such as logging data, which changes every moment, is displayed;
Parallel I / O connected to the control device to be controlled
It comprises an I / F circuit 82.

Here, the communication arithmetic unit 73 and the buffer R
AM (buffer RAM (A)) 72, parallel I / O-
An I / F circuit 82 is connected via a CPU bus 87a,
The communication arithmetic unit 73 and the display arithmetic unit 74 are connected by transmission lines (85, 86) of the buffer RAM busy signal, and the display arithmetic unit 74, the bus control circuit 79, the display unit memory 80, the display unit 81 is connected via a CPU bus 87c.

By the way, the display 90 shown in FIG. 10 is characterized in that a computing unit 73 for communication is provided, and a part of the received data is transmitted directly from the computing unit 73 for communication to the computing unit 74 for display. That is, the load on the control (CPU) unit 20 of the apparatus 100 is reduced, and the processing speed in the display 70 is increased.

Therefore, a buffer RAM busy signal (buffer RAM use permission signal) 86 is transmitted from the communication operation device 74 to the display operation device 74, and the display operation device 74 transmits the signal to the communication operation device 73. Buffer RA
The M busy signal 85 is returned.

The communication arithmetic unit 73 and the buffer RA
M (buffer RAM (A)) 72, communication I / F circuit 71
(I / O (master) unit 1 shown in FIG. 1)
0, buffer RAM (buffer RAM (B))
The portion including the bus control circuits 78 and 79 corresponds to the high function unit 30 shown in FIG. A portion including the display operation device 74, the display unit memory 80, and the display unit 81 corresponds to the display device in FIG.

FIGS. 11 and 12 are flowcharts showing the details of the processing of the communication operation device (communication device) shown in FIG.

In FIG. 11, when this processing is started (step 401), the control of the control device 100 (CPU)
It is checked whether there is a request from the unit 20 for access to the buffer RAM (buffer RAM (B)) 78, which is a shared memory (step 402).

If it is determined that there is a request from the control (CPU) unit 20 for access to the buffer RAM (buffer RAM (B)) 78 (step 4).
02, YES), buffer RAM (buffer RAM
(A)) I / O data is read from 72 and the read data is stored in a buffer RAM (buffer RAM).
(B)) 78 is written (step 403). And
The control (CPU) unit 20 is permitted to access the buffer RAM (buffer RAM (B)) 78 (step 404).

Next, it is checked whether there is a signal indicating that the access from the control (CPU) unit 20 to the buffer RAM (buffer RAM (B)) 78 has been completed (step 405). Here, the control (CPU) unit 20 sends the buffer RAM
If it is determined that there is no signal indicating that access to (buffer RAM (B)) 78 has been completed (NO in step 405), another process is executed (step 406), and the process returns to step 405. Control (CPU) unit 2
If it is determined from 0 that there is a signal indicating that access to the buffer RAM (buffer RAM (B)) 78 has been completed (step 4).
05, YES), and proceeds to step 407.

In step 402, control (CPU)
From the unit 20 to the buffer RAM (buffer RAM)
(B) If it is determined that there is no request for access to 78 (NO in step 402), the flow directly proceeds to step 407.

In step 407, the display arithmetic unit 74
Is allowed to access the buffer RAM (buffer RAM (B)) 78, and the type of I / O data required as the display operation device 74 (display device) is written into the buffer RAM (buffer RAM (B)) 78. .

The buffer RAM (buffer RAM)
(B)) Check the contents of 78 (step 308),
Proceed to step 409 in FIG.

In FIG. 12, in step 409, the I / O is stored in the buffer RAM (buffer RAM (B)) 78.
It is checked whether or not there is data only for the monitor that does not change the contents of O. Here, the buffer RAM (buffer RA
If it is determined that there is data only for the monitor that does not change the contents of the I / O in the M (B)) 78 (YES in step 409), the corresponding data is stored in the buffer RAM.
(Buffer RAM (A)) 72, and reads the read data into a buffer RAM (buffer RAM (A)).
(B)) 78 is written (step 410).

Then, the buffer R is stored in the display operation device 74.
Access to the AM (buffer RAM (B)) 78 is permitted (step 411).

Next, the buffer RA is stored in the display operation device 74.
It is checked whether there is a signal indicating that access to the M (buffer RAM (B)) 78 has been completed (step 412). Here, a buffer RAM (buffer RAM) is stored in the display operation device 74.
(B)) If it is determined that there is no signal indicating that access to 78 has been completed (NO in step 412), another process is executed (step 313), and the process returns to step 412. If it is determined that the device 74 has a signal indicating that access to the buffer RAM (buffer RAM (B)) 78 has been completed (YES in step 412), another process is executed (step 414), and step 40 in FIG. 11 is performed.
Return to 2.

In step 409, the buffer RAM
If it is determined that there is no data in the (buffer RAM (B)) 78 for the monitor that does not change the contents of the I / O (NO in step 409), another process is executed as it is (step 414). ), And return to step 402 of FIG.

In the flowchart shown in FIG. 12, it is determined in step 409 whether or not there is data in the buffer RAM (buffer RAM (B)) 78 only for the monitor that does not change the contents of the I / O. Although the judgment is made, this judgment may be omitted as in FIG.

In this case, the processing of step 409 in FIG.
M (B)) 78 is checked (FIG. 9)
The same as the processing in step 309A).

As described above, according to the present invention, among the data shared between the control device and the display device, the monitor data that is only displayed on the display screen without any particular change is directly transmitted without passing through the control device. Since the communication device is configured to write in the shared memory shared with the control device of the display device, the following effects can be obtained.

1) The load on the control device is reduced, and the control capability of the control device can be improved.

2) The speed of display of control system data can be increased.

That is, data acquired by the communication device is stored temporarily in a memory serving as a buffer between the control device and the control device.
Data necessary for the display device is transferred to a memory serving as a buffer between the control device and the display device.

However, according to the present invention, the display data which does not involve the control program can be used by the display device regardless of the convenience of the control device, ie, between the control programs. It is configured to write directly to the buffer memory between the devices, thereby eliminating unnecessary processing of the control device, and not only the processing performance of the control device, but also the display capacity is increased by updating the display data faster. Will be possible.

[0107] In the past, even if the communication system became faster,
Further, even if the communication between the distributed control devices becomes faster and the data exchange becomes faster, there is a loss before the data reaches the display device, and the high-speed communication cannot be fully utilized as the display device. In other words, data carried by high-speed communication is temporarily stored in a buffer between the communication device and the control device, that is, the time during which the data is buffered becomes longer, and there is a case where there is no point in increasing the speed of the communication system. But,
According to the present invention, this disadvantage can be solved.

3) It is possible to cope with the flow of opening.

In other words, the flow of open control systems that have been developed and provided by each manufacturer up to now have been started from the point of communication (open path). In other words, an open bus can be connected by an I / O bus for which a standard is determined in advance, even if the bus is not from the same manufacturer.

In the present invention, however, the open (I /
O) By eliminating waste in communication, control and display using the bus, for example, the effects of the above 1) and 2) can be obtained, so that even under the same condition of an open bus, The function can be effectively used.

[0111]

As described above, according to the first aspect of the present invention, in the communication device of the control device system connected by the network, the data acquired via the network is stored in the buffer memory, and the writing means is Since the data required by the display device of the control device system among the data stored in the buffer memory is written directly to a memory accessible by the display device without passing through the control device, the following effects are provided. Is obtained.

1) The load on the control device is reduced, and the control capability of the control device can be improved.

2) High-speed display of control system data can be achieved.

3) It is possible to cope with the flow of opening.

According to the second aspect of the present invention, in the communication device of the control device system to which the control device is directly connected, the data obtained directly from the control device is stored in the buffer memory, and the writing means is stored in the buffer memory. At least the data required by the display device of the control device system among the data obtained is written directly to a memory accessible by the display device without involving the control device, so that the following effects are obtained. Can be

1) The load on the control device is reduced, and the control capability of the control device can be improved.

2) High-speed display of control system data can be achieved.

According to the third aspect of the present invention, since the data written by the writing means is data that is not changed by the display device, the control device accesses the data later. However, the control device is not affected by the time lag.

In the invention according to claim 4, the writing means needs a display device of the control device system among the data stored in the buffer memory without involvement of the control device of the control device system. Is written in a memory accessible by the display device, so that efficient data transmission can be performed.

[0120] In the invention according to claim 5, the judging means in the communication means judges whether or not there is display data which is not changed by the display device in the first shared memory. If it is determined that there is display data that is not to be changed, the display data is transmitted to the second display data output means without using the control means.
Since the configuration is such that the data is directly output to the shared memory, the load on the control device is reduced, and the control capability of the control device can be improved.

According to the present invention, the first means in the communication means checks whether there is data which is not changed by the display device among the data stored in the buffer memory, and checks the second data. The means, if it is determined by the first means that there is data which is not changed by the display device among the data stored in the buffer memory, the corresponding data is stored in the buffer memory without going through a device control unit. Since the configuration is such that data is read from the memory and written to the shared memory, the load on the device control unit is reduced, and the control capability of the device control unit can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a control device system configured by applying a communication device, a PLC unit, and a display according to the present invention.

FIG. 2 shows an I / O connected to the I / O bus shown in FIG.
FIG. 3 is a block diagram showing details of a (slave) unit.

FIG. 3 is a flowchart showing details of processing of an I / O (master) unit (communication device) shown in FIG. 1;

FIG. 4 is a flowchart showing details of another process of the I / O (master) unit (communication device) shown in FIG. 1;

FIG. 5 is a block diagram showing another embodiment of a control device system configured by applying the communication device and method according to the present invention.

FIG. 6 is a flowchart showing details of processing of the communication arithmetic device (communication device) shown in FIG. 5;

FIG. 7 is a flowchart showing details of the processing of the communication arithmetic device (communication device) shown in FIG. 5;

FIG. 8 is a flowchart showing details of other processing of the communication arithmetic device (communication device) shown in FIG. 5;

FIG. 9 is a flowchart showing details of other processing of the communication arithmetic device (communication device) shown in FIG. 5;

FIG. 10 is a block diagram showing another embodiment of a control device system configured by applying the communication device and method according to the present invention.

11 is a communication arithmetic device (communication device) shown in FIG.
5 is a flowchart showing details of the processing of FIG.

FIG. 12 is a communication operation device (communication device) shown in FIG.
5 is a flowchart showing details of the processing of FIG.

FIG. 13 is a flowchart showing details of a display data transmission process in a conventional communication device.

FIG. 14 is a flowchart showing details of display data transmission processing in a conventional display device.

[Explanation of symbols]

Reference Signs List 10 I / O (master) unit 11 Communication operation device (1) 12 System ROM 13 Buffer RAM (buffer RAM (A)) 14 System bus I / F circuit 15 Communication I / F circuit 16 CPU bus 20 Control (CPU) Unit 21 Control arithmetic unit 22 System ROM 23 User memory (UM) 24 I / O memory (IOM) 25 Work RAM 26 System bus I / F circuit 27 CPU bus 30 High-performance unit 31 Communication arithmetic unit (2) 32 System ROM 33 Buffer RAM (Buffer RAM (B)) 34 System bus I / F circuit 35 Communication I / F circuit 40 CPU bus 50 I / O bus 60 I / O (slave) unit 61 Communication operation device (3) 62 System ROM 63 Buffer RAM 64 Communication I / F circuit 65 Para I / O-I / F circuit 70 Display 71 Communication I / F circuit 72 Buffer RAM (Buffer RAM (A)) 73 Communication operation device 74 Display operation device 75 Control operation device 76, 77, 79 Bus control Circuit 78 Buffer RAM (Buffer RAM (B)) 80 Display Memory 81 Display 82 Parallel I / O-I / F Circuit 83 Buffer RAM Busy Signal 84 Buffer RAM Busy Signal (Buffer RAM Use Permit Signal) 85 Buffer RAM Busy signal 86 Buffer RAM busy signal (buffer RAM use permission signal) 90 Display 100 Control device

Claims (6)

[Claims] 1. A communication device of a control device system connected via a network, comprising: a buffer memory for storing data acquired via the network; and at least one of the control device systems of the data stored in the buffer memory. A writing device for directly writing data required by the display device into a memory accessible by the display device without involving the control device. 2. A communication device for a control device system to which a control device is directly connected, wherein: a buffer memory for storing data directly obtained from the control device; and at least the control device system among data stored in the buffer memory. A writing unit for directly writing data required by the display device into a memory accessible by the display device without involving the control device. 3. The communication device according to claim 1, wherein the data written by the writing means is data that has been considered so as not to be changed by the display device. 4. The writing device according to claim 1, wherein the display device stores data required by the display device of the control device system among data stored in the buffer memory without involvement of the control device of the control device system. 3. The communication device according to claim 1, wherein the data is written in an accessible memory. 5. A PLC comprising: communication means for communicating with an external control device; control means for integrally controlling the entire device; and display data output means for outputting display data on the external control device to a display device. In the unit, the communication means has a first shared memory which is a memory for storing device data obtained from the control device and is accessible together with the control device, and the display data output means has the display device and the display device. A second shared memory accessible by a control unit, wherein the communication unit determines whether or not the first shared memory has display data that is not changed by the display device; When it is determined that there is display data that is not changed by the display device, the display data is output to the display data output unit. PLC unit and outputs to the shared memory directly. 6. A communication means for storing device data acquired from a controlled device by communicating with the controlled device in a buffer memory, a display device for displaying the device data, and a device control for controlling the controlled device. And a shared memory that can be accessed by the display device and the device control unit. The communication unit, wherein the data stored in the buffer memory is data that is not changed by the display device. The first to check if there is
Means, if it is determined by the first means that there is data that is not changed by the display device among the data stored in the buffer memory, read the corresponding data from the buffer memory, And a second means for writing to the shared memory.