JPH0512221A - Data exchange speeding up system between multi cpu - Google Patents

Abstract

PURPOSE:To speed up data exchange between CPU by providing a control part having a function which subordinetes memories respectively to plural CPU and which exchanges a part of the memories in different CPU by an input/ output instruction from CPU. CONSTITUTION:At the time of transmitting data from CUP 1 to CPU 2, CPU 1 gives the notice of the use start of a memory for inter-CPU data exchange 10 to a control part 13 and writes transmission information to CPU 2 into the exchange memory 10. CPU 1 gives the notice of use termination to the control part 13 after writing, and gives the command of switching the memory for inter-CPU data exchange between CPU 1 and CPU 2. The control part 13 checks whether CPU 2 is in the middle of using a memory for inter-CPU data exchange 11 or not by internal information. When it is not in the middle of use, the memories for inter-CPU data exchange 10 and 11 in CPU 1 and CPU 2 are immediately switched. Thus, a processing is speeded up since data transfer between a local memory and a common memory is not required.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-CPU data exchange speed-up system in a multi-CPU system having a plurality of CPUs.

[0002]

2. Description of the Related Art In a conventional multi-CPU system, as a data exchange means between a plurality of CPUs, there are a method using a local area network and a method using a shared memory which can be commonly read and written among a plurality of CPUs. An example of a conventional multi-CPU data exchange system is shown in FIG. 4 and explained. FIG. 4 shows an example in which a system having three CPUs is connected by a local area network. In FIG. 4, reference numerals 21, 22, 23 are CPUs, and the CPU 21,
The CPU 22 and the CPU 23 are the local memory 24 and the local memory 25 which can be read and written only by the respective CPUs.
And has a local memory 26. The three CPUs 21, 22, and 23 are connected by the local area network 27, and when exchanging data, information to which the address of the destination CPU is added from the CPU of the source is added to the local area network 27. And sends it out, and the CPU at the destination receives it.

FIG. 5 is a block diagram showing another example of a conventional multi-CPU data exchange system, showing a case where a shared memory is used. In FIG. 5, the same reference numerals as those in FIG. 4 indicate the corresponding parts, and 28 is the three CPUs 21,
It is a shared memory that can be commonly read and written by the CPU 22 and the CPU 23. Then, when data exchange between the CPUs is realized, the transmission source CPU writes information with the address of the transmission destination CPU added to the shared memory 28 and reads it from the transmission destination CPU.

[0004]

In the above-mentioned conventional multi-CPU data exchange method, when the former local area network is used, the speed of data transmission / reception cannot be increased due to the limitation of the data transfer speed of the local area network. There was a problem called. Even in the latter method using the shared memory, an extra time is required for the transmission source CPU to transfer the data from the local memory to the shared memory and an extra time for the transmission destination CPU to transfer the data from the shared memory to the local memory. There was a problem to do.

[0005]

In the multi-CPU data exchange accelerating method of the present invention, in a multi-CPU system having a plurality of CPUs, a memory subordinate to each CPU and an input / output instruction from the CPU are used for the above-mentioned operation. By mounting a control unit having a function of exchanging a part of the memory between different CPUs, the speed of data exchange between the CPUs is increased.

[0006]

In the present invention, the CP is controlled via the bus switching unit based on the program loaded in the memory of the control unit.
The switching of the memory for data exchange between U is realized.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of a high speed data exchange system between multiple CPUs according to the present invention. In FIG. 1, 1, 2, 3 are CPUs, 4, 5, 6 are memories (local memories) subordinate to the CPUs 1, 2, 3, respectively, and the local memories 4, 5, 6 are CPUs for reading and writing. Fixed CPU fixed memory 7,8,9
And memory for data exchange between CPUs 10, 11, and 12. A control unit 13 has a function of exchanging a part of the memory between different CPUs according to input / output instructions from the CPU. Here, the memory for data exchange between CPUs 10, 11,
The CPU 12 can change the CPU for reading and writing according to an instruction from the control unit 13. Further, in the control unit 13, each CPU 1, 2, 3 is C
Stores information on whether the memories 10, 11, 12 for data exchange between PUs are in use. The CPUs 1, 2, and 3 and the control unit 13 exchange information by input / output commands. As described above, the multi-CPU data speedup method of the present invention includes the memories 4, 5, and 6 which are subordinate to the CPUs 1, 2, and 3, and C, respectively.
By mounting a control unit 13 having a function of exchanging a part of the memories 4 to 6 between different CPUs according to input / output instructions from the PUs 1 to 3, it is configured to speed up data exchange between the CPUs. ..

FIG. 2 is an explanatory diagram showing the flow of control in the embodiment shown in FIG.

Next, the operation of the embodiment shown in FIG.
2 to CPU 2 will be described as an example with reference to FIG. The CPU 1 first sends a CP to the control unit 13.
The start of use of the U-to-U data exchange memory 10 is notified. After that, the CPU 1 stores C in the memory 10 for exchanging data between CPUs.
Write the transmission information for PU2, and after writing,
The control unit 13 is notified of the end of use. Finally, C
The PU 1 issues a memory switching instruction for data exchange between the CPU 1 and the CPU 2 to the control unit 13.

Next, in the control unit 13, the CPU 2 makes the CP
It is checked by internal information whether the memory 11 for data exchange between CPUs of U2 is in use, and if it is not in use,
Immediately, the data exchange memories 10 and 11 between the CPU 1 and the CPU 2 are switched. Then, when it is in use, the switching is postponed until the use end notification is received from the CPU 2. Here, the postponement of this switching is usually
Since this is a rare event, it hardly affects the processing time. After the switching is completed, the control unit 13 notifies the CPU 2 that the switching has occurred by an interrupt. Further, in the data exchange between the CPUs of this embodiment, the data transfer by the local area network is not required, and the data transfer time between the local memory and the shared memory is not required, so that the processing becomes faster.

FIG. 3 is a block diagram showing a configuration example of the control unit 13 in FIG. The control unit 13 is the CPU 1 of the control unit.
3-1 and memory 13-2 of control unit and peripheral LSI 13
3 is a control device including a memory of the control unit 13-2.
Bus switching unit 1 based on the program installed in
Memory for data exchange between CPUs 1 and 3 via 3-4
Switching between 1 and 12 is realized.

[0012]

As described above, according to the present invention, each C
The bus switching unit includes a memory subordinate to the PU and a control unit having a function of exchanging a part of the memory between different CPUs according to an input / output instruction from the CPU, and based on a program installed in the memory of the control unit. Since the switching of the memory for data exchange between CPUs is realized via
This has the effect of speeding up data exchange between PUs.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a method for accelerating data exchange between multiple CPUs according to the present invention.

FIG. 2 is an explanatory diagram showing a control flow in the embodiment shown in FIG.

FIG. 3 is a block diagram showing a configuration example of a control unit in FIG.

FIG. 4 is a block diagram showing an example of a conventional multi-CPU data exchange system.

FIG. 5 is a block diagram showing another example of a conventional multi-CPU data exchange system.

[Explanation of symbols]

 1-3 CPU 4-6 Local memory (memory) 7-9 CPU fixed memory 10-12 CPU data exchange memory 13 Control unit

Claims (1)

Claim: What is claimed is: 1. In a multi-CPU system having a plurality of CPUs, a memory subordinate to each CPU and a part of the memory are exchanged between different CPUs according to an input / output instruction from the CPU. A high-speed data exchange method between multiple CPUs, which is characterized by accelerating data exchange between CPUs by mounting a control unit having functions.