JPS5866102A - Sequence controller - Google Patents
Sequence controllerInfo
- Publication number
- JPS5866102A JPS5866102A JP16471481A JP16471481A JPS5866102A JP S5866102 A JPS5866102 A JP S5866102A JP 16471481 A JP16471481 A JP 16471481A JP 16471481 A JP16471481 A JP 16471481A JP S5866102 A JPS5866102 A JP S5866102A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- output
- data
- error
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002950 deficient Effects 0.000 abstract 2
- 230000002159 abnormal effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
Abstract
PURPOSE:To recover easily a data destruction part of a memory, by making the writable and readable memory dual to prevent the stop of the control function and the discontinuity of the control due to data destruction of the memory. CONSTITUTION:Data outputted to memory output lines 13 and 14 are sent to parity checkers 4 and 3; and if the parity is abnormal, an error signal is outputted to an error output signal line 15 or 16. An output line 17 is turned on when the output of a memory 1 is defective, and an output line 18 is turned on when the output of a memory 2 is defective, and one of outputs of memory output lines 13 and 14 which has no parity error is outputted to a data output line 19. In case that the memory where the parity error occurs is recovered, outputs of error output lines 15 and 16 are inputted to an OR gate 8, and a CPU is interrupted through an interrupt line 20, and data obtained on the data output line 19 from the CPU is written in the memory again.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16471481A JPS5866102A (en) | 1981-10-15 | 1981-10-15 | Sequence controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16471481A JPS5866102A (en) | 1981-10-15 | 1981-10-15 | Sequence controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5866102A true JPS5866102A (en) | 1983-04-20 |
Family
ID=15798484
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16471481A Pending JPS5866102A (en) | 1981-10-15 | 1981-10-15 | Sequence controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5866102A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61183702A (en) * | 1985-02-08 | 1986-08-16 | Sony Corp | Electronic equipment |
JPS61199104A (en) * | 1985-03-01 | 1986-09-03 | Hitachi Ltd | Memory multiplexing control system |
JPS62163103A (en) * | 1986-01-14 | 1987-07-18 | Omron Tateisi Electronics Co | Process controller |
-
1981
- 1981-10-15 JP JP16471481A patent/JPS5866102A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61183702A (en) * | 1985-02-08 | 1986-08-16 | Sony Corp | Electronic equipment |
JPS61199104A (en) * | 1985-03-01 | 1986-09-03 | Hitachi Ltd | Memory multiplexing control system |
JPS62163103A (en) * | 1986-01-14 | 1987-07-18 | Omron Tateisi Electronics Co | Process controller |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5866102A (en) | Sequence controller | |
JPS55157022A (en) | Output circuit for microcomputer | |
JPS5413236A (en) | Bus control system | |
JPS56143599A (en) | Check system for fault of p-rom | |
JPS62274355A (en) | Memory error processing system | |
JPS58103040A (en) | Microprogram controller | |
JPS56118153A (en) | Digital input circuit | |
JPS5693196A (en) | Error detecting system of checking circuit | |
JPS6246358A (en) | Error processing system | |
JPS52103933A (en) | Trouble-shooter of redundancy logic circuit | |
JPS6027070A (en) | Vector processor | |
JPS5585928A (en) | Bus duplex system for clock signal | |
JPS5731020A (en) | Channel controller | |
JPS60258663A (en) | Memory error processing circuit | |
JPS58129656A (en) | Controlling system for microprogram | |
JPS6095664A (en) | Data storage control device | |
JPS61224044A (en) | Error check circuit | |
JPS6232544A (en) | Abnormally detecting circuit for information processor | |
JPH02253343A (en) | Output protecting device | |
JPH03189831A (en) | Inter-system information control system | |
JPS5642862A (en) | Fault detecting system for electronic computer | |
JPS58117056A (en) | Parity check system | |
JPS59132050A (en) | Erroneous output preventing circuit of microcomputer system or the like | |
JPS5936396A (en) | Memory controller | |
JPS60116042A (en) | 1 bit error correction write system |