JPS608962A - Temporary fault detecting system of storage information - Google Patents

Abstract

PURPOSE:To improve a processing capability of a central control device by executing an existing stand-by switching processing, only in case an error caused by an element fault of a main storage device in a duplex main storage device has been detected. CONSTITUTION:With regard to an information read out of the same address (a) of a main storage device MM0, when an error is detected continuously by a parity checking circuit PC, an element fault detecting signal e2 is transferred to a central control device CC0. The central control device CC0 which has received said signal executes first a switching processing by which a main storage control device MMC1 and a main storage device MM1 become existing, and a main storage control device MMC0 and a main storage device MM0 become stand-by. As a result, it becomes unnecessary that the central control device CC0 executes the switching processing in the event of a temporary fault of the main storage device MM0.

Description

DETAILED DESCRIPTION OF THE INVENTION (al) Technical Field of the Invention The present invention relates to an information processing system equipped with a duplicated main memory, and particularly to a memory that minimizes the frequency of switching between the active and spare main memory of the duplicated main memory. Information regarding temporary failure detection method.

fbl Technical Background FIG. 1 is a diagram showing an example of an information processing system to which the present invention is applied. In FIG. 1, the information processing system includes dual central control units CCO and CC1,
It includes main memory control units MMCO and MMCI, and main memory units MMO and MMl. The central control unit (for example, CC0) currently operating is connected to the main memory control word MM via the main memory control word MMCO and MMCI.
The same information is written to the same address of O and MMI, the information is read from the current main memory (for example, MMO), and required processing is performed. When the active main criminal equipment E, MMO is affected, the backup main memory device MMI is switched to the active main storage device MMI and processing continues. An error detection code such as a parity bit is added to the information stored in each main memory controller MMCO and MMCI.
perform error checking on information read from the corresponding main memories MMO and MMI, respectively. The main culprit 1. a
Errors detected by the control devices MMCO and MMCI include:
There are two types of failures: one is due to an element failure in the main memory devices MMO and MMI, and the other is a temporary cause such as the influence of alpha rays. In the former case, the main memories MMO and MMI
However, in the latter case, the device can be used again by writing new information.

(c) Prior Art and Problems In conventional information processing systems of this type, when the current main memory controller (for example, MMCO) detects an error in the information read from the current main memory (for example, MMO), the central Since the control units CCO and CCI execute the current/standby switching process for the main memory control units MMCO and MMC1 and the main memory units MMO and MMI even in the case of a temporary failure as described above, in the same way as in the case of an element failure. This has the disadvantage that the switching process takes a lot of time and reduces the processing capacity of the central control unit CCO.

(d+ Purpose of the Invention The purpose of the present invention is to eliminate the drawbacks of conventional information processing systems as described above, and to improve the processing capacity of a central control unit by eliminating as much as possible the work/standby switching process.

(el) Structure of the Invention The object of the present invention is to provide an information processing system that includes a current main storage device and a backup main storage device, and checks for errors in information read from the current main storage device, in which information in which an error has been detected is stored. an address storage means for storing an address on the current main storage device that has been previously stored; and a collation means for collating the address stored this time by the address storage means with the address stored last time; If the matching means detects a match between the two addresses, the current main storage device and the backup main storage device are switched for use; This is achieved by the address storage means reading information from the same address as the address ↑a, writing it into the currently stored address on the current main storage device, and continuing to use it as the current main storage device.

ff) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a main memory control device according to an embodiment of the present invention, and FIG. 3 is a diagram showing a central control device according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures. Also, as in Figure 1, the 0 series is currently in use,
1 series will be reserved. In FIG. 2, in the initial state, both flip-flop FF registers REGO and IREGI are set to the reset state. Main memory controller MMC
The parity check circuit PC in O is the main memory MM.

When an error is detected in the information read from address a and an error detection signal e is output, flip-flop FF enters the cent state and energizes register REGO. As a result, register REGO stores address a transmitted from main memory control device MMCO to main memory device MMO. Verification circuit MA
T compares the stored contents of registers REGO and REGI, detects that they do not match, and outputs a check signal m of logical value O. As a result, gate G1 is set to a conductive state and gate G2 is set to a blocked state. On the other hand, error detection signal e
is temporarily passed through the delay circuit DL which has a delay time sufficient for the verification circuit MAT to set the logic value of the verification signal m based on the verification result by the delay circuit DL, and then through the gate 1-GO and the gate G1. The fault detection signal e1 is transmitted to the central control unit CCO. In FIG. 3, a temporary failure detection signal e1 transmitted from the main memory controller MMCO
is transmitted to special microaddress generation circuit MAS and microaddress control circuit CTL. The special microaddress generation circuit MAS transmits the start address of the copy microprogram MPI stored in the control memory CM to the sequencer SEQ. As a result, sequencer S
EQ is the copy microprogram M from the control memory CM.
The microinstructions constituting the PI are sequentially read out and stored in the microinstruction register CMIR. Central control unit CCO
For example, by executing each microinstruction of the copy microprogram MPI stored in the microinstruction register CMI'R, information is read from the same address a of the main memory device MMI via the main memory control device MMCI, and After causing the main memory control device MMCO to write the information successively received from the main memory device MMl to the corresponding address a of the main memory device MMO, the main memory control device MMCO and the main memory device MMO are continued to be used as the active system. If the error detected by the parity check circuit pc is due to a temporary failure that occurred at address a of the main memory MMO, normal information can be restored to address a by writing the information read from the main memory MMI. stored and returned to the central control unit CC
When O reads information from the corresponding address a of the main memory MMO, the parity check circuit pc outputs an error detection signal e.
There is no output. On the other hand, if the error detected by the parity check circuit PC is due to an element failure that occurred at address a of the main memory MMO, even if the information read from the main memory MM1 is written, there will still be normal information at address a. is not stored and the central control unit CCO again reads information from the corresponding address a of the main memory MMO, the parity check circuit pc outputs the error detection signal e. As a result, flip-flop FF enters the reset state and energizes register REGI. Therefore register R
EG1 stores the address a transmitted from the main memory control device MMCO to the main memory device MMO. The collation circuit MAT collates the stored contents of the registers REGO and REGI, detects that they match, and outputs a collation signal m having a logic value of 1. As a result, the gate G2 is set to the channel state, and the gate G1 is set to the blocking state. On the other hand, the error detection signal e is the delay time F
After passing through the delay circuit DL having the delay time by IPfDL, it is transmitted to the central control unit CCO as an element failure detection signal e2 via the gate GO and the gate G2. In FIG. 3, the element failure detection signal e2 transmitted from the main memory controller MMCO sets the corresponding interrupt causing flip-flop SF by a known method. The interrupt microaddress generation circuit M/l executes an interrupt microprogram M stored in the control memory CM.
The start address of P2 is transmitted to the sequencer SEQ. As a result, the sequencer SEQ sequentially reads the microinstructions constituting the interrupt microprogram MP2 from the control memory CM and stores them in the microinstruction register CMIR.

The central control unit CCO has a microinstruction register CMIR.
By executing each microinstruction of the interrupt microprogram MP2 stored in the interrupt microprogram MP2, the required interrupt processing program is started, the main memory control unit MMC1 and the main memory unit MMI are made active, and the main memory control units MMCO and Execute the current/standby switching process using the main storage device MMO as the standby system.

As is clear from the above description, according to the present embodiment, the main memory control unit MMCO performs the following operations when consecutive pieces of information from the same address a of the main memory unit MMO are not detected as errors by the parity check circuit PC. Central control unit CCO
The temporary failure detection signal e1 is transmitted to the temporary failure detection signal e1.
1, the central control unit CCO temporarily reads information from the same address a of the main memory MMI, writes the information to the corresponding address a of the main memory MMO, and also writes the information to the corresponding address a of the main memory MMO. If the parity check circuit PC successively detects an error in the information that has been continuously received from a to
For the first time, the CO executes a switching process in which the main memory control device MMCI and the main memory device MMI are used as active, and the main memory control device MMCO and the main memory device MMO are used as backup. As a result, the central control unit CCO does not need to perform switching processing in the event of a temporary failure in the main memory unit MMO, and the load is reduced.

Note that FIGS. 2 and 3 are only one embodiment of the present invention; for example, the currently used system is not limited to the θ system;
Even in the case of 1 system, the effects of the present invention do not change. Furthermore, the configurations of the main memory control device and the central control device are not limited to those shown in the drawings, and many other modifications may be considered.
In either case, the effects of the present invention remain the same.

(gl) Effects of the Invention According to the present invention, in the information processing system, when the central control unit detects an error caused by a temporary failure of the main storage device, there is no need to execute the working/standby switching process; The working/standby switching process is executed only when an error caused by an element failure in the above 4.1 device is detected, which reduces the load and improves the processing capacity of the central control unit, that is, the information processing system.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of an information processing system to which the present invention is applied, FIG. 2 is a diagram showing a main memory control device according to an embodiment of the present invention, and FIG. 3 is a diagram showing a main memory control device according to an embodiment of the present invention. It is a figure showing a control device. In the figure, CCO and CC1 are the central controller, CM
is control memory, CMTR is microinstruction register, CT
L is a microaddress control circuit, DL is a delay circuit, e
is an error detection signal, el is a temporary failure detection signal, e2 is an element failure detection signal, FF is a flip-flop, Go to G2
is a gate, TR is an instruction register, TSF is an interrupt cause flip-flop, m is a verification signal, MAI is an interrupt microaddress generation circuit, MAS is a special microaddress generation circuit, MAT is a verification circuit, MMO and MMI are main memory devices , MMCO and MMCI are main memory controllers, MPI
is a copy microprogram, MB2 is an interrupt microprogram, PC is a parity check circuit, REGO and RE
GI stands for Regisf. 1 Mine 1 Figure ≠ 2 Note 2 Figure 3

Claims (1)

[Claims] In an information processing system that includes a current main storage device and a backup main storage device and checks for errors in information read from the current main storage device, an address on the current main storage device where information in which an error has been detected is stored is stored. and a collation means that collates the address stored this time by the address storage means with the address stored last time, and when the collation means detects a match between the two addresses, the current main storage device and the backup main storage device, and when the collation means detects a mismatch between the two addresses, the address storage means on the backup main storage device retrieves information from the same address as the currently stored address. A storage information temporary failure detection method characterized in that the currently used main storage device is read out and written to the currently stored address on the current main storage device, and is subsequently used as the current main storage device.