JPS608962A - Temporary fault detecting system of storage information - Google Patents
Temporary fault detecting system of storage informationInfo
- Publication number
- JPS608962A JPS608962A JP58117359A JP11735983A JPS608962A JP S608962 A JPS608962 A JP S608962A JP 58117359 A JP58117359 A JP 58117359A JP 11735983 A JP11735983 A JP 11735983A JP S608962 A JPS608962 A JP S608962A
- Authority
- JP
- Japan
- Prior art keywords
- main storage
- storage device
- address
- main memory
- control device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2017—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where memory access, memory control or I/O control functionality is redundant
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Hardware Redundancy (AREA)
Abstract
Description
【発明の詳細な説明】
(al 発明の技術分野
本発明は二重化された主記憶装置を具備する情報処理シ
ステムに係り、特に二重化された主記憶装置の現用およ
び予備の切替え頻度を極力減少させる記憶情報一時障害
検出方式に関す。DETAILED DESCRIPTION OF THE INVENTION (al) Technical Field of the Invention The present invention relates to an information processing system equipped with a duplicated main memory, and particularly to a memory that minimizes the frequency of switching between the active and spare main memory of the duplicated main memory. Information regarding temporary failure detection method.
fbl 技術の背景
第1図は本発明の対象となる情報処理システムの一例を
示す図である。第1図において、情報処理システムはそ
れぞれ二重化された中央制御装置CCOおよびCC1、
主記憶制御装置MMCOおよびMMCI、並びに主記憶
装置MMOおよびMMlを具備している。現用として動
作中の中央制御装置(例えばCC0)は、主記憶制御語
MM MCOおよびMMCIを介して両生記憶装置MM
OおよびMMIの同一アドレスに同一情報を書込み、現
用主記憶装置(例えばMMO)から情報を読出して所要
の処理を行う。現用主犯備装E、 M M Oが罹障す
ると予備主記憶装置MMIを現用に切替えて処理を継続
する。各主記憶装置MMOおよびMMlに格納される情
報には例えばパリティビットの如き誤り検出符号が付加
されており、各主記憶制御装置MMCOおよびMMCI
はそれぞれ対応する主記憶装置MMOおよびMMIから
読出される情報に対し誤り検査を行う。なお主犯1.a
制御装置MMCOおよびMMCIが検出する誤りには、
主記憶装置MMOおよびMMIの素子障害に起因するも
のと、例えばα線の影響等の一時的な原因によるものと
がある。前者の場合には主記憶装置MMOおよびMMI
の該当素子を交換しないと修復しないが、後者の場合に
は新たな情報を書込めば再び使用可能となる。fbl Technical Background FIG. 1 is a diagram showing an example of an information processing system to which the present invention is applied. In FIG. 1, the information processing system includes dual central control units CCO and CC1,
It includes main memory control units MMCO and MMCI, and main memory units MMO and MMl. The central control unit (for example, CC0) currently operating is connected to the main memory control word MM via the main memory control word MMCO and MMCI.
The same information is written to the same address of O and MMI, the information is read from the current main memory (for example, MMO), and required processing is performed. When the active main criminal equipment E, MMO is affected, the backup main memory device MMI is switched to the active main storage device MMI and processing continues. An error detection code such as a parity bit is added to the information stored in each main memory controller MMCO and MMCI.
perform error checking on information read from the corresponding main memories MMO and MMI, respectively. The main culprit 1. a
Errors detected by the control devices MMCO and MMCI include:
There are two types of failures: one is due to an element failure in the main memory devices MMO and MMI, and the other is a temporary cause such as the influence of alpha rays. In the former case, the main memories MMO and MMI
However, in the latter case, the device can be used again by writing new information.
(c) 従来技術と問題点
従来あるこの種情報処理システムにおいては、現用主記
憶制御装置(例えばMMCO)が現用主記憶装置(例え
ばMMO)から読出した情報に誤りを検出した場合には
、中央制御装置CCOおよびCCIは前述の如き一時障
害の場合にも素子障害の場合と同様に、主記憶制御装置
MMCOおよびMMC1、並びに主記憶装置MMOおよ
びMMIの現用予備切替処理を実行している為、切替処
理に多くの時間を要し、中央制御装置CCOの処理能力
を低下させる欠点があった。(c) Prior Art and Problems In conventional information processing systems of this type, when the current main memory controller (for example, MMCO) detects an error in the information read from the current main memory (for example, MMO), the central Since the control units CCO and CCI execute the current/standby switching process for the main memory control units MMCO and MMC1 and the main memory units MMO and MMI even in the case of a temporary failure as described above, in the same way as in the case of an element failure. This has the disadvantage that the switching process takes a lot of time and reduces the processing capacity of the central control unit CCO.
(d+ 発明の目的
本発明の目的は、前述の如き従来ある情報処理システム
の欠点を除去し、現用予備切替処理を極力除去すること
により中央制御装置の処理能力を向上させることに在る
。(d+ Purpose of the Invention The purpose of the present invention is to eliminate the drawbacks of conventional information processing systems as described above, and to improve the processing capacity of a central control unit by eliminating as much as possible the work/standby switching process.
(el 発明の構成
この目的は、現用および予備主記憶装置を具備し、該現
用主記憶装置から読出す情報の誤りを検査する情報処理
システムにお、いて、誤りが検出された情報の格納され
ていた前記現用主記憶装置上のアドレスを記憶するアド
レス記憶手段と、該アドレス記憶手段が今回記憶したア
ドレスと前回記憶したアドレスとを照合する照合手段と
を設&−1、該照合手段が前記両アドレスの一致を検出
した場合には前記現用主記憶装置と前記予備主記憶装置
とを切替えて使用し、前記照合手段が前記両アドレスの
不一致を検出した場合には前記予備主記憶装置上の前記
アドレス記憶手段が今回記↑aしたアドレスと同一のア
ドレスから情報を読出して前記現用主記憶装置上の前記
今回記憶したアドレスに書込み、引続き現用主記憶装置
として使用することにより達成される。(el) Structure of the Invention The object of the present invention is to provide an information processing system that includes a current main storage device and a backup main storage device, and checks for errors in information read from the current main storage device, in which information in which an error has been detected is stored. an address storage means for storing an address on the current main storage device that has been previously stored; and a collation means for collating the address stored this time by the address storage means with the address stored last time; If the matching means detects a match between the two addresses, the current main storage device and the backup main storage device are switched for use; This is achieved by the address storage means reading information from the same address as the address ↑a, writing it into the currently stored address on the current main storage device, and continuing to use it as the current main storage device.
ff) 発明の実施例 以下、本発明の一実施例を図面により説明する。ff) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.
第2図は本発明の一実施例による主記憶制御装置を示す
図であり、第3図は本発明の一実施例による中央制御装
置を示す図である。なお、全図を通じて同一符号は同一
対象物を示す。また第1図におけると同様0系が現用、
1系が予備とする。第2図において、初期状態ではフリ
ップフロップFFルジスタREGOおよびIREGIは
共にリセット状態に設定される。主記憶制御装置MMC
O内のパリティ検査回路PCが主記憶装置MM。FIG. 2 is a diagram showing a main memory control device according to an embodiment of the present invention, and FIG. 3 is a diagram showing a central control device according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures. Also, as in Figure 1, the 0 series is currently in use,
1 series will be reserved. In FIG. 2, in the initial state, both flip-flop FF registers REGO and IREGI are set to the reset state. Main memory controller MMC
The parity check circuit PC in O is the main memory MM.
のアドレスaから読出した情報に誤りを検出し、誤り検
出信号eを出力すると、フリップフロップFFがセント
状態となり、レジスタREGOを付勢する。その結果レ
ジスタREGOは主記憶制御装置MMCOが主記憶装置
MMOに伝達したアドレスaを蓄積する。照合回路MA
TはレジスタREGOおよびREGIの蓄積内容を照合
し、両者が不一致であることを検出して論理値Oの照合
信号mを出力する。その結果ゲートG1が導通状態、ゲ
ートG2が阻止状態に設定される。一方誤り検出信号e
は、遅延回路DLにより照合回路MATが照合結果に基
づき照合信号mの論理値を設定するに充分な遅延時間を
有する遅延回路DLを経由した後、ゲー1−GOおよび
ゲートG1を経由して一時障害検出信号e1として中央
制御装置CCOに伝達される。第3図において、主記憶
制御装置MMCOから伝達された一時障害検出信号e1
は、特殊マイクロアドレス発生回路MASおよびマイク
ロアドレス制御回路CTLに伝達される。特殊マイクロ
アドレス発生回路MASは、制御メモリCM内に格納さ
れている複写マイクロプログラムMPIの先頭アドレス
をシーケンサSEQに伝達する。その結果シーケンサS
EQは、制御メモリCMから複写マイクロプログラムM
PIを構成するマイクロ命令を順次読出し、マイクロ命
令レジスタCMIRに蓄積させる。中央制御装置CCO
ば、マイクロ命令レジスタCM I’ Rに蓄積される
複写マイクロプログラムMPIの各マイクロ命令を実行
することにより、主記憶制御装置MMCIを介して主記
憶装置MMIの同一アドレスaがら情報を読出すと共に
、主記憶制御装置MMCOに対し、主記憶装置MMlか
ら続出した情報を主記憶装置MMOの該当アドレスaに
書込ませた後、引続き主記憶制御装置MMCOおよび主
記憶装置MMOを現用系として使用する。パリティ検査
回路pcが検出した誤りが主記憶装置MMOのアドレス
aに発生した一時障害に起因するものであれば、主記憶
装置MMIがら読出した情報を書込むことによりアドレ
スaには正常な情報が格納され、再び中央制御装置CC
Oが主記憶装置MMOの該当アドレスaから情報を読出
した場合には、パリティ検査回路pcは誤り検出信号e
を出力することは無い。一方パリティ検査回路PCが検
出した誤りが主記憶装置MMOのアドレスaに発生した
素子障害に起因するものであれば、主記憶装置MM1か
ら読出した情報を書込んでもアドレスaには依然として
正常な情報は格納されず、再び中央制御装置CCOが主
記憶装置MMOの該当アドレスaから情報を読出した場
合にも、パリティ検査回路pcは誤り検出信号eを出力
する。その結果フリップフロップFFはリセット状態と
なり、レジスタREGIを付勢する。従ってレジスタR
EG1は主記憶制御装置MMCOが主記憶装置MMOに
伝達したアドレスaを蓄積する。照合回路MATはレジ
スタREGOおよびREGIの蓄積内容を照合し、両者
が一致したことを検出して論理値1の照合信号mを出力
する。その結果ゲートG2は溝道状態、ゲー)Glは阻
止状態に設定される。一方誤り検出信号eは、遅延回F
IPfDLにより前記遅延時間を有する遅延回路DLを
経由した後、ゲートGOおよびゲー)G2を経由して素
子障害検出信号e2として中央制御装置CCOに伝達さ
れる。第3図において、主記憶制御装置MMCOから伝
達された素子障害検出信号e2は、公知の方法により対
応する割込原因フリップフロップ■SFをセット状態と
する。割込マイクロアドレス発生回路M/lは、制御メ
モリCM内に格納されている割込マイクロプログラムM
P2の先頭アドレスをシーケンサSEQに伝達する。そ
の結果シーケンサSEQは、制御メモリCMから割込マ
イクロプログラムMP2を構成するマイクロ命令を順次
読出し、マイクロ命令レジスタCMIRに蓄積させる。When an error is detected in the information read from address a and an error detection signal e is output, flip-flop FF enters the cent state and energizes register REGO. As a result, register REGO stores address a transmitted from main memory control device MMCO to main memory device MMO. Verification circuit MA
T compares the stored contents of registers REGO and REGI, detects that they do not match, and outputs a check signal m of logical value O. As a result, gate G1 is set to a conductive state and gate G2 is set to a blocked state. On the other hand, error detection signal e
is temporarily passed through the delay circuit DL which has a delay time sufficient for the verification circuit MAT to set the logic value of the verification signal m based on the verification result by the delay circuit DL, and then through the gate 1-GO and the gate G1. The fault detection signal e1 is transmitted to the central control unit CCO. In FIG. 3, a temporary failure detection signal e1 transmitted from the main memory controller MMCO
is transmitted to special microaddress generation circuit MAS and microaddress control circuit CTL. The special microaddress generation circuit MAS transmits the start address of the copy microprogram MPI stored in the control memory CM to the sequencer SEQ. As a result, sequencer S
EQ is the copy microprogram M from the control memory CM.
The microinstructions constituting the PI are sequentially read out and stored in the microinstruction register CMIR. Central control unit CCO
For example, by executing each microinstruction of the copy microprogram MPI stored in the microinstruction register CMI'R, information is read from the same address a of the main memory device MMI via the main memory control device MMCI, and After causing the main memory control device MMCO to write the information successively received from the main memory device MMl to the corresponding address a of the main memory device MMO, the main memory control device MMCO and the main memory device MMO are continued to be used as the active system. If the error detected by the parity check circuit pc is due to a temporary failure that occurred at address a of the main memory MMO, normal information can be restored to address a by writing the information read from the main memory MMI. stored and returned to the central control unit CC
When O reads information from the corresponding address a of the main memory MMO, the parity check circuit pc outputs an error detection signal e.
There is no output. On the other hand, if the error detected by the parity check circuit PC is due to an element failure that occurred at address a of the main memory MMO, even if the information read from the main memory MM1 is written, there will still be normal information at address a. is not stored and the central control unit CCO again reads information from the corresponding address a of the main memory MMO, the parity check circuit pc outputs the error detection signal e. As a result, flip-flop FF enters the reset state and energizes register REGI. Therefore register R
EG1 stores the address a transmitted from the main memory control device MMCO to the main memory device MMO. The collation circuit MAT collates the stored contents of the registers REGO and REGI, detects that they match, and outputs a collation signal m having a logic value of 1. As a result, the gate G2 is set to the channel state, and the gate G1 is set to the blocking state. On the other hand, the error detection signal e is the delay time F
After passing through the delay circuit DL having the delay time by IPfDL, it is transmitted to the central control unit CCO as an element failure detection signal e2 via the gate GO and the gate G2. In FIG. 3, the element failure detection signal e2 transmitted from the main memory controller MMCO sets the corresponding interrupt causing flip-flop SF by a known method. The interrupt microaddress generation circuit M/l executes an interrupt microprogram M stored in the control memory CM.
The start address of P2 is transmitted to the sequencer SEQ. As a result, the sequencer SEQ sequentially reads the microinstructions constituting the interrupt microprogram MP2 from the control memory CM and stores them in the microinstruction register CMIR.
中央制御装置CCOは、マイクロ命令レジスタCMIR
に蓄積される割込マイクロプログラムMP2の各マイク
ロ命令を実行することにより、所要の割込処理プログラ
ムを起動し、主記憶制御装置MMC1および主記憶゛装
置MMIを現用とし、主記憶制御装置MMCOおよび主
記憶装置MMOを予備系とする現用予備切替処理を実行
する。The central control unit CCO has a microinstruction register CMIR.
By executing each microinstruction of the interrupt microprogram MP2 stored in the interrupt microprogram MP2, the required interrupt processing program is started, the main memory control unit MMC1 and the main memory unit MMI are made active, and the main memory control units MMCO and Execute the current/standby switching process using the main storage device MMO as the standby system.
以上の説明から明らかな如く、本実施例によれば、主記
憶制御装置MMCOは主記憶装置MMOの同一アドレス
aがら続出した情報が連続してパリティ検査回路PCに
より誤り検出されなかった場合には中央制御装置CCO
に一時障害検出信号e1を伝達し、一時障害検出信号e
1を受信した中央制御装置CCOは主記憶装置MMIの
同一アドレスaから一時的に情報を読出すと共に該情報
を主記憶装置MMOの該当アドレスaに書込ませ、また
主記憶装置MMOの同一アドレスaがら続出した情報が
連続してパリティ検査回路PCにより誤り検出された場
合には中央制御装置CCOに素子障害検出信号e2を伝
達し、素子障害検出信号e2を受信した中央制御装置C
COは初めて主記憶制御装置MMCIおよび主記憶装置
MMIを現用、主記憶制御装置MMCOおよび主記憶装
置MMOを予備とする切替処理を実行する。その結果中
央制御装置CCOは主記憶装置MMOの一時障害の際に
切替処理を実行する必要が無くなり、負荷が軽減される
。As is clear from the above description, according to the present embodiment, the main memory control unit MMCO performs the following operations when consecutive pieces of information from the same address a of the main memory unit MMO are not detected as errors by the parity check circuit PC. Central control unit CCO
The temporary failure detection signal e1 is transmitted to the temporary failure detection signal e1.
1, the central control unit CCO temporarily reads information from the same address a of the main memory MMI, writes the information to the corresponding address a of the main memory MMO, and also writes the information to the corresponding address a of the main memory MMO. If the parity check circuit PC successively detects an error in the information that has been continuously received from a to
For the first time, the CO executes a switching process in which the main memory control device MMCI and the main memory device MMI are used as active, and the main memory control device MMCO and the main memory device MMO are used as backup. As a result, the central control unit CCO does not need to perform switching processing in the event of a temporary failure in the main memory unit MMO, and the load is reduced.
なお、第2図および第3図はあく迄本発明の一実施例に
過ぎず、例えば現用系はθ系に限定されることは無く、
1系の場合にも本発明の効果は変らない。また主記憶制
御装置および中央制御装置の構成は図示されるものに限
定されることは無く、他に幾多の変形が考慮されるが、
何れの場合にも本発明の効果は変らない。Note that FIGS. 2 and 3 are only one embodiment of the present invention; for example, the currently used system is not limited to the θ system;
Even in the case of 1 system, the effects of the present invention do not change. Furthermore, the configurations of the main memory control device and the central control device are not limited to those shown in the drawings, and many other modifications may be considered.
In either case, the effects of the present invention remain the same.
(gl 発明の効果
以上、本発明によれば、前記情報処理システムにおいて
、中央制御装置は主記憶装置の一時障害に起因する誤り
を検出した場合には現用予備切替処理を実行する必要が
無くなり、上記4.1装置の素子障害に起因する誤りを
検出した場合にのみ現用予備切替処理を実行することと
なり、負荷が軽減され、当該中央制御装置、即ち情報処
理システムの処理能力が向上する。(gl) Effects of the Invention According to the present invention, in the information processing system, when the central control unit detects an error caused by a temporary failure of the main storage device, there is no need to execute the working/standby switching process; The working/standby switching process is executed only when an error caused by an element failure in the above 4.1 device is detected, which reduces the load and improves the processing capacity of the central control unit, that is, the information processing system.
第1図は本発明の対象となる情報処理システムの一例を
示す図、第2図は本発明の一実施例による主記憶制御装
置を示す図、第3図は本発明の一実施例による中央制御
装置を示す図である。
図において、CCOおよびCC1は中央制御装置、CM
は制御メモリ、CMTRはマイクロ命令レジスタ、CT
Lはマイクロアドレス制御回路、DLは遅延回路、e
ば誤り検出信号、elば一時障害検出信号、e2は素子
障害検出信号、FFはフリップフロップ、Go乃至G2
はゲート、TRは命令レジスタ、TSFは割込原因フリ
ップフロップ、mは照合信号、MAIは割込マイクロア
ドレス発生回路、MASは特殊マイクロアドレス発生回
路、MATは照合回路、MMOおよびMMIは主記憶装
置、MMCOおよびMMCIは主記憶制御装置、MPI
は複写マイクロプログラム、MB2は割込マイクロプロ
グラム、PCはパリティ検査回路、REGOおよびRE
GIはレジスフ、を示す。
1
峯 1 図
≠ 2 記
2
第 3 図FIG. 1 is a diagram showing an example of an information processing system to which the present invention is applied, FIG. 2 is a diagram showing a main memory control device according to an embodiment of the present invention, and FIG. 3 is a diagram showing a main memory control device according to an embodiment of the present invention. It is a figure showing a control device. In the figure, CCO and CC1 are the central controller, CM
is control memory, CMTR is microinstruction register, CT
L is a microaddress control circuit, DL is a delay circuit, e
is an error detection signal, el is a temporary failure detection signal, e2 is an element failure detection signal, FF is a flip-flop, Go to G2
is a gate, TR is an instruction register, TSF is an interrupt cause flip-flop, m is a verification signal, MAI is an interrupt microaddress generation circuit, MAS is a special microaddress generation circuit, MAT is a verification circuit, MMO and MMI are main memory devices , MMCO and MMCI are main memory controllers, MPI
is a copy microprogram, MB2 is an interrupt microprogram, PC is a parity check circuit, REGO and RE
GI stands for Regisf. 1 Mine 1 Figure ≠ 2 Note 2 Figure 3
Claims (1)
から読出す情報の誤りを検査する情報処理システムにお
いて、誤りが検出された情報の格納されていた前記現用
主記憶装置上のアドレスを記憶するアドレス記憶手段と
、該アドレス記憶手段が今回記憶したアドレスと前回記
憶したアドレスとを照合する照合手段とを設け、該照合
手段が前記両アドレスの一致を検出した場合には前記現
用主記憶装置と前記予備主記憶装置とを切替えて使用し
、前記照合手段が前記両アドレスの不一致を検出した場
合には前記予備主記憶装置上の前記アドレス記憶手段が
今回記憶したアドレスと同一のアドレスから情報を読出
して前記現用主記憶装置上の前記今回記憶したアドレス
に書込み、引続き現用主記憶装置として使用することを
特徴とする記憶情報一時障害検出方式。In an information processing system that includes a current main storage device and a backup main storage device and checks for errors in information read from the current main storage device, an address on the current main storage device where information in which an error has been detected is stored is stored. and a collation means that collates the address stored this time by the address storage means with the address stored last time, and when the collation means detects a match between the two addresses, the current main storage device and the backup main storage device, and when the collation means detects a mismatch between the two addresses, the address storage means on the backup main storage device retrieves information from the same address as the currently stored address. A storage information temporary failure detection method characterized in that the currently used main storage device is read out and written to the currently stored address on the current main storage device, and is subsequently used as the current main storage device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58117359A JPS608962A (en) | 1983-06-29 | 1983-06-29 | Temporary fault detecting system of storage information |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58117359A JPS608962A (en) | 1983-06-29 | 1983-06-29 | Temporary fault detecting system of storage information |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS608962A true JPS608962A (en) | 1985-01-17 |
Family
ID=14709725
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58117359A Pending JPS608962A (en) | 1983-06-29 | 1983-06-29 | Temporary fault detecting system of storage information |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS608962A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03269745A (en) * | 1990-03-20 | 1991-12-02 | Yokogawa Electric Corp | Duplex processor system |
US8667372B2 (en) | 2006-08-18 | 2014-03-04 | Fujitsu Limited | Memory controller and method of controlling memory |
-
1983
- 1983-06-29 JP JP58117359A patent/JPS608962A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03269745A (en) * | 1990-03-20 | 1991-12-02 | Yokogawa Electric Corp | Duplex processor system |
US8667372B2 (en) | 2006-08-18 | 2014-03-04 | Fujitsu Limited | Memory controller and method of controlling memory |
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